Ordering number : EN4929A CMOS LSI LC75366, 75366M Two-Channel Electronic Volume Control Overview Package Dimensions The LC75366 (DIP20) and the LC75366M (MFP20) are electronic volume controls that can be controlled by serial input data and provide volume, balance and loudness functions. unit: mm 3021B-DIP20 [LC75366] Features • Silicon gate CMOS process for low switching noise Functions • Volume: 0 dB to –68 dB (in 2 dB steps) and –∞; 36 positions. A balance function can be implemented by controlling the left and right channel volume settings independently. • Loudness: Taps are provided at the –20 dB positions in the 10 dB step resistor ladder used by the volume control function. A loudness function can be implemented by attaching external RC circuits at these tap points. • An address selection pin (the S pin) allows two LC75366 chips to be used on the same bus. • Serial data input: Supports CCB* format communication with the system controller. SANYO: DIP20 unit: mm 3036B-MFP20 [LC75366M] • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Specifications SANYO: MFP20 Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Maximum input voltage Allowable power dissipation Symbol Conditions VDD max VDD VIN max1 VIN max2 Pd max Ratings Unit 12 V CL, DI, CE, S VSS – 0.3 to VDD + 0.3 V L10dBIN, L2dBIN, R10dBIN, R2dBIN VSS – 0.3 to VDD + 0.3 Ta ≤ 85°C 140 V mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –50 to +125 °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 63096HA (OT)/62095HA (OT) No. 4929-1/11 LC75366, 75366M Allowable Operating Ranges at Ta = 25°C, VSS = 0 V Parameter Symbol Supply voltage VDD Input high level voltage Input low level voltage Input voltage amplitude Input pulse width Conditions Ratings VDD Unit 4.0 to 11.0 V 0.3 VDD + 1 to VDD V VIH (1) CL, DI, CE VIH (2) S 0.8 VDD to VDD V VIL (1) CL, DI, CE VSS to 0.2 VDD V VIL (2) S VSS to 0.2 VDD VIN L10dBIN, L2dBIN, R10dBIN, R2dBIN tøW V VSS to VDD Vp-p CL 1 or longer µs Setup time tset up CL, DI, CE 1 or longer µs Hold time thold CL, DI, CE 1 or longer µs Operating frequency fop CL Up to 500 kHz Electrical Characteristics at Ta = 25°C, VSS = 0 V Parameter Symbol Output at maximum attenuation Total resistance typ max Unit 0.006 % THD (2) VIN = 1 Vrms, f = 20 kHz, all settings flat overall, VDD = 9 V 0.015 % CT VIN = 1 Vrms, f = 20 kHz, all settings flat overall, Rg = 1 kΩ 85 dB –80 dB VO min VIN = 1 Vrms, f = 20 kHz, volume setting: –∞, with a 470 µF capacitor between L/R Vref and VSS RVOL (1) 10 dB steps RVOL (2) 2 dB steps Output off leakage current Ioff L10dBIN, R10dBIN, LCT1, L2dBIN, R2dBIN, RCT1, L10dBOUT, R10dBOUT, LCT2, L2dBOUT, R2dBOUT, RCT2, LVref, RVref Input high level current IIH VI = VDD (CL, CE and DI pins) Input low level current IIL VI = VSS (CL, CE and DI pins) Output noise voltage VN All settings flat overall (IHF-A), VDD = 9 V, Rg = 1 kΩ Current drain IDD VDD – VSS = 11 V CT1 Analog switch on resistance (Design target value) min THD (1) Total harmonic distortion Crosstalk Conditions VIN = 1 Vrms, f = 1 kHz, all settings flat overall, VDD = 9 V RON For use between CT2 and Vref 28.2 47 65.8 kΩ 12 20 28 kΩ +10 µA –10 10 –10 µA µA 2 10 µV 1 mA 180 300 420 Ω 90 150 210 Ω 0 dB, –∞ 0.6 1.0 1.4 kΩ Other than the above 6.0 10.0 14.0 kΩ Pin Assignment No. 4929-2/11 LC75366, 75366M Equivalent Circuit Block Diagram Test Circuits 1. Total harmonic distortion No. 4929-3/11 LC75366, 75366M 2. Output noise voltage 3. Crosstalk No. 4929-4/11 LC75366, 75366M Volume Block Equivalent Circuit No. 4929-5/11 LC75366, 75366M Pin Functions Pin No. Symbol 1 L10dBIN 20 R10dBIN 2 LCT1 3 LCT2 19 RCT1 18 RCT2 4 L10dBOUT Function Note Input pins for the 10 dB step attenuator. Must be driven from a low impedance. Loudness connections. Connect a high band compensation capacitor between CT1 and 10dBIN and connect a low band compensation capacitor between CT2 and Vref. Output pins for the 10 dB step attenuator. These outputs must be received by a load of about 1 MΩ. 17 R10dBOUT 5 L2dBIN 16 R2dBIN 6 L2dBOUT Input pins for the 2 dB step attenuator. Must be driven from a low impedance. Output pins for the 2 dB step attenuator. These outputs must be received by a load of about 1 MΩ. 15 R2dBOUT 7 LVref 14 RVref 12 S 9 CL 10 DI 11 CE 8 VDD 13 VSS Volume circuit common pins. The impedance of the pattern connected to these pins should be kept as low as possible. Since the capacitors between Vref and VSS form the residual resistance components when the volume is cut, adequate care must be taken in determining the value of these capacitors. Pin that selects the address code in the data format. Data will be accepted for an address code of 88 when this pin is tied to VDD, and for an address code of 89 when tied to VSS. Serial data and clock inputs for control Chip enable. The internally latched data is written and the analog switches operate when this pin goes from high to low. Data transfer is enabled when this pin is at the high level. These pins must be connected to the power supply. No. 4929-6/11 LC75366, 75366M Control System Timing and Data Format Apply the stipulated serial data to the CE, CL and DI pins to control the LC75366 and LC75366M. The data consists of 20 bits, of which 8 bits are the address and 12 bits are control data. No. 4929-7/11 LC75366, 75366M Sample Application Circuit No. 4929-8/11 LC75366, 75366M No. 4929-9/11 LC75366, 75366M Loudness Function External Circuit Constant Calculation Example First, refer to the LC75366 and LC75366M 10 dB step internal equivalent circuit shown on page 5. Figure 1 below shows this circuit simplified with the external components used for the loudness function connected for this calculation. The sample calculation below uses this diagram to acquire a 5 dB boost at f = 100 Hz. (f = 100 Hz, 5 dB boost) Let R and C in Figure 1 be: R1 = R2 = 10 kΩ R3 = 1 kΩ C1 = Z1, C2 = Z2 Then: R2 (R3 + Z2) R2 + R3 + Z2 VOUT = = –20 dB R1 · Z1 R2 (R3 + Z2) (at = 1 kHz) + R1 + Z1 R2 + R3 + Z2 R2 (R3 + 10 · Z2) R2 + R3 + 10 · Z2 VOUT = = –15 dB R1 · 10 · Z1 R2 (R3 + 10 · Z2) (at = 100 Hz) + R1 + 10 · Z1 R2 + R3 + 10 · Z2 Solving the above equations gives: Z1 ≠ 178.3 kΩ and Z2 = 176 Ω No. 4929-10/11 LC75366, 75366M Therefore, under such conditions where f = 1 kHz, specifications may be satisfied if C (capacitor) having these impedances is supplied externally. The result is that C1 = 893 pF and C2 = 0.9 µF. Figure 1 Usage Notes 1. The states of the internal analog switches will be indeterminate when power is first applied. Muting should be applied externally until control data has been transferred and stored. 2. The signal lines for the CL, DI and CE pins should either be covered by the pattern ground or be formed from shielded cable to prevent the high-frequency digital signals transmitted over these lines from entering the analog system. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 4929-11/11