Ordering number : ENN7053 CMOS IC LC75412E, 75412W Electronic Volume Controller for Car Audio Systems Overview Features The LC75412E and 75412W are electronic volume controllers that enable control of volume, balance, fader, bass/treble, loudness, input switching, and input gain using only a small number of external components. • On-chip buffer amplifier cuts down number of external components • Low switching noise generated by on-chip switch through use of silicon gate CMOS process, for low switching noise when there is no signal • Low switching noise when there is a signal due to use of on-chip zero-cross switching circuit • On-chip 1/2 VDD reference voltage circuit • Controls performed with serial input (CCB) Functions • Volume: 0 dB to –79 dB in 1-dB steps, and –∞ (81 positions) Balance function with separate L/R control • Fader: rear output or front output can be attenuated across 16 positions (in 1-dB steps from 0 dB to –2 dB, 2-dB steps from –2 dB to –20 dB, 10-dB steps from –20 dB to –30 dB, and –45 dB, –60 dB, –∞) • Bass/treble: Each band can be controlled in 2-dB steps from ±0 dB to ±18 dB. • Input gain: 0 dB to +18.75 dB (1.25-dB steps) amplification is possible for the input signal. • Input switching: Six input signals can be selected for Left and for Right (five are singleended inputs and one is a differential input.) • Loudness: A tap is output from the –32 dB position of a volume control resistor ladder. A loudness function can be implemented by connecting an external RC circuit. • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN O1901RM (OT) No. 7053-1/21 LC75412E, 75412W Package Dimensions unit: mm unit: mm 3159-QIP64E 3190-SQFP64 [LC75412E] [LC75412W] 17.2 0.8 1.0 1.6 1.0 14.0 0.35 1.25 0.15 33 0.8 0.5 14.0 12.0 1.25 32 10.0 15.6 0.1 2.7 1 16 0.1 16 1.25 1 17 64 3.0max 64 1.7max 1.6 1.0 32 17 1.0 0.5 48 49 48 49 17.2 1.25 0.15 33 12.0 10.0 0.18 0.5 0.8 0.5 SANYO: SQFP64 SANYO: QIP64E LTOUT LF3C3 LF3C2 LF3C1 NC NC NC LF1C3 LF1C2 LF1C1 NC NC NC LCT LVRIN LSELO Pin Assignment 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 L5P 49 32 LFIN L5M 50 31 LFOUT L4 51 30 LROUT L3 52 29 LAVSS L2 53 28 TEST L1 54 27 DVSS L6 55 26 CL VDD 56 25 DI LC75412E/W Vref 57 24 CE 19 RROUT R5M 63 18 RFOUT R5P 64 17 RFIN 8 9 10 11 12 13 14 15 16 RTOUT 7 RF3C3 6 RF3C2 5 RF3C1 4 NC 3 NC 2 NC 1 RF1C3 R4 62 RF1C2 20 TIM RF1C1 R3 61 NC 21 NC NC R2 60 NC 22 RAVSS RCT R1 59 RVRIN 23 MUTE RSELO R6 58 No. 7053-2/21 22µF R5P + R3 + R5M R2 + R4 R1 + + R6 + 64 + RVref LVref 10 NC 9 RF1C3 8 RF1C2 7 RF1C1 6 NC NC NC RVRIN RSELO 1000pF 12 11 NC 5 0.1µF NC 4 13 14 ZEROCROSS DET 15 LOGIC CIRCUIT 34 RF3C3 1µF 3 RCT 2 CONTROL CIRCUIT 35 ZEROCROSS DET 36 16 33 RVref 1 RVref Multiplexer Multiplexer 37 38 39 LVref 63 62 61 60 59 58 57 56 55 54 LVref + Vref L6 + 53 LVref + L1 + VDD L2 + LVref 40 10µF NO SIGNAL TIMER CCB INTERFACE 10µF 47kΩ 1µF × 7 1µF × 7 52 51 LSELO L3 LVRIN + LCT L4 NC + NC 50 NC L5M LF1C1 49 10kΩ NC L5P 0.1µF 41 LF1C2 42 NC NC + 1kΩ LF1C3 43 LF3C1 + 0.33µF 44 0.1µF 45 0.001µF 46 LF3C2 47 0.001µF LF3C3 48 LTOUT + 1000pF 1µF TEST LAVSS LROUT LFOUT LFIN DI CL RAVSS RFOUT RROUT TIM 17 RFIN 18 19 20 21 NC 22 23 MUTE 24 CE 25 26 27 DVSS 28 29 30 31 32 CE DI CL PA PA 10µF 10µF PA PA 0.033µF µCOM 10µF 10µF LC75412E, 75412W Equivalent Circuit Block Diagram/Sample Application Circuit 1MΩ RTOUT 0.001µF RF3C2 RF3C1 0.001µF 0.1µF 1kΩ 0.33µF 10kΩ RVref + RVref No. 7053-3/21 LC75412E, 75412W Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions Maximum supply voltage VDD max VDD Maximum input voltage VIN max All input pins Allowable power dissipation Pd max Ta ≤ 85°C, when mounted on board Ratings Unit 11 V VSS – 0.3 to VDD + 0.3 V QIP64E 680 SQFP64 800 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –50 to +125 °C Allowable Operating Ranges at Ta = 25°C, VSS = 0 V Parameter Symbol Ratings Conditions min typ max Unit Supply voltage VDD VDD 6.0 10 V Input high-level voltage VIH CL, DI, CE 4.0 10 V Input low-level voltage VIL CL, DI, CE VSS 1.0 V Input amplitude voltage VIN VSS VDD Vp-p Input pulse width CL 1 µs Setup time Tsetup TøW CL, DI, CE 1 µs Hold time Thold CL, DI, CE 1 Operating frequency fopg CL µs 500 kHz Electrical Characteristics at Ta = 25°C, VDD = 9 V, VSS = 0 V Parameter Symbol Pin Name Conditions Ratings min typ max Unit [Input block] Input resistance Rin L1 to L4, L6, R1 to R4, R6 25 50 100 kΩ Minimum input gain Ginmin L1 to L4, L6, R1 to R4, R6 –1 0 +1 dB Maximum input gain Ginmax +16.5 +18.75 +21 dB ATerr ±0.5 dB BAL ±0.5 dB Step setting error L/R balance [Volume Block] Input resistance Step setting error L/R balance 100 kΩ ATerr Rvr LVRIN, RVRIN, loudness off 25 50 ±0.5 dB BAL ±0.5 dB [Tone block] Step setting error ATerr ±1.0 dB Bass control range Gbass max. boost/cut ±15 ±18 ±21 dB Treble control range Gtre max. boost/cut ±15 ±18 ±21 dB L/R balance BAL ±0.5 dB Continued on next page. No. 7053-4/21 LC75412E, 75412W Continued from preceding page. Parameter Symbol Pin Name Conditions Ratings min typ max Unit [Fader Block] Input resistance Rfed LFIN, RFIN 25 50 100 0dB to –2dB Step setting error L/R balance dB ±1 dB –2dB to –20dB ATerr kΩ ±0.5 –20dB to –30dB ±2 dB –30dB to –60dB ±3 dB ±0.5 dB % BAL [General] Total harmonic distortion Input crosstalk L/R crosstalk Maximum attenuated output Output noise voltage THD (1) VIN = 0dBV, f = 1 kHz 0.004 0.01 THD (2) VIN = –10dBV, f = 10 kHz 0.006 0.01 VIN = 1Vrms, f = 1 kHz 80 88 dB CT VIN = 1Vrms, f = 1 kHz 80 88 dB Vomin (1) VIN = 1Vrms, f = 1 kHz 80 88 dB VIN = 1Vrms, f = 1 kHz Vomin (2) INMUTE, fader –∞ 90 95 dB VN (1) Flat overall, IHF-A filter 5 10 VN (2) Flat overall, 20 to 20 kHzBPF 7 15 µV 55 60 mA 10 µA Current drain IDD Input high-level current IIH CL, DI, CE, VIN = 9 V Input low-level current IIL CL, DI, CE, VIN = 0 V –10 THD = 1%, RL = 10 kΩ flat overall, fIN = 1 kHz 2.3 Maximum input voltage VCL Common-mode rejection ratio % CT CMRR VIN = 0 dB, f = 1 kHz µV µA 2.5 Vrms 70 dB Control Timing and Data Format To control the LC75412E and LC75412W input specified serial data to the CE, CL, and DI pins. The data configuration consists of a total of 52 bits broken down into 8 address bits and 44 data bits. CE DI B0 B1 B2 B3 A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D38 D39 D40 D41 D42 D43 CL 1µs 1µs 1µs min min min CE CL 1µs min 1µs min DI 1µs min ≤ TDEST No. 7053-5/21 LC75412E, 75412W Address code (B0 to A3) The LC75412E and 75412W use 8-bit address code and can be used in common with ICs that support SANYO’s CCB serial bus. Address Code (LSB) B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 0 0 0 1 (81HEX) Control code allocation Input Switching Control D0 D1 D2 Setting 0 0 0 L1 (R1) 1 0 0 L2 (R2) 0 1 0 L3 (R3) 1 1 0 L4 (R4) 0 0 1 L5 (R5) 1 0 1 L6 (R6) D3 Setting Bit for IC testing: Normally set to 0 Input Gain Control D4 D5 D6 D7 0 0 0 0 0dB Operation 1 0 0 0 +1.25dB 0 1 0 0 +2.50dB 1 1 0 0 +3.75dB 0 0 1 0 +5.00dB 1 0 1 0 +6.25dB 0 1 1 0 +7.50dB 1 1 1 0 +8.75dB 0 0 0 1 +10.0dB 1 0 0 1 +11.25dB 0 1 0 1 +12.5dB 1 1 0 1 +13.75dB 0 0 1 1 +15.0dB 1 0 1 1 +16.25dB 0 1 1 1 +17.5dB 1 1 1 1 +18.75dB No. 7053-6/21 LC75412E, 75412W Volume Control (0 to –40dB) D8 D9 D10 D11 D12 D13 D14 D15 0 0 0 0 0 0 0 0 0dB Operation 1 0 0 0 0 0 0 0 –1dB 0 1 0 0 0 0 0 0 –2dB 1 1 0 0 0 0 0 0 –3dB 0 0 1 0 0 0 0 0 –4dB 1 0 1 0 0 0 0 0 –5dB 0 1 1 0 0 0 0 0 –6dB 1 1 1 0 0 0 0 0 –7dB 0 0 0 1 0 0 0 0 –8dB 1 0 0 1 0 0 0 0 –9dB 0 1 0 1 0 0 0 0 –10dB 1 1 0 1 0 0 0 0 –11dB 0 0 1 1 0 0 0 0 –12dB 1 0 1 1 0 0 0 0 –13dB 0 1 1 1 0 0 0 0 –14dB 1 1 1 1 0 0 0 0 –15dB 0 0 0 0 1 0 0 0 –16dB 1 0 0 0 1 0 0 0 –17dB 0 1 0 0 1 0 0 0 –18dB 1 1 0 0 1 0 0 0 –19dB 0 0 1 0 1 0 0 0 –20dB 1 0 1 0 1 0 0 0 –21dB 0 1 1 0 1 0 0 0 –22dB 1 1 1 0 1 0 0 0 –23dB 0 0 0 1 1 0 0 0 –24dB 1 0 0 1 1 0 0 0 –25dB 0 1 0 1 1 0 0 0 –26dB 1 1 0 1 1 0 0 0 –27dB 0 0 1 1 1 0 0 0 –28dB 1 0 1 1 1 0 0 0 –29dB 0 1 1 1 1 0 0 0 –30dB 1 1 1 1 1 0 0 0 –31dB 0 0 0 0 0 1 0 0 –32dB 1 0 0 0 0 1 0 0 –33dB 0 1 0 0 0 1 0 0 –34dB 1 1 0 0 0 1 0 0 –35dB 0 0 1 0 0 1 0 0 –36dB 1 0 1 0 0 1 0 0 –37dB 0 1 1 0 0 1 0 0 –38dB 1 1 1 0 0 1 0 0 –39dB 0 0 0 1 0 1 0 0 –40dB No. 7053-7/21 LC75412E, 75412W Volume Control (–41 to –∞dB) D8 D9 D10 D11 D12 D13 D14 D15 1 0 0 1 0 1 0 0 –41dB Operation 0 1 0 1 0 1 0 0 –42dB 1 1 0 1 0 1 0 0 –43dB 0 0 1 1 0 1 0 0 –44dB 1 0 1 1 0 1 0 0 –45dB 0 1 1 1 0 1 0 0 –46dB 1 1 1 1 0 1 0 0 –47dB 0 0 0 0 1 1 0 0 –48dB 1 0 0 0 1 1 0 0 –49dB 0 1 0 0 1 1 0 0 –50dB 1 1 0 0 1 1 0 0 –51dB 0 0 1 0 1 1 0 0 –52dB 1 0 1 0 1 1 0 0 –53dB 0 1 1 0 1 1 0 0 –54dB 1 1 1 0 1 1 0 0 –55dB 0 0 0 1 1 1 0 0 –56dB 1 0 0 1 1 1 0 0 –57dB 0 1 0 1 1 1 0 0 –58dB 1 1 0 1 1 1 0 0 –59dB 0 0 1 1 1 1 0 0 –60dB 1 0 1 1 1 1 0 0 –61dB 0 1 1 1 1 1 0 0 –62dB 1 1 1 1 1 1 0 0 –63dB 0 0 0 0 0 0 1 0 –64dB 1 0 0 0 0 0 1 0 –65dB 0 1 0 0 0 0 1 0 –66dB 1 1 0 0 0 0 1 0 –67dB 0 0 1 0 0 0 1 0 –68dB 1 0 1 0 0 0 1 0 –69dB 0 1 1 0 0 0 1 0 –70dB 1 1 1 0 0 0 1 0 –71dB 0 0 0 1 0 0 1 0 –72dB 1 0 0 1 0 0 1 0 –73dB 0 1 0 1 0 0 1 0 –74dB 1 1 0 1 0 0 1 0 –75dB 0 0 1 1 0 0 1 0 –76dB 1 0 1 1 0 0 1 0 –77dB 0 1 1 1 0 0 1 0 –78dB 1 1 1 1 0 0 1 0 –79dB 1 1 1 1 1 1 0 –∞ No. 7053-8/21 LC75412E, 75412W Tone Control D16 D17 D18 D19 D40 Bass D24 D25 D26 D27 D41 Treble 1 1 0 0 1 +18dB 0 1 0 0 1 +16dB 1 0 0 0 1 +14dB 0 1 1 0 0 +12dB 1 0 1 0 0 +10dB 0 0 1 0 0 +8dB 1 1 0 0 0 +6dB 0 1 0 0 0 +4dB 1 0 0 0 0 +2dB 0 0 0 0 0 0dB 1 0 0 1 0 –2dB 0 1 0 1 0 –4dB 1 1 0 1 0 –6dB 0 0 1 1 0 –8dB 1 0 1 1 0 –10dB 0 1 1 1 0 –12dB 1 0 0 1 1 –14dB 0 1 0 1 1 –16dB 1 1 0 1 1 –18dB D20 D21 D22 D23 0 0 0 0 Set to 0 Fader Volume Control D28 D29 D30 D31 0 0 0 0 0dB Operation 1 0 0 0 –1dB 0 1 0 0 –2dB 1 1 0 0 –4dB 0 0 1 0 –6dB 1 0 1 0 –8dB 0 1 1 0 –10dB 1 1 1 0 –12dB 0 0 0 1 –14dB 1 0 0 1 –16dB 0 1 0 1 –18dB 1 1 0 1 –20dB 0 0 1 1 –30dB 1 0 1 1 –45dB 0 1 1 1 –60dB 1 1 1 1 –∞ Channel Selection Control D32 D33 0 0 Operation 1 0 RCH 0 1 LCH 1 1 L/R simultaneously No. 7053-9/21 LC75412E, 75412W Fader Rear/Front Control D34 Setting 0 Rear 1 Front Loudness Control D35 Setting 0 OFF 1 ON Zero-Cross Control D36 D37 0 0 Data write through zero-cross detection Setting 1 1 Zero-cross detection stopped (data write at falling edge of CE) Zero-Cross Signal Detection Block Control D38 D39 0 0 Setting Selector 1 0 Volume 0 1 Tone 1 1 Fader Test Mode Control D42 D43 0 0 Setting For IC testing. Always set to 0. No. 7053-10/21 LC75412E, 75412W Pin Functions Pin Name Pin No. L1 54 L2 53 L3 52 L4 51 L6 55 R1 59 R2 60 R3 61 R4 62 R6 58 Function Equivalent circuit VDD • Single-end input pins LVref RVref VDD L5M 50 L5P 49 R5M 63 R5P 64 M – • Differential input pins VDD + P LVref RVref VDD LSEL0 48 RSEL0 1 • Input selector output pins VDD LCT 46 RCT 3 • Loudness pins. Connect high-pass compensation RC between LCT (RCT) and LVRIN (RVRIN), and connect low-pass compensation RC between LCT (RCT) and GND. VDD LVRIN 47 RVRIN 2 • Volume and equalizer input pins. Continued on next page. No. 7053-11/21 LC75412E, 75412W Continued from preceding page. Pin Name Pin No. LF1C1 42 LF1C2 41 Function Equivalent circuit VDD + – • Equalizer F1 band filter configuration capacitor connection pins. LF1C3 40 Connect capacitor between RF1C1 7 LF1C1 (RF1C1) and LF1C2 (RF1C2) RF1C2 8 LF1C2 (RF1C2) and LF1C3 (RF1C3) RF1C3 9 VDD VDD FnC1 FnC3 LF3C1 36 LF3C2 35 LF3C3 34 Connect capacitor between RF3C1 13 LF3C1 (RF3C1) and LF3C2 (RF3C2) RF3C2 14 LF3C2 (RF3C2) and LF3C3 (RF3C3) RF3C3 15 NC 45 NC 44 NC 43 NC 39 NC 38 NC 37 NC 21 NC 10 NC 11 NC 12 NC 5 NC 4 NC 3 • Equalizer F3 band filter configuration capacitor connection pins. FnC2 VDD • No connect pin VDD TEST 28 • Dedicated IC test pin. • Normally this pin is used connected to GND. VDD LTOUT 33 RTOUT 16 • Equalizer output pins VDD LFIN 32 • Fader block input pins RFIN 17 • Drive at low impedance. Continued on next page. No. 7053-12/21 LC75412E, 75412W Continued from preceding page. Pin Name Pin No. LFOUT 31 Function Equivalent circuit VDD LROUT 30 RFOUT 18 RROUT 19 • Fader output pins. Attenuation is possible separately for the front end and rear end. The attenuation amount is the same for L and R. VDD Vref 57 • Connect a capacitor of a few tens of µF between Vref and AVSS (VSS) as a VDD/2 voltage generator, current ripple countermeasure. LVref RVref VDD 56 • Power supply pin DVSS 27 • Logic system ground pin LAVSS 29 RAVSS 22 • Analog system ground pins VDD • External muting control pin MUTE 23 • Setting this pin to VSS level sets forcibly fader volume block to –∞ level. VDD • Timer pin when there is no signal in the zero-cross circuit. TIM 20 CL 26 DI 25 CE 24 Forcibly set data when there is no zero-cross signal, from the time the data is set until the timer ends. • Input pin for serial data and clock used for control VDD • Chip enable pin. Data is written to the internal latch and the analog switches are operated when the level changes from High to Low. Data transfer is enabled when the level is High. No. 7053-13/21 LC75412E, 75412W Internal Equivalent Circuit Block Diagram Selector Block Equivalent Circuit Block Diagram R3=22.65k L5P + - + - R4=25k LSELO 0dB LVref 6.702k 1.25dB R2=25k L5M 5.804k R1=22.65k 2.50dB 5.026k 3.75dB L6 4.352k 50k 5.00dB LVref 3.769k L4 6.25dB 50k 3.264k 7.50dB LVref 2.826k L3 8.75dB 50k 2.447k LVref 10.0dB L2 2.119k 50k 11.25dB 1.835k LVref 12.5dB L1 1.589k 50k LVref INMUTE SW 13.75dB 1.376k 15.0dB 1.192k LVref 16.25dB Total resistance: 50 kΩ Same for right channel Unit (Resistance: Ω) 1.032k 17.5dB 0.894k 18.75dB 5.774k LVref No. 7053-14/21 LC75412E, 75412W Volume Block Equivalent Circuit Block Diagram LVRIN 0dB –1dB R28=243 –28dB R55=133 –55dB R2=4845 R1=5434 –2dB R29=216 –29dB R56=119 –56dB R3=4319 –3dB R30=193 –30dB R57=106 –57dB R4=3850 –4dB R31=172 –31dB R58=94 –58dB R5=3431 –5dB R32=153 –32dB R59=84 –59dB R6=3058 –6dB R33=839 –33dB R60=75 –60dB R7=2726 –7dB R34=748 –34dB R61=134 –61dB R8=2429 –8dB R35=667 –35dB R62=119 –62dB R9=2165 –9dB R36=594 –36dB R63=106 –63dB R10=1930 –10dB R37=530 –37dB R64=95 –64dB R11=1720 –11dB R38=472 –38dB R65=84 –65dB R12=1533 –12dB R39=421 –39dB R66=75 –66dB R13=1366 –13dB R40=375 –40dB R67=134 –67dB R14=1218 –14dB R41=334 –41dB R68=119 –68dB R15=1085 –15dB R42=298 –42dB R69=106 –69dB R16=967 –16dB R43=266 –43dB R70=95 –70dB R17=862 –17dB R44=237 –44dB R71=85 –71dB R18=768 –18dB R45=211 –45dB R72=75 –72dB R19=685 –19dB R46=188 –46dB R73=134 –73dB R20=610 –20dB R47=168 –47dB R74=120 –74dB R21=544 –21dB R48=149 –48dB R75=107 –75dB R22=485 –22dB R49=133 –49dB R76=95 –76dB R23=432 –23dB R50=119 –50dB R77=85 –77dB R24=385 –24dB R51=106 –51dB R78=76 –78dB R25=343 –25dB R52=94 –52dB R79=67 –79dB R26=306 –26dB R53=84 –53dB R80=552 –∞ R27=273 –27dB R54=75 –54dB 1500 R81 1227 R82 Total resistance of 48.746 kΩ over tap Total resistance of 1.256 kΩ under tap (LOUD OFF) LCT 1M R86 To tone block 1230 R83 1233 R84 1236 R85 LVref Total resistance of 7.662 kΩ under tap (LOUD ON) Same for right channel Unit (Resistance: Ω) No. 7053-15/21 LC75412E, 75412W Tone Control Block Equivalent Circuit Diagram + – + – SW2 SW3 SW2 SW1 LTOUT SW3 SW1 0.655 SW4 0.655 SW4 18dB 18dB 2.189 2.189 16dB 16dB 2.756 2.756 14dB 3.470 14dB 3.470 12dB 12dB 4.368 4.368 10dB 5.498 10dB 5.498 8dB 6.923 8dB 6.923 6dB 8.715 6dB 8.715 4dB 10.972 4dB 10.972 2dB 13.813 2dB 13.813 0dB 3.90 LF1C1 + – LF1C2 0dB 3.90 LF1C3 LF3C1 LF3C2 LF3C3 Unit: kΩ Total resistance: 59.359 kΩ Same for right channel During boost, SW 1 and SW 3 are ON, during cut SW 2 and SW 4 are ON, and when 0 dB, 0 dB SW and SW 2 and SW 3 are ON. No. 7053-16/21 LC75412E, 75412W F1/F3 Band Circuit The equivalent circuit and the formula for calculating the external RC with a mean frequency of 1 kHz are shown below. • F1/F3 band equivalent circuit block diagram R1 R2 C1 C2 R3 • Calculation example Specification Mean frequency: f0 = 1 kHz Gain during maximum boost: G+18 dB = 18 dB Let us use R1 = 0.665 kΩ, R2 = 58.704 kΩ, and C1 = C2 = C. G+18 dB = 20 × LOG10 1 + R2 2R3+R1 1. Calculate R3 with G+18 dB = 18 dB: R3 = R2 10G/20 –1 – R1 ÷ 2 = 3900 Ω 2. Calculate C with the center frequency f0 = 1 kHz f0= C= 1 2π (R1+R2)R3C1C2 1 1 = 2πf0 (R1+R2)R3 2π × 1000 39359×3900 = 0.010 × 10–6 ≅ 0.01 µF 3. Calculate Q: Q= 1 R3(R1+R2) ≅ 1.789 × (R1+R2)R3 (2R3+R1) No. 7053-17/21 LC75412E, 75412W Fader Volume Block Equivalent Circuit Block Diagram S1 LFIN LFOUT 0dB 5.437k S2 –1dB S3 4.846k –2dB S4 LROUT 8.169k –4dB 6.489k –6dB 5.154k –8dB 4.094k –10dB When FADER = "1", S2 and S3 are ON. When FADER = "0", S1 and S4 are ON. 3.252k –12dB 2.583k –14dB 2.052k –16dB 1.630k –18dB 1.295k –20dB 3.419k –30dB 1.300k –45dB 0.231k –60dB 0.050k Unit: Ω Total resistance: 50 kΩ Same for right channel –∞dB LVref When –∞ data is sent to the main volume, S1 and S2 become open, and S3 and S4 simultaneously become ON. No. 7053-18/21 LC75412E, 75412W Usage Cautions (1) Data transmission at power ON • The status of internal analog switches is unstable at power ON. Therefore, perform muting or some other countermeasure until the data has been set. (2) Description of zero-cross switching circuit operation The LC75412E and 75412W have a function to switch zero-cross comparator signal detection locations, enabling the selection of the optimum detection location for blocks whose data is to be updated. Basically, the switching noise can be minimized by inputting the signal immediately following the block whose data is to be updated to the zero-cross comparator, so it is necessary to switch the detection location every time. Volume Selector Tone Fader Switch Zero-cross comparator LC75412E, 75412W Zero-Cross Detection Circuit (3) Zero-cross switching control method The zero-cross switching control method consists of setting the zero-cross control bits to the zero-cross detection mode (D36, D37 = 0), and specifying the detection blocks (D38, D39) before transmitting the data. These control bits are latched immediately following data transfer, that is to say beforehand in sync with the falling edge of CE, so when updating data of volumes, etc., it is possible to perform mode setting and zero-cross switching with one data transfer. An example of control when updating the data of the volume block is shown below. D36 D37 D38 D39 0 0 1 0 Zero-cross detection mode setting Volume block setting (4) Zero-cross timer setting If the input signal becomes lower than the zero-cross comparator detection sensitivity, or if only low-frequency signals are input, zero-cross detection continues to be impossible, and data is not latched during this time. The zero-cross timer can set a time for forcible latch during such a status when zero-cross detection is not possible. For example, to set 25 ms, using T = 0.69CR and C = 0.033 µF, we obtain R= 25 × 10 –3 0.69 × 0.033 × 10 –6 1.1 MΩ Normally, a value between 10 ms and 50 ms is set. No. 7053-19/21 LC75412E, 75412W (5) Cautions related to serial data transfer 1. To ensure that the high-frequency digital signals transferred to the CL, DI, and CE pins do not spill over to the analog signal block, either guard these signal lines with a ground pattern, or perform transmission using shielded wires. 2. The data format of the LC75412E and 75412W uses 8-bit addresses and 44-bit data. When sending data using multiples of 8 (when sending 48 bits), use the method described in Figure 1. Method for Receiving Data Using Multiple of 8 of LC75412E and 75412W X X X X Dummy data D0 D1 D2 D3 D36 D37 D38 D39 D40 D41 D42 D43 Test mode control Input switching control X : don’t care Figure 1 (6) Note on usage of external muting When using external mute function, take adequate countermeasures against noise to prevent malfunction. Input Gain Step Characteristics 20 VDD = 9 V VIN = –20 dBV f = 1 kHz Overall VDD = 9 V, VIN = 0, VR = 0 to –54 dB Overall z H 1k 20 z 0 kH --10 Level — dB Level — dB 15 Output Level Characteristics 10 10 --20 --30 --40 5 --50 --60 10 0 2 4 6 8 10 12 14 16 Step setting 20 5 7 100 2 3 5 7 1k 2 3 5 7 10k 2 3 Frequency, f — Hz Loudness Characteristics 0 VDD = 9 V, VIN = 0, VR = 0 to –54 dB Loudness ON, Overall --10 0 --20 --10 5 7100k ILC05455 Feder Step Characteristics VDD = 9 V VIN = 0 f = 1 kHz Overall --30 --30 --40 --50 --60 --70 --40 --80 --50 z f= 20 kH z --20 kH Level — dB Level — dB 2 3 ILC05454 1 10 18 f= 0 --90 --60 10 2 3 5 7 100 2 3 5 7 1k 2 3 Frequency, f — Hz 5 7 10k 2 3 5 7100k ILC05456 --100 --∞ --70 --60 --50 --40 --30 Step setting — dB --20 --10 0 ILC05457 No. 7053-20/21 LC75412E, 75412W F1 Band Characteristics 0 VDD = 9 V VIN = –20 dBV Overall --10 --15 --15 Level — dB --10 --20 --25 --25 --30 --35 --35 2 3 5 7 100 2 3 5 7 1k 2 3 5 7 10k Frequency, f — Hz 1.0 7 5 5 7100k ILC05458 0.1 7 5 3 2 0.01 7 5 VIN = 0 dBV VIN = –10 dBV 3 2 2 3 5 7 100 2 3 5 7 1k 2 3 5 7 10k Frequency, f — Hz 2 3 5 7100k ILC05460 2 3 5 7 100 2 3 5 7 1k 2 3 5 7 10k 2 3 Frequency, f — Hz THD — Frequency Characteristics 3 2 0.001 10 --40 10 2 3 VDD = 9 V 80 kHz LPF Overall VDD = 9 V VIN = –20 dBV Overall --20 --30 --40 10 Total harmonic distortion, THD — % --5 Total harmonic distortion, THD — % Level — dB --5 F3 Band Characteristics 0 1.0 7 5 3 2 5 7100k ILC05459 THD — Input Level Characteristics VDD = 9 V 80 kHz LPF Overall 0.1 7 5 3 2 z kH 20 z kH 10 Hz 1k 0.01 7 5 3 2 0.001 --40 --35 --30 --25 --20 --15 --10 --5 Input level — dBV 0 5 ILC05461 Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of Octomber, 2001. Specifications and information herein are subject to change without notice. PS No. 7053-21/21