SANYO LC75816W

Ordering number : ENN7142
CMOS IC
LC75816E, 75816W
1/8 to 1/10 Duty Dot Matrix LCD Display Controllers/Drivers
with Key Input Function
Overview
The LC75816E and LC75816W are 1/8 to 1/10 duty dot
matrix LCD display controllers/drivers that support the
display of characters, numbers, and symbols. In addition to
generating dot matrix LCD drive signals based on data
transferred serially from a microcontroller, the LC75816E
and LC75816W also provide on-chip character display ROM
and RAM to allow display systems to be implemented easily.
These products also provide up to 2 general-purpose output
ports and incorporate a key scan circuit that accepts input
from up to 30 keys to reduce printed circuit board wiring.
Features
• Key input function for up to 30 keys (A key scan is
performed only when a key is pressed.)
• Controls and drives a 5 × 7, 5 × 8, or 5 × 9 dot matrix LCD.
• Supports accessory display segment drive (up to 65
segments)
• Display technique: 1/8 duty 1/4 bias drive (5 × 7 dots)
1/9 duty 1/4 bias drive (5 × 8 dots)
1/10 duty 1/4 bias drive (5 × 9 dots)
• Display digits: 13 digits × 1 line (5 × 7 dots)
12 digits × 1 line (5 × 8 dots, 5 × 9 dots)
• Display control memory
CGROM: 240 characters (5 × 7, 5 × 8, or 5 × 9 dots)
CGRAM: 16 characters (5 × 7, 5 × 8, or 5 × 9 dots)
ADRAM: 13 × 5 bits
DCRAM: 52 × 8 bits
• Instruction function
Display on/off control
Display shift function
• Sleep mode can be used to reduce current drain.
• Built-in display contrast adjustment circuit
• Switching between the key scan output port and generalpurpose output port functions can be controlled by
instructions.
• The frame frequency of the common and segment output
waveforms can be controlled by instructions.
• Serial data I/O supports CCB format communication
with the system controller.
• Independent LCD driver block power supply VLCD
• A voltage detection type reset circuit is provided to
initialize the IC and prevent incorrect display.
• The INH pin is provided. This pin turns off the display,
disables key scanning, and forces the general-purpose
output ports to the low level.
• RC oscillator circuit
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
21202TN (OT) No. 7142-1/43
LC75816E, 75816W
Package Dimensions
unit: mm
unit: mm
3151-QFP100E
3181B-SQFP100
[LC75816W]
0.65
0.575
23.2
20.0
0.3
16.0
14.0
1.6
0.575
0.15
80
81
0.5
1.0
1.0
75
0.145
51
51
1.0
0.825
[LC75816E]
50
76
16.0
14.0
0.5
21.6
0.1
1.0
30
0.8
100
1
1
0.2
25
1.6max
26
31
100
3.0max
1.6
0.825
15.6
17.2
14.0
0.65
50
1.4
0.1
2.7
0.8
SANYO: QFP100E
0.5
0.5
SANYO: SQFP100
No. 7142-2/43
LC75816E, 75816W
KS5
KS4
KS3
KS2/P2
KS1/P1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
S65/COM9
S64/COM10
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
Pin Assignments (Top View)
80
51
81
50
KS6
KI1
KI2
KI3
KI4
KI5
VDD
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VSS
TEST
OSCO
OSCI
INH
DO
CE
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
LC75816E
(QFP100E)
100
31
30
KS2/P2
KS1/P1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
S65/COM9
S64/COM10
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
CL
DI
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
1
75
51
76
50
KS3
KS4
KS5
KS6
KI1
KI2
KI3
KI4
KI5
VDD
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VSS
TEST
OSCO
OSCI
INH
DO
CE
CL
DI
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
LC75816W
(SQFP100)
100
26
25
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
1
No. 7142-3/43
LC75816E, 75816W
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Symbol
Maximum supply voltage
Conditions
Ratings
Unit
VDD max
VDD
–0.3 to +7.0
VLCD max
VLCD
–0.3 to +11.0
Input voltage
Output voltage
Output current
Allowable power dissipation
VIN1
CE, CL, DI, INH
VIN2
OSCI, KI1 to KI5, TEST
VIN3
VLCD1, VLCD2, VLCD3, VLCD4
VOUT1
DO
VOUT2
OSCO, KS1 to KS6, P1, P2
VOUT3
VLCD0, S1 to S65, COM1 to COM10
–0.3 to +7.0
–0.3 to VDD + 0.3
V
–0.3 to VLCD + 0.3
–0.3 to +7.0
–0.3 to VDD + 0.3
V
–0.3 to VLCD + 0.3
IOUT1
S1 to S65
IOUT2
COM1 to COM10
3
IOUT3
KS1 to KS6
1
IOUT4
P1, P2
5
Pd max
V
300
Ta = 85°C
200
µA
mA
mW
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V
Parameter
Symbol
VDD
Supply voltage
VLCD
Output voltage
Input voltage
Input high level voltage
Input low level voltage
Conditions
Ratings
min
typ
max
VDD
4.5
6.0
VLCD: When the display contrast adjustment circuit is used.
7.0
10.0
VLCD: When the display contrast adjustment circuit is not used.
4.5
10.0
VLCD0
VLCD0
VLCD1
VLCD1
3/4 (VLCD0–VLCD4)
VLCD0
VLCD4+4.5
VLCD
VLCD2
VLCD2
2/4 (VLCD0–VLCD4)
VLCD0
VLCD3
VLCD3
1/4 (VLCD0–VLCD4)
VLCD0
VLCD4
VLCD4
0
Unit
V
V
V
1.5
VIH1
CE, CL, DI, INH
0.8 VDD
6.0
VIH2
OSCI
0.7 VDD
VDD
VIH3
KI1 to KI5
0.6 VDD
VDD
VIL1
CE, CL, DI, INH, KI1 to KI5
0
0.2 VDD
VIL2
OSCI
0
0.3 VDD
Recommended external resistance
ROSC
OSCI, OSCO
33
Recommended external capacitance
COSC
OSCI, OSCO
220
Guaranteed oscillation range
fOSC
OSC
150
300
V
V
kΩ
pF
600
kHz
Data setup time
tds
CL, DI: Figure 2
160
ns
Data hold time
tdh
CL, DI: Figure 2
160
ns
CE wait time
tcp
CE, CL: Figure 2
160
ns
CE setup time
tcs
CE, CL: Figure 2
160
ns
CE hold time
tch
CE, CL: Figure 2
160
ns
High level clock pulse width
tøH
CL: Figure 2
160
ns
Low level clock pulse width
tøL
CL: Figure 2
160
ns
DO output delay time
tdc
DO, RPU = 4.7kΩ, CL = 10pF*1: Figure 2
1.5
µs
DO rise time
tdr
DO, RPU = 4.7kΩ, CL = 10pF*1: Figure 2
1.5
µs
Note: *1. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load capacitance CL.
No. 7142-4/43
LC75816E, 75816W
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Hysteresis
Power-down detection voltage
Input high level current
Symbol
VH
Conditions
Input low level current
IIL
CE, CL, DI, INH, OSCI: VI = 0 V
Input floating voltage
VIF
KI1 to KI5
Pull-down resistance
RPD
KI1 to KI5: VDD = 5.0 V
Output low level voltage
Output middle level voltage*2
Oscillator frequency
Unit
max
0.1 VDD
2.5
CE, CL, DI, INH, OSCI: VI = 6.0 V
Output high level voltage
typ
CE, CL, DI, INH, KI1 to KI5
VDET
IIH
Output off leakage current
Ratings
min
3.0
V
3.5
V
5.0
µA
–5.0
µA
0.05 VDD
50
IOFFH
DO: VO = 6.0 V
VOH1
S1 to S65: IO = –20 µA
VLCD0 – 0.6
VLCD0 – 0.6
100
VOH2
COM1 to COM10: IO = –100 µA
VOH3
KS1 to KS6: IO = –500 µA
VDD – 1.0 VDD – 0.5
VOH4
P1, P2: IO = –1 mA
VDD – 1.0
VOH5
OSCO: IO = –500 µA
VDD – 1.0
VOL1
S1 to S65: IO = 20 µA
VOL2
COM1 to COM10: IO = 100 µA
VOL3
KS1 to KS6: IO = 25 µA
VOL4
P1, P2: IO = 1 mA
VOL5
OSCO: IO = 500 µA
VOL6
DO: IO = 1 mA
kΩ
6.0
µA
VDD – 0.2
V
VLCD4 + 0.6
VLCD4 + 0.6
0.2
0.5
1.5
1.0
V
1.0
0.1
0.5
VMID1
S1 to S65: IO = ±20 µA
2/4 (VLCD0 – VLCD4) – 0.6
2/4 (VLCD0 – VLCD4) + 0.6
VMID2
COM1 to COM10: IO = ±100 µA
3/4 (VLCD0 – VLCD4) – 0.6
3/4 (VLCD0 – VLCD4) + 0.6
VMID3
COM1 to COM10: IO = ±100 µA
1/4 (VLCD0 – VLCD4) – 0.6
1/4 (VLCD0 – VLCD4) + 0.6
fOSC
OSCI, OSCO: ROSC = 33 kΩ, COSC = 220 pF
IDD1
VDD: sleep mode
210
300
390
V
kHz
100
IDD2
VDD: VDD = 6.0 V, output open, fOSC = 300 kHz
ILCD1
VLCD: sleep mode
ILCD2
VLCD: VLCD = 10.0 V, output open, fOSC = 300 kHz
When the display contrast adjustment circuit is used.
ILCD3
VLCD: VLCD = 10.0 V, output open, fOSC = 300 kHz
When the display contrast adjustment circuit is not used.
Current drain
V
250
500
1000
450
900
200
400
5
µA
Note: *2. Excluding the bias voltage generation divider resistor built into the VLCD0, VLCD1, VLCD2, VLCD3, and VLCD4. (See Figure 1.)
VLCD
CONTRAST
ADJUSTER
VLCD0
VLCD1
VLCD2
To the common and segment drivers
VLCD3
VLCD4
Excluding these resistors
Figure 1
No. 7142-5/43
LC75816E, 75816W
• When CL is stopped at the low level
VIH1
CE
VIL1
tøH
CL
tøL
VIH1
50%
VIL1
tcp
DI
tcs
tch
VIH1
VIL1
tds
tdh
tdc
tdr
D0
DO
D1
• When CL is stopped at the high level
VIH1
CE
VIL1
tøL
tøH
VIH1
50%
VIL1
CL
tcp
tcs
tch
VIH1
VIL1
DI
tds
tdh
D0
DO
D1
tdr
tdc
COMMON
DRIVER
S1
S63
S65/COM9
COM8
COM1
Block Diagram
S64/COM10
Figure 2
SEGMENT DRIVER
LATCH
INSTRUCTION
DECODER
ADRAM
65
bits
INSTRUCTION
REGISTER
ADDRESS
COUNTER
VLCD
CONTRAST
ADJUSTER
VLCD0
CGRAM
5 × 9 × 16
bits
CGROM
5 × 9 × 240
bits
DCRAM
52 × 8
bits
VLCD1
ADDRESS
REGISTER
VLCD2
VLCD3
VLCD4
SHIFT REGISTER
KEY BUFFER
CCB INTERFACE
VDD
VDET
TIMING
GENERATOR
VSS
KS6
KS5
KS4
KS3
P2/KS2
P1/KS1
KI5
KI4
KI3
KI2
KI1
CE
CL
DI
DO
KEY SCAN
INH
OSCO
CLOCK
GENERATOR
OSCI
TEST
No. 7142-6/43
LC75816E, 75816W
Pin Functions
Pin No.
Pin
LC75816E
LC75816W
S1 to S63
S64/COM10
S65/COM9
3 to 65
66
67
1 to 63
64
65
COM1 to COM8
75 to 68
73 to 66
KS1/P1
76
KS2/P2
77
75
KS3 to KS6
78 to 81
76 to 79
KI1 to KI5
82 to 86
80 to 84
OSCI
97
95
OSCO
96
94
CE
100
98
74
CL
1
99
DI
2
100
DO
99
97
Function
Active
I/O
Segment driver outputs.
The S64/COM10, S65/COM9 pins can be used as common
driver output under the “set display technique” instruction.
—
O
OPEN
Common driver outputs.
—
O
OPEN
Key scan outputs. Although normal key scan timing lines require
diodes to be inserted in the timing lines to prevent shorts, since
these outputs are unbalanced CMOS transistor outputs, these
outputs will not be damaged by shorting when these outputs are
used to form a key matrix. The KS1/P1 and KS2/P2 pins can be
used as general-purpose output ports under the "set key scan
output port/general-purpose output port state" instruction.
—
O
OPEN
Key scan inputs.
These pins have built-in pull-down resistors.
H
I
GND
Oscillator connections. An oscillator circuit is formed by
connecting an external resistor and capacitor at these pins.
—
I
GND
—
O
OPEN
Serial data interface connections to the controller. Note that DO,
being an open-drain output, requires a pull-up resistor.
CE : Chip enable
CL : Synchronization clock
DI : Transfer data
DO : Output data
H
I
I
—
I
Handling when unused
GND
—
O
OPEN
L
I
VDD
INH
98
96
Input that turns the display off, disables key scanning, and
forces the general-purpose output ports low.
• When INH is low (VSS):
• Display off
S1 to S63 = “L” (VLCD4).
S64/COM10, S65/COM9 = “L” (VLCD4).
COM1 to COM8 = “L” (VLCD4).
• General-purpose output ports P1, P2 = low (VSS)
• Key scanning disabled: KS1 to KS6 = low (VSS)
• All the key data is reset to low.
• When INH is high (VDD):
• Display on
• The state of the pins as key scan output pins or
general-purpose output ports can be set with the
"set key scan output port/general-purpose output
port state" instruction.
• Key scanning is enabled.
However, serial data can be transferred when the INH pin is low.
TEST
95
93
This pin must be connected to ground.
—
I
—
—
O
OPEN
VLCD0
89
87
LCD drive 4/4 bias voltage (high level) supply pin. The level on
this pin can be changed by the display contrast adjustment circuit.
However, (VLCD0 – VLCD4) must be greater than or equal to 4.5
V. Also, external power must not be applied to this pin since the
pin circuit includes the display contrast adjustment circuit.
VLCD1
90
88
LCD drive 3/4 bias voltage (middle level) supply pin. This pin can
be used to supply the 3/4 (VLCD0 – VLCD4) voltage level externally.
—
I
OPEN
VLCD2
91
89
LCD drive 2/4 bias voltage (middle level) supply pin. This pin can
be used to supply the 2/4 (VLCD0 - VLCD4) voltage level externally.
—
I
OPEN
VLCD3
92
90
LCD drive 1/4 bias voltage (middle level) supply pin. This pin can
be used to supply the 1/4 (VLCD0 – VLCD4) voltage level externally.
—
I
OPEN
—
I
GND
VLCD4
93
91
LCD drive 0/4 bias voltage (low level) supply pin. Fine
adjustment of the display contrast can be implemented by
connecting an external variable resistor to this pin.
However, (VLCD0 – VLCD4) must be greater than or equal to 4.5
V, and VLCD4 must be in the range 0 V to 1.5 V, inclusive.
VDD
87
85
Logic block power supply connection. Provide a voltage of
between 4.5 and 6.0 V.
—
—
—
VLCD
88
86
LCD driver block power supply connection. Provide a voltage of
between 7.0 and 10.0 V when the display contrast adjustment
circuit is used and provide a voltage of between 4.5 and 10.0 V
when the circuit is not used.
—
—
—
VSS
94
92
Power supply connection. Connect to ground.
—
—
—
No. 7142-7/43
LC75816E, 75816W
Block Functions
• AC (address counter)
AC is a counter that provides the addresses used for DCRAM and ADRAM.
The address is automatically modified internally, and the LCD display state is retained.
• DCRAM (data control RAM)
DCRAM is RAM that is used to store display data expressed as 8-bit character codes. (These character codes are
converted to 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of
52 × 8 bits, and can hold 52 characters. The table below lists the correspondence between the 6-bit DCRAM address
loaded into AC and the display position on the LCD panel.
•
When the DCRAM address loaded into AC is 00H.
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
DCRAM address (hexadecimal)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
However, when the display shift is performed by specifying MDATA, the DCRAM address shifts as shown below.
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
DCRAM address (hexadecimal)
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
DCRAM address (hexadecimal)
33
00
01
02
03
04
05
06
07
08
09
0A
0B
(Shift left)
(Shift right)
Note: *3. The DCRAM address is expressed in hexadecimal.
Least significant bit
↓
LSB
DCRAM address
DA0
Most significant bit
↓
MSB
DA1
DA2
DA3
Hexadecimal
DA4
DA5
Hexadecimal
Example: When the DCRAM address is 2EH.
DA0
DA1
DA2
DA3
DA4
DA5
0
1
1
1
0
1
Note: *4. 5 × 7 dots ... 13-digit display
5 × 8 dots ... 13-digit display
5 × 9 dots ... 13-digit display
5 × 7 dots
4 × 8 dots
3 × 9 dots
No. 7142-8/43
LC75816E, 75816W
• ADRAM (Additional data RAM)
ADRAM is RAM that is used to store the ADATA display data. ADRAM has a capacity of 13 × 5 bits, and the stored
display data is displayed directly without the use of CGROM or CGRAM. The table below lists the correspondence
between the 4-bit ADRAM address loaded into AC and the display position on the LCD panel.
•
When the ADRAM address loaded into AC is 0H. (Number of digit displayed: 13)
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
ADRAM address (hexadecimal)
0
1
2
3
4
5
6
7
8
9
A
B
C
However, when the display shift is performed by specifying ADATA, the ADRAM address shifts as shown below.
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
ADRAM address (hexadecimal)
1
2
3
4
5
6
7
8
9
A
B
C
0
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
13
ADRAM address (hexadecimal)
C
0
1
2
3
4
5
6
7
8
9
A
B
(Shift left)
(Shift right)
Note: *5. The ADRAM address is expressed in hexadecimal.
Least significant bit
↓
LSB
ADRAM address
RA0
Most significant bit
↓
MSB
RA1
RA2
RA3
Hexadecimal
Example: When the ADRAM address is AH
RA0
RA1
RA2
RA3
0
1
0
1
Note: *6. 5 × 7 dots ... 13-digit display
5 × 8 dots ... 13-digit display
5 × 9 dots ... 13-digit display
5 dots
4 dots
3 dots
• CGROM (Character generator ROM)
CGROM is ROM that is used to generate the 240 kinds of 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns from the
8-bit character codes. CGROM has a capacity of 240 × 45 bits. When a character code is written to DCRAM, the
character pattern stored in CGROM corresponding to the character code is displayed at the position on the LCD
corresponding to the DCRAM address loaded into AC.
• CGRAM (Character generator RAM)
CGRAM is RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5 × 7, 5 × 8,
or 5 × 9 dot matrix character patterns can be stored. CGRAM has a capacity of 16 × 45 bits.
No. 7142-9/43
LC75816E, 75816W
Serial Data Input
• When CL is stopped at the low level
CE
CL
DI
0
B0
1
B1
0
B2
0
B3
0
A0
0
A1
1
A2
0
A1
1
A2
0
A3
D0
D1 D2 D3 D4
D62 D63
Instruction data (Up to 64 bits)
DO
• When CL is stopped at the high level
CE
CL
DI
0
B0
1
B1
0
B2
0
B3
0
A0
0
A3
D0 D1 D2 D3 D4
D62 D63
Instruction data (Up to 64 bits)
DO
•
•
B0 to B3, A0 to A3: CCB address 42H
D0 to D63: Instruction data
The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When
transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set
of instruction data until the next instruction data transfer is significantly longer than the instruction execution time.
No. 7142-10/43
D41
D42
D43 D44
D45
D46
D47
D48
D49
D50
D51
D52
X
D53
X
*7. The data format differs when the “DCRAM data write” instruction is executed in the increment mode (IM = 1).
(See detailed instruction descriptions .)
*8. The data format differs when the “ADRAM data write” instruction is executed in the increment mode (IM = 1).
(See detailed instruction descriptions.)
*9. The execution times listed here apply when fosc = 300 kHz. The execution times differ when the oscillator frequency fosc differs.
Example: When fosc = 210 kHz
300
27 µs ×—— = 39 µs
210
*10.When the sleep mode (SP = 1) is set, the execution time is 27 µs (when fosc = 300 kHz).
X
KC1 KC2 KC3 KC4 KC5 KC6
Notes:
X
X
X
X
D54
X
X
X
X
X
X
X
X
X
X
X
CTC
X
X
X
PC1 PC2 KP1 KP2
X
X
X
1
1
0
0
X
X
IM
X
0
0
X
X
0
0
IM
R/L
SP
X
0
0
1
1
1
1
0
0
0
D60 D61
0
A
M
SC
FC
D58 D59
RA0 RA1 RA2 RA3
A
M
DT1 DT2
D55 D56 D57
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7
X
Set key scan output port/
general-purpose output port state
X
X
CT0 CT1 CT2 CT3
X
RA0 RA1 RA2 RA3
Set display contrast
X
X
CD41 CD42 CD43 CD44 CD45
X
CGRAM data write
X
AD1 AD2 AD3 AD4 AD5
ADRAM data write *8
DA0 DA1 DA2 DA3 DA4 DA5
DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 DG13
D40
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5
CD1 CD2...CD40
D0 D1...D39
DCRAM data write *7
Set AC address
Display shift
Display on/off control
Set display technique
Instruction
Instruction Table
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
D62 D63
X: don’t care
0 µs
0 µs
27 µs
27 µs
27 µs
27 µs
27 µs
0 µs/27 µs *10
0 µs
Execution time *9
LC75816E, 75816W
No. 7142-11/43
LC75816E, 75816W
Detailed Instruction Descriptions
• Set display technique ... <Sets the display technique>
Code
D56
D57
D58
D59
D60
D61
DT1 DT2
FC
X
0
0
D62 D63
0
1
X: don’t care
DT1, DT2: Sets the display technique
DT1
DT2
0
0
1
0
Output pins
Display technique
S65/COM9
S64/COM10
1/8 duty, 1/4 bias drive
S65
S64
0
1/9 duty, 1/4 bias drive
COM9
S64
1
1/10 duty, 1/4 bias drive
COM9
COM10
Note: *11 Sn (n = 64, 65): Segment outputs
COMn (n = 9, 10): Common outputs
FC: Sets the frame frequency of the common and segment output waveforms
Frame frequency
FC
1/8 duty, 1/4 bias drive f8 (Hz)
1/9 duty, 1/4 bias drive f9 (Hz)
1/10 duty, 1/4 bias drive f10 (Hz)
0
fosc
3072
fosc
3456
fosc
3840
1
fosc
1536
fosc
1728
fosc
1920
• Display on/off control ... <Turns the display on or off>
Code
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59 D60
X
X
X
M
A
SC
SP
DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 DG13
0
D61
D62
D63
0
1
0
X: don’t care
M, A: Specifies the data to be turned on or off
M
A
0
0
Both MDATA and ADATA are turned off (The display is forcibly turned off regardless of the DG1 to DG13 data.)
Display operating state
0
1
Only ADATA is turned on (The ADATA of display digits specified by the DG1 to DG13 data are turned on.)
1
0
Only MDATA is turned on (The MDATA of display digits specified by the DG1 to DG13 data are turned on.)
1
1
Both MDATA and ADATA are turned on (The MDATA and ADATA of display digits specified by the DG1 to DG13 data are turned on.)
Note: *12. MDATA, ADATA
5 × 7 dot matrix display
5 × 8 dot matrix display
5 × 9 dot matrix display
....
ADATA
. . . . ADATA
....
ADATA
...
MDATA
. . . MDATA
...
MDATA
A10719
DG1 to DG13: Specifies the display digit
Display digit
Display digit data
1
2
3
4
5
6
7
8
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
9
10
11
12
13
DG9 DG10 DG11 DG12 DG13
For example, if DG1 to DG7 are 1, and DG8 to DG13 are 0, then display digits 1 to 7 will be turned on, and display digits 8
to 13 will be turned off (blanked).
No. 7142-12/43
LC75816E, 75816W
SC: Controls the common and segment output pins
SC
Common and segment output pin states
0
Output of LCD drive waveforms
1
Fixed at the VLCD4 level (all segments off)
Note: *13. When SC is 1, the S1 to S65 and COM1 to COM10 output pins are set to the VLCD4 level, regardless of the M, A, and DG1 to DG13 data.
SP: Controls the normal mode and sleep mode
SP
Mode
0
Normal mode
1
Sleep mode
(The common and segment pins go to the VLCD4 level and the oscillator on the OSCI, OSCO pins is stopped (although it operates during key
scan operations), to reduce current drain. Although the "display on/off control", "set display contrast", and "set key scan output port/generalpurpose output port state" instructions can be executed in this mode, applications must return the IC to normal mode to execute any of the other
instruction settings.)
• Display shift ... <Shifts the display>
Code
D56
D57
D58
D59
D60
D61
M
A
R/L
X
0
0
D62 D63
1
1
X: don’t care
M, A: Specifies the data to be shifted
R/L: Specifies the shift direction
M
A
0
0
Neither MDATA nor ADATA is shifted
Shift operating state
R/L
0
Shift direction
Shift left
0
1
Only ADATA is shifted
1
Shift right
1
0
Only MDATA is shifted
1
1
Both MDATA and ADATA are shifted
• Set AC address... <Specifies the DCRAM and ADRAM address for AC>
Code
D48
D49
D50
D51
D52
D53
D54
D55
X
X
DA0 DA1 DA2 DA3 DA4 DA5
D56
D57
D58
D59
RA0 RA1 RA2 RA3
D60
D61
D62
D63
0
1
0
0
X: don’t care
DA0 to DA5: DCRAM address
DA0
DA1
LSB
↑
Least significant bit
DA2
DA3
DA4
DA5
MSB
↑
Most significant bit
RA0 to RA3: ADRAM address
RA0
RA1
LSB
↑
Least significant bit
RA2
RA3
MSB
↑
Most significant bit
This instruction loads the 6-bit DCRAM address DA0 to DA5 and the 4-bit ADRAM address RA0 to RA3 into the AC.
No. 7142-13/43
LC75816E, 75816W
• DCRAM data write ... <Specifies the DCRAM address and stores data at that address>
Code
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
X
X
IM
X
X
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5
D59 D60
X
D61
D62
D63
1
0
1
0
X: don’t care
DA0 to DA5: DCRAM address
DA0
DA1
DA2
DA3
DA4
LSB
↑
Least significant bit
DA5
MSB
↑
Most significant bit
AC0 to AC7: DCRAM data (character code)
AC0
AC1
AC2
AC3
AC4
AC5
AC6
LSB
↑
Least significant bit
AC7
MSB
↑
Most significant bit
This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code, and is converted to a
5 × 7, 5 × 8, or 5 × 9 dot matrix display data using CGROM or CGRAM.
IM: Sets the method of writing data to DCRAM
IM
DCRAM data write method
0
Normal DCRAM data write (Specifies the DCRAM address and writes the DCRAM data.)
1
Increment mode DCRAM data write (Increments the DCRAM address by +1 each time data is written to DCRAM.)
Notes: *14.
· DCRAM data write method when IM = 0
CE
CCB address
CCB address
CCB address
CCB address
(1)
(1)
(1)
(1)
24 bits
24 bits
24 bits
24 bits
Instruction
execution time
Instruction
execution time
DI
DCRAM
DCRAM data
write finishes
Instruction
execution time
Instruction
execution time
DCRAM data
write finishes
DCRAM data
write finishes
DCRAM data
write finishes
· DCRAM data write method when IM = 1 (Instructions other than the “DCRAM data write” instruction cannot be
executed.)
CE
CCB address
DI
CCB address
CCB address
CCB address
CCB address
CCB address
(1)
(2)
(2)
(2)
(2)
(3)
24 bits
8 bits
8 bits
8 bits
8 bits
16 bits
Instruction
execution
time
Instruction
execution
time
Instruction
execution time
Instruction
execution
time
DCRAM
Instruction
execution time
DCRAM data
write finishes
DCRAM data
write finishes
DCRAM data
write finishes
DCRAM data
write finishes
Instruction
execution time
DCRAM data
write finishes
DCRAM data
write finishes
Instructions other than the “DCRAM data write” instruction cannot be executed.
No. 7142-14/43
LC75816E, 75816W
Data format at (1) (24 bits)
Code
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5
D54
D55
D56
D57
D58
X
X
IM
X
X
D59 D60
X
0
D61
D62
D63
1
0
1
X: don’t care
Data format at (2) (8 bits)
Code
D56
D57
D58
D59
D60
D61
D62 D63
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7
Data format at (3) (16 bits)
Code
D48
D49
D50
D51
D52
D53
D54
D55
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7
D56
D57
D58
D59
D60
D61
D62
D63
0
X
X
X
0
1
0
1
X: don’t care
• ADRAM data write ... <Specifies the ADRAM address and stores data at that address>
Code
D40
D41
D42
D43
D44
AD1 AD2 AD3 AD4 AD5
D45
D46
D47
X
X
X
D48
D49
D50
D51
RA0 RA1 RA2 RA3
D52
D53
D54
D55
D56
D57
D58
X
X
X
X
IM
X
X
D59 D60
X
0
D61
D62
D63
1
1
0
X: don’t care
RA0 to RA3: ADRAM address
RA0
RA1
LSB
RA2
RA3
MSB
Least significant bit
Most significant bit
AD1 to AD5: ADATA display data
In addition to the 5 × 7, 5 × 8, or 5 × 9 dot matrix display data (MDATA), this IC supports direct display of the five
accessory display segments provided in each digit as ADATA. This display function does not use CGROM or CGRAM.
The figure below shows the correspondence between the data and the display. When ADn = 1 (where n is an integer
between 1 and 5) the segment corresponding to that data will be turned on.
ADATA
S5m+1
S5m+5 (m is an integer
between 0 and 12)
Corresponding output pin
AD1
S5m + 1 (m is an integer between 0 and 12)
AD2
S5m + 2
AD3
S5m + 3
AD4
S5m + 4
AD5
S5m + 5
No. 7142-15/43
LC75816E, 75816W
IM: Sets the method of writing data to ADRAM
IM
ADRAM data write method
0
Normal ADRAM data write (Specifies the ADRAM address and writes the ADRAM data.)
1
Increment mode ADRAM data write (Increments the ADRAM address by +1 each time data is written to ADRAM.)
Notes: *15.
· ADRAM data write method when IM = 0
CE
CCB address
CCB address
CCB address
DI
(4)
CCB address
(4)
(4)
(4)
24 bits
24 bits
24 bits
24 bits
ADRAM
Instruction
execution time
Instruction
execution time
ADRAM data
write finishes
Instruction
execution time
ADRAM data
write finishes
Instruction
execution time
ADRAM data
write finishes
ADRAM data
write finishes
· ADRAM data write method when IM = 1 (Instructions other than the “ADRAM data write” instruction cannot
be excuted.)
CE
CCB address
CCB address
CCB address
DI
CCB address
CCB address
CCB address
(4)
(5)
(5)
(5)
(5)
(6)
24 bits
8 bits
8 bits
8 bits
8 bits
16 bits
Instruction
execution
time
Instruction
execution
time
Instruction
execution time
Instruction
execution
time
ADRAM
Instruction
execution time
ADRAM data
write finishes
ADRAM data
write finishes
ADRAM data
write finishes
ADRAM data
write finishes
Instruction
execution time
ADRAM data
write finishes
ADRAM data
write finishes
Instructions other than the “ADRAM data write” instruction cannot be excuted.
Data format at (4) (24 bits)
Code
D40
D41
D42
D43
D44
AD1 AD2 AD3 AD4 AD5
D45
D46
D47
X
X
X
D48
D49
D50
D51
RA0 RA1 RA2 RA3
D52
D53
D54
D55
D56
D57
D58
X
X
X
X
IM
X
X
D59 D60
X
0
D61
D62
D63
1
1
0
X: don’t care
Data format at (5) (8 bits)
Code
D56
D57
D58
D59
D60
AD1 AD2 AD3 AD4 AD5
D61
X
D62 D63
X
X
X: don’t care
Data format at (6) (16 bits)
Code
D48
D49
D50
D51
D52
AD1 AD2 AD3 AD4 AD5
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
X
X
X
0
X
X
X
0
1
1
0
X: don’t care
No. 7142-16/43
LC75816E, 75816W
• CGRAM data write ... <Specifies the CGRAM address and stores data at that address>
Code
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CD16
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
CD17
CD18
CD19
CD20
CD21
CD22
CD23
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
CD32
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD41
CD42
CD43
CD44
CD45
X
X
X
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
X
X
X
X
0
1
1
1
Code
Code
Code
X: don’t care
CA0 to CA7: CGRAM address
CA0
CA1
CA2
CA3
LSB
↑
Least significant bit
CA4
CA5
CA6
CA7
MSB
↑
Most significant bit
CD1 to CD45: CGRAM data (5 × 7, 5 × 8, or 5 × 9 dot matrix display data)
The bit CDn (where n is an integer between 1 and 45) corresponds to the 5 × 7, 5 × 8, or 5 × 9 dot matrix display data.
The figure below shows that correspondence. When CDn is 1 the dots which correspond to that data will be turned on.
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
CD32
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD41
CD42
CD43
CD44
CD45
Note: *16. CD1 to CD35: 5 × 7 dot matrix display data
CD1 to CD40: 5 × 8 dot matrix display data
CD1 to CD45: 5 × 9 dot matrix display data
No. 7142-17/43
LC75816E, 75816W
• Set display contrast ... <Sets the display contrast>
Code
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
CT0
CT1
CT2
CT3
X
X
X
X
CTC
X
X
X
1
0
0
0
X: don’t care
CT0 to CT3: Sets the display contrast (11 steps)
CT0
CT1
CT2
CT3
0
0
0
0
LCD drive 4/4 bias voltage supply VLCD0 level
0.94 VLCD = VLCD – (0.03 VLCD × 2)
1
0
0
0
0.91 VLCD = VLCD – (0.03 VLCD × 3)
0
1
0
0
0.88 VLCD = VLCD – (0.03 VLCD × 4)
1
1
0
0
0.85 VLCD = VLCD – (0.03 VLCD × 5)
0
0
1
0
0.82 VLCD = VLCD – (0.03 VLCD × 6)
1
0
1
0
0.79 VLCD = VLCD – (0.03 VLCD × 7)
0
1
1
0
0.76 VLCD = VLCD – (0.03 VLCD × 8)
1
1
1
0
0.73 VLCD = VLCD – (0.03 VLCD × 9)
0
0
0
1
0.70 VLCD = VLCD – (0.03 VLCD × 10)
1
0
0
1
0.67 VLCD = VLCD – (0.03 VLCD × 11)
0
1
0
1
0.64 VLCD = VLCD – (0.03 VLCD × 12)
CTC: Sets the display contrast adjustment circuit state
CTC
Display contrast adjustment circuit state
0
The display contrast adjustment circuit is disabled, and the VLCD0 pin level is forced to the VLCD level.
1
The display contrast adjustment circuit operates, and the display contrast is adjusted.
Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it is also
possible to apply fine adjustments to the contrast by connecting an external variable resistor to the VLCD4 pin and modifying
the VLCD4 pin voltage. However, the following conditions must be met: (VLCD0 – VLCD4) ≥ 4.5 V, and 1.5 V ≥ VLCD4 ≥ 0 V.
No. 7142-18/43
LC75816E, 75816W
• Set key scan output port/general-purpose output port state
... <Sets the key scan output port and general-purpose output port states>
Code
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
KC1
KC2
KC3
KC4
KC5
KC6
X
X
PC1
PC2
KP1
KP2
1
0
0
1
X: don’t care
KP1, KP2: These bits switch the functions of the KS1/P1 and KS2/P2 output pins between the key scan output port and
the general-purpose output port.
Output pins
KS1/P1
KS2/P2
Maximum number of
key inputs
Number of generalpurpose output ports
0
KS1
KS2
30
0
0
P1
KS2
25
1
1
P1
P2
20
2
KP1
KP2
0
1
0
Note: *17 KSn (n = 1, 2): Key scan output port
Pn (n = 1, 2): General-purpose output port
KC1 to KC6: Sets the key scan output pin KS1 to KS6 state
Output pin
KS1
KS2
KS3
KS4
KS5
KS6
Key scan output state setting data
KC1
KC2
KC3
KC4
KC5
KC6
Consider the case where the KS1/P1 and KS2/P2 output pins are set to function as key scan output ports. When KC1 to
KC3 are set to 1 and KC4 to KC6 are set to 0, in the key scan standby state the KS1 to KS3 output pins will output the
high level (VDD) and KS4 to KS6 will output the low level (VSS).
Note that key scan output signals are not output from output pins that are set to the low level.
PC1, PC2: Sets the general-purpose output port P1, P2 state
Output pin
General-purpose output port state setting data
P1
P2
PC1
PC2
Consider the case where the KS1/P1 and KS2/P2 output pins are set to function as general-purpose output ports. When
PC1 is set to 1 and PC2 is set to 0, the P1 output pin will output the high level (VDD) and P2 will output the low level
(VSS).
No. 7142-19/43
LC75816E, 75816W
Serial Data Output
• When CL is stopped at the low level
CE
CL
DI
1
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
X
DO
KD1 KD2
KD27 KD28 KD29 KD30 SA
Output data
X: don't care
• When CL is stopped at the high level
CE
CL
DI
1
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
DO
X KD1 KD2 KD3
KD28 KD29 KD30 SA
X
Output data
X: don't care
•
•
•
B0 to B3, A0 to A3 : CCB address 43H
KD1 to KD30 : Key data
SA : Sleep acknowledge data
Note: *18. If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep
acknowledge data(SA) will be invalid.
No. 7142-20/43
LC75816E, 75816W
Output Data
• KD1 to KD30 : Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one
of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship
between those pins and the key data bits.
KS1/P1
KI1
KI2
KI3
KI4
KI5
KD1
KD2
KD3
KD4
KD5
KS2/P2
KD6
KD7
KD8
KD9
KD10
KS3
KD11
KD12
KD13
KD14
KD15
KS4
KD16
KD17
KD18
KD19
KD20
KS5
KD21
KD22
KD23
KD24
KD25
KS6
KD26
KD27
KD28
KD29
KD30
When the KS1/P1 and KS2/P2 output pins are set to function as general-purpose output ports with the "set key scan
output port/general-purpose output port state" instruction and a key matrix of up to 20 keys is formed from the KS3 to
KS6 output pins and the KI1 to KI5 input pins, the KD1 to KD10 key data bits will be set to 0.
• SA : Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is
input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep
mode and 0 in normal mode.
No. 7142-21/43
LC75816E, 75816W
Key Scan Operation Functions
• Key scan timing
The key scan period is 2304T(s). To reliably determine the on/off state of the keys, the LC75816E/W scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 4800T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75816E/W cannot detect a key press shorter than 4800T(s).
KS1
*19
KS2
*19
KS3
*19
KS4
*19
KS5
*19
KS6
*19
1
1
2
*19
2
3
*19
3
*19
T=
4
4
5
*19
5
6
1
fosc
*19
6
*19
4608T[s]
Key on
Note: *19. Not that the high/low states of these pins are determined by the "set key scan output port/general-purpose output port state" instruction, and that
key scan output signals are not output from pins that are set to low.
• In normal mode
• The pins KS1 to KS6 are set to high or low with the "set key scan output port/general-purpose output port state"
instruction.
• If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, a key scan is started and
the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple
key data bits are set.
1 ) the LC75816E/W outputs a key data read request (a
• If a key is pressed for longer than 4800T(s) (Where T= ——
fosc
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE
is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75816E/W
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and
10 kΩ).
Key input 1
Key input 2
Key scan
4800T[s]
CE
Serial data
transfer
4800T[s]
Serial data
transfer Key address
(43H)
Serial data
transfer Key address
4800T[s]
Key address
DI
DO
Key data read
Key data read request
Key data read
Key data read
Key data read request
Key data read request
T=
1
fosc
No. 7142-22/43
LC75816E, 75816W
• In sleep mode
• The pins KS1 to KS6 are set to high or low with the "set key scan output port/general-purpose output port state"
instruction.
• If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the
OSCI, OSCO pins is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key
presses are recognized by determining whether multiple key data bits are set.
1 ) the LC75816E/W outputs a key data read request (a
• If a key is pressed for longer than 4800T(s)(Where T= ——
fosc
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE
is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75816E/W
performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain output,
requires a pull-up resistor (between 1 and 10 kΩ).
• Sleep mode key scan example
Example: When a "display on/off control (SP = 1)" instruction and a "set key scan output port/general-purpose
output port state (KP1 and KP2 = 0, KC1 to KC5 = 0, KC6 = 1)" instruction are executed. (i.e. sleep mode with only
KS6 high.)
"L"KS1
"L"KS2
"L"KS3
"L"KS4
"L"KS5
"H"KS6
When any one of these keys is pressed,
the oscillator on the OSCI, OSCO pins is
started and the keys are scanned.
*20
KI1
KI2
KI3
KI4
KI5
Note: *20. These diodes are required to reliably recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above
example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to
KS5 lines are pressed at the same time.
Key input
(KS6 line)
Key scan
4800T[s]
CE
Serial data
transfer
4800T[s]
Serial data
Key address
transfer
(43H)
Serial data
transfer Key address
DI
T=
1
fosc
DO
Key data read
Key data read request
Key data read
Key data read request
Multiple Key Presses
Although the LC75816E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bits and ignore such data.
No. 7142-23/43
LC75816E, 75816W
1/8 Duty, 1/4 Bias Drive Technique
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
COM1
COM2
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
COM8
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
LCD driver output when all
LCD segments
corresponding to COM1 to
COM8 are turned off
LCD driver output when
only LCD segments
corresponding to COM1
are turned on
LCD driver output when
only LCD segments
corresponding to COM2
are turned on
LCD driver output when all
LCD segments
corresponding to COM1 to
COM8 are turned on
T8
8
T8
T8 =
1
f8
fosc
3072
fosc
When a "set display technique" instruction with FC = 1 is executed: f8 =
1536
When a "set display technique" instruction with FC = 0 is executed: f8 =
No. 7142-24/43
LC75816E, 75816W
1/9 Duty, 1/4 Bias Drive Technique
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
COM1
COM2
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
COM9
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
LCD driver output when all
LCD segments
corresponding to COM1 to
COM9 are turned off
LCD driver output when
only LCD segments
corresponding to COM1
are turned on
LCD driver output when
only LCD segments
corresponding to COM2
are turned on
LCD driver output when all
LCD segments
corresponding to COM1 to
COM9 are turned on
T9
9
T9
T9 =
1
f9
fosc
3456
fosc
When a "set display technique" instruction with FC = 1 is executed: f9 =
1728
When a "set display technique" instruction with FC = 0 is executed: f9 =
No. 7142-25/43
LC75816E, 75816W
1/10 Duty, 1/4 Bias Drive Technique
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
COM1
COM2
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
COM10
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
LCD driver output when all
LCD segments
corresponding to COM1 to
COM10 are turned off
LCD driver output when
only LCD segments
corresponding to COM1
are turned on
LCD driver output when
only LCD segments
corresponding to COM2
are turned on
LCD driver output when all
LCD segments
corresponding to COM1 to
COM10 are turned on
T10
10
T10
T10 =
1
f10
fosc
3840
When a "set display technique" instruction with FC = 1 is executed: f10 = fosc
1920
When a "set display technique" instruction with FC = 0 is executed: f10 =
No. 7142-26/43
LC75816E, 75816W
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage
drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET,
which is 3.0V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power
supply line so that the logic block power supply voltage VDD rise time when the logic block power is first applied and the
logic block power supply voltage VDD fall time when the voltage drops are both at least 1 ms. (See Figure 3.)
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 3.)
• Power on :Logic block power supply(VDD) on → LCD driver block power supply(VLCD) on
• Power off:LCD driver block power supply(VLCD) off → Logic block power supply(VDD) off
However, if the logic and LCD driver blocks use a shared power supply, then the power supplies can be turned on and off
at the same time.
System Reset
1. Reset function
The LC75816E/W performs a system reset with the VDET. When a system reset is applied, the display is turned off, key
scanning is disabled, the key data is reset, and the general-purpose output ports are set to and held at the low level (VSS).
These states that are created as a result of the system reset can be cleared by executing the instruction described below.
(See Figure 3.)
• Clearing the display off state
Display operation can be enabled by executing a “display on/off control” instruction. However, since the contents of the
DCRAM, ADRAM, and CGRAM are undefined, applications must set the contents of these memories before turning on
display with the “display on/off control” instruction. That is, applications must execute the following instructions.
Set display technique
DCRAM data write
• ADRAM data write (If the ADRAM is used.)
• CGRAM data write (If the CGRAM is used.)
• Set AC address
• Set display contrast (If the display contrast adjustment circuit is used.)
•
•
After executing the above instructions, applications must turn on the display with a “display on/off control” instruction.
Note that when applications turn off in the normal mode, applications must turn off the display with a “display on/off
control” instruction or the INH pin.
• Clearing the key scan disable and key data reset states
Executing a "set key scan output port/general-purpose output port state" instruction not only creates a state in which
key scanning can be performed, but also clears the key data reset.
• Clearing the general-purpose output ports locked at the low level (VSS) state
Executing a "set key scan output port/general-purpose output port state" instruction clears the general-purpose output
ports locked at the low level (VSS) state and sets the states of the general-purpose output ports.
No. 7142-27/43
LC75816E, 75816W
VDD
t1 t2
t3 t4
VDET
VDET
VLCD
Initial state settings
Instruction execution
Key scan
General-purpose
output ports
Display state
Disabled
Fixed at the low level (VSS)
Execution enabled
Can be set to either the high (VDD), or low (VSS) level
Display off
Display on
“Display on/off control”
instruction execution
(Turning the display on)
“Set key scan output
port/general-purpose output
port state” instruction execution
Display off
”Display on/off control“
instruction execution
(Turning the display off)
• t1 ≥ 1 ms (Logic block power supply voltage VDD rise time)
• t2 ≥ 0 ms
• t3 ≥ 0 ms
• t4 ≥ 1 ms (Logic block power supply voltage VDD fall time)
• Initial state settings
Set display technique
DCRAM data write
ADRAM data write (If the ADRAM is used.)
CGRAM data write (If the CGRAM is used.)
Set AC address
Set display contrast (If the display contrast adjustment circuit is used.)
Figure 3
No. 7142-28/43
LC75816E, 75816W
2. Block states during a system reset
(1) CLOCK GENERATOR, TIMING GENERATOR
When a reset is applied, the oscillator on the OSCI, OSCO pins is started forcibly. This generates the base clock and
enables instruction execution.
(2) INSTRUCTION REGISTER, INSTRUCTION DECODER
When a reset is applied, these circuits are forcibly initialized internally. Then, when instruction execution starts, the
IC operates according to those instructions.
(3) ADDRESS REGISTER, ADDRESS COUNTER
When a reset is applied, these circuits are forcibly initialized internally. Then, the DCRAM and the ADRAM
addresses are set when “Set AC address” instruction is executed.
(4) DCRAM, ADRAM, CGRAM
Since the contents of the DCRAM, ADRAM, and CGRAM become undefined during a reset, applications must
execute “DCRAM data write”, “ADRAM data write (If the ADRAM is used.)”, and “CGRAM data write (If the
CGRAM is used.)” instructions before executing a “display on/off control” instruction.
(5) CGROM
Character patterns are stored in this ROM.
(6) LATCH
Although the value of the data in the latch is undefined during a reset, the ADRAM, CGROM, and CGRAM data is
stored by executing a “display on/off control” instruction.
(7) COMMON DRIVER, SEGMENT DRIVER
These circuits are forced to the display off state when a reset is applied.
(8) CONTRAST ADJUSTER
Display contrast adjustment circuit operation is disabled when a reset is applied. After that, the display contrast can be
set by executing a “set display contrast” instruction.
(9) KEY SCAN, KEY BUFFER
When a reset is applied, these circuits are forcibly initialized internally, and key scan operation is disabled. Also, the
key data is all set to 0. After that, key scanning can be performed by executing a "set key scan output port/generalpurpose output port state" instruction.
(10) CCB INTERFACE, SHIFT REGISTER
These circuits go to the serial data input wait state.
No. 7142-29/43
S1
S63
S64/COM10
S65/COM9
COM8
COM1
LC75816E, 75816W
SEGMENT DRIVER
COMMON
DRIVER
LATCH
CGRAM
5 × 9 × 16
bits
INSTRUCTION
DECODER
ADRAM
65
bits
INSTRUCTION
REGISTER
ADDRESS
COUNTER
CGROM
5 × 9 × 240
bits
VLCD
CONTRAST
ADJUSTER
VLCD0
DCRAM
52 × 8
bits
VLCD1
ADDRESS
REGISTER
VLCD2
VLCD3
VLCD4
SHIFT REGISTER
CCB INTERFACE
VDD
VDET
KEY BUFFER
TIMING
GENERATOR
VSS
KS4
KS3
P2/KS2
P1/KS1
KS6
KS5
KI4
KI3
KI2
KI1
KI5
CE
CL
DI
DO
KEY SCAN
INH
OSCI
TEST
OSCO
CLOCK
GENERATOR
Blocks that are reset
3. Output pin states during the reset period
Output pin
State during reset
S1 to S63
L (VLCD4)
S64/COM10, S65/COM9
L (VLCD4)*21
COM1 to COM8
L (VLCD4)
KS1/P1, KS2/P2
L (VSS)*22
KS3 to KS6
L (VSS)
DO
H *23
Notes: *21. These output pins are forcibly set to the segment output function and held at the low level (VLCD4). However, when a “set display technique”
instruction is executed, the segment output or the common output function is selected as specified by that instruction.
*22. These output pins are forcibly set to the general-purpose output port function and held at the low level (VSS). However, when a "set key scan
output port/general-purpose output port state" instruction has been executed, the key scan output port or general-purpose output port function will
be selected as specified by that instruction.
*23. Since this output pin is an open-drain output, a pull-up resistor (between 1 kΩ and 10 kΩ) is required. This pin is held at the high level even if a
key data read operation is performed before executing a "set key scan output port/general-purpose output port state" instruction.
No. 7142-30/43
LC75816E, 75816W
Sample Application Circuit 1
1/8 duty, 1/4 bias drive technique (for use with normal panels)
LCD panel
+5V
VDD
COM1
TEST
COM2
COM3
COM4
COM5
COM6
COM7
COM8
*24
VSS
+8V
OPEN
VLCD
VLCD0
VLCD1
VLCD2
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD3
C
C
C
VLCD4 *25
C ≥ 0.047 µF
OSCI
OSCO
INH *26
CE
CL
DI
DO K K K K K
I I I I I
5 4 3 2 1
From the
controller
To the
controller
To the
controller
power supply
P
2
/
KKKKK
SSSSS
6 5 4 3 2
S61
S62
S63
COM10/S64
P COM9/S65
1
/
K
S
1
*27
(general-purpose output ports)
used with the backlight controller
or other circuit
Key matrix
(up to 30 keys)
Notes: *24. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the
logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75816E/W is reset by the VDET.
*25. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground.
*26. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD.
*27. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 7142-31/43
LC75816E, 75816W
Sample Application Circuit 2
1/8 duty, 1/4 bias drive technique (for use with large panels)
LCD panel
+5V
VDD
COM1
TEST
VSS
COM2
COM3
COM4
COM5
COM6
COM7
COM8
*24
+8V
VLCD
VLCD0
R
VLCD1
R
VLCD2
R
VLCD3
C
C
C
R
VLCD4 *25
C ≥ 0.047 µF
10 kΩ ≥ R ≥ 2.2 kΩ
OSCI
OSCO
INH *26
CE
CL
DI
DO K K K K K
I I I I I
5 4 3 2 1
From the
controller
To the
controller
To the
controller
power supply
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S61
S62
S63
COM10/S64
P P COM9/S65
2 1
/ /
KKKKKK
SSSSSS
6 5 4 3 2 1
*27
(general-purpose output ports)
used with the backlight controller
or other circuit
Key matrix
(up to 30 keys)
Notes: *24. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the
logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75816E/W is reset by the VDET.
*25. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground.
*26. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD.
*27. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 7142-32/43
LC75816E, 75816W
Sample Application Circuit 3
1/9 duty, 1/4 bias drive technique (for use with normal panels)
LCD panel
+5V
VDD
COM1
*24
TEST
COM2
COM3
COM4
COM5
COM6
COM7
COM8
S65/COM9
VSS
+8V
OPEN
VLCD
VLCD0
VLCD1
VLCD2
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD3
C
C
C
VLCD4 *25
OSCI
C ≥ 0.047 µF
OSCO
INH *26
CE
CL
DI
DO K K K K K
I I I I I
5 4 3 2 1
From the
controller
To the
controller
To the
controller
power supply
P
2
/
KKKKK
SSSSS
6 5 4 3 2
S61
S62
S63
COM10/S64
P
1
/
K
S
1
*27
(general-purpose output ports)
used with the backlight controller
or other circuit
Key matrix
(up to 30 keys)
Notes: *24. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the
logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75816E/W is reset by the VDET.
*25. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground.
*26. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD.
*27. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 7142-33/43
LC75816E, 75816W
Sample Application Circuit 4
1/9 duty, 1/4 bias drive technique (for use with large panels)
LCD panel
+5V
VDD
COM1
*24
TEST
VSS
+8V
COM2
COM3
COM4
COM5
COM6
COM7
COM8
S65/COM9
VLCD
VLCD0
R
VLCD1
R
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD2
R
VLCD3
C
C
C
R
VLCD4 *25
C ≥ 0.047 µF
10 kΩ ≥ R ≥ 2.2 kΩ
OSCI
OSCO
INH *26
CE
CL
DI
DO K K K K K
I I I I I
5 4 3 2 1
From the
controller
To the
controller
To the
controller
power supply
P
2
/
KKKKK
SSSSS
6 5 4 3 2
S61
S62
S63
COM10/S64
P
1
/
K
S
1
*27
(general-purpose output ports)
used with the backlight controller
or other circuit
Key matrix
(up to 30 keys)
Notes: *24. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the
logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75816E/W is reset by the VDET.
*25. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground.
*26. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD.
*27. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 7142-34/43
LC75816E, 75816W
Sample Application Circuit 5
1/10 duty, 1/4 bias drive technique (for use with normal panels)
LCD panel
+5V
VDD
COM1
*24
TEST
VSS
+8V
VLCD
OPEN
C
C
VLCD0
VLCD1
VLCD2
VLCD3
COM2
COM3
COM4
COM5
COM6
COM7
COM8
S65/COM9
S64/COM10
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
C
VLCD4 *25
C ≥ 0.047 µF
OSCI
OSCO
INH *26
CE
CL
DI
DO K K K K K
I I I I I
5 4 3 2 1
From the
controller
To the
controller
To the
controller
power supply
S61
S62
S63
PP
2 1
/ /
KKKKKK
SSSSSS
6 5 4 3 2 1
(general-purpose output ports)
*27
used with the backlight controller
or other circuit
Key matrix
(up to 30 keys)
Notes: *24. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the
logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75816E/W is reset by the VDET.
*25. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground.
*26. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD.
*27. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 7142-35/43
LC75816E, 75816W
Sample Application Circuit 6
1/10 duty, 1/4 bias drive technique (for use with large panels)
LCD panel
+5V
VDD
COM1
*24
TEST
VSS
+8V
VLCD
VLCD0
R
VLCD1
R
COM2
COM3
COM4
COM5
COM6
COM7
COM8
S65/COM9
S64/COM10
VLCD2
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
R
VLCD3
C
C
C
R
VLCD4 *25
C ≥ 0.047 µF
10 kΩ ≥ R ≥ 2.2 kΩ
OSCI
OSCO
INH *26
CE
CL
DI
DO K K K K K
I I I I I
5 4 3 2 1
From the
controller
To the
controller
To the
controller
power supply
S61
S62
S63
PP
2 1
/ /
KKKKKK
SSSSSS
6 5 4 3 2 1
(general-purpose output ports)
*27
used with the backlight controller
or other circuit
Key matrix
(up to 30 keys)
Notes: *24. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the
logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75816E/W is reset by the VDET.
*25. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground.
*26. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD.
*27. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 7142-36/43
LC75816E, 75816W
Sample Correspondence between Instructions and the Display (When the LC75816-8722 is used)
No.
Instruction (hexadecimal)
LSB
MSB
Display
Operation
D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63
Power application
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
The display is in the off state.
Set display technique
2
3
Initializes the IC.
(Initialization with the VDET.)
0
8
DCRAM data write (increment mode)
0
2
0
0
1
A
DCRAM data write (increment mode)
3
5
DCRAM data write (increment mode)
1
4
DCRAM data write (increment mode)
E
4
DCRAM data write (increment mode)
9
5
DCRAM data write (increment mode)
F
4
DCRAM data write (increment mode)
0
2
DCRAM data write (increment mode)
C
4
DCRAM data write (increment mode)
3
5
DCRAM data write (increment mode)
9
4
DCRAM data write (increment mode)
0
2
DCRAM data write (increment mode)
C
4
DCRAM data write (increment mode)
3
4
DCRAM data write (increment mode)
7
3
DCRAM data write (increment mode)
5
3
DCRAM data write (increment mode)
8
3
DCRAM data write (increment mode)
1
3
DCRAM data write (increment mode)
6
3
DCRAM data write (increment mode)
0
2
0
A
Sets to 1/8 duty 1/4 bias display drive technique
Writes the display data “ ” to DCRAM address 00H
Writes the display data “S” to DCRAM address 01H
Writes the display data “A” to DCRAM address 02H
Writes the display data “N” to DCRAM address 03H
Writes the display data “Y” to DCRAM address 04H
Writes the display data “O” to DCRAM address 05H
Writes the display data “ ” to DCRAM address 06H
Writes the display data “L” to DCRAM address 07H
Writes the display data “S” to DCRAM address 08H
Writes the display data “I” to DCRAM address 09H
Writes the display data “ ” to DCRAM address 0AH
Writes the display data “L” to DCRAM address 0BH
Writes the display data “C” to DCRAM address 0CH
Writes the display data “7” to DCRAM address 0DH
Writes the display data “5” to DCRAM address 0EH
Writes the display data “8” to DCRAM address 0FH
Writes the display data “1” to DCRAM address 10H
Writes the display data “6” to DCRAM address 11H
Writes the display data “ ” to DCRAM address 12H
Continued on next page.
No. 7142-37/43
LC75816E, 75816W
Continued from preceding page.
No.
Instruction (hexadecimal)
LSB
MSB
Display
Operation
D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63
Set AC address
22
23
0
F
F
F
1
1
4
1
C
1
C
1
C
1
C
1
C
1
C
8
4
1
4
0
2
Display shift
Display shift
26
Display shift
27
Display shift
28
Display shift
29
32
2
Display shift
25
31
Loads the DCRAM address 00H and the ADRAM
0
address 0H into AC
Display on/off control
24
30
0
S ANYO
S ANYO
ANYO
NYO
YO
O
L S I
L S I
Shifts the display (MDATA only) to the left
L C 7 5
Shifts the display (MDATA only) to the left
L C 7 58
Shifts the display (MDATA only) to the left
L C 7 5 8 1
Shifts the display (MDATA only) to the left
L C 7 5 8 1 6
Shifts the display (MDATA only) to the left
L S I
L S I
L S I
L C 7 5 8 1 6
Display on/off control
0
0
F
F
0
0
Display on/off control
F
1
Set AC address
0
0
Turns on the LCD for all digits (13 digits) in MDATA
L C7
L S I
L S I
L C
Shifts the display (MDATA only) to the left
Set to sleep mode, turns off the LCD for all digits
L S I
L C 7 5 8 1 6
S ANYO
L S I
L C
Turns on the LCD for all digits (13 digits) in MDATA
Loads the DCRAM address 00H and the ADRAM
address 0H into AC
Note: *28. This sample above assumes the use of 13 digits 5 × 7 dot matrix LCD. CGRAM and ADRAM are not used.
X: don’t care
No. 7142-38/43
LC75816E, 75816W
Notes on the controller key data read techniques
1. Timer based key data acquisition
• Flowchart
CE = L
NO
DO = L
YES
Key data read
processing
• Timing chart
Key on
Key on
Key input
Key scan
t5
t6
t5
t5
CE
t8
t8
t8
Key address
DI
t7
Key data read
t7
t7
DO
Key data read request
t9
Controller
determination
(Key on)
t9
Controller
determination
(Key on)
t9
Controller
determination
(Key off)
t9
Controller
determination
(Key on)
Controller
determination
(Key off)
t5: Key scan execution time when the key data agreed for two key scans. (4800T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600T(s))
t7: Key address (43H) transfer time
t8: Key data read time
1
T = ———
fosc
• Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must
check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has
been pressed and executes the key data read operation.
The period t9 in this technique must satisfy the following condition.
t9>t6+t7+t8
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
No. 7142-39/43
LC75816E, 75816W
2. Interrupt based key data acquisition
• Flowchart
CE = L
NO
DO = L
YES
Key data read
processing
Wait for at least t10
CE = L
NO
DO = H
YES
Key off
• Timing chart
Key on
Key on
Key input
Key scan
t5
t5
t6
t5
CE
t8
t8
t8
t8
Key address
DI
t7
Key data read
t7
t7
t7
DO
Key data read request
t10
Controller
determination
(Key on)
Controller
determination
(Key off)
t10
Controller
determination
(Key on)
Controller
determination
(Key on)
t10
Controller
determination
(Key on)
t10
Controller
determination
(Key off)
t5: Key scan execution time when the key data agreed for two key scans. (4800T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600T(s))
t7: Key address (43H) transfer time
t8: Key data read time
1
T = ———
fosc
No. 7142-40/43
LC75816E, 75816W
• Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t10 has
elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must
satisfy the following condition.
t10 > t6
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
No. 7142-41/43
Lower
4bits
Upper
4bits
LC75816-8722 Character Font (Standard)
LC75816E, 75816W
No. 7142-42/43
LC75816E, 75816W
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
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This catalog provides information as of February, 2002. Specifications and information herein are subject
to change without notice.
PS No. 7142-43/43