Ordering number : ENN6860 CMOS IC LC75864E, 75864W 1/4 Duty LCD Display Drivers with Key Input Function Overview Package Dimensions The LC75864E and LC75864W are 1/4 duty LCD display drivers that can directly drive up to 96 segments and can control up to four general-purpose output ports. These products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. unit: mm 3156-QIP48E [LC75864E] 17.2 1.5 1.6 37 1.5 0.15 25 14.0 24 13 48 12 1 0.8 3.0max 1.5 1.0 17.2 0.35 36 Features 15.6 0.1 2.7 SANYO: QIP48E unit: mm 3163A-SQFP48 [LC75864W] 9.0 7.0 0.5 0.18 0.75 36 0.75 0.15 25 37 0.75 24 0.5 9.0 7.0 • Key input function for up to 30 keys (A key scan is performed only when a key is pressed.) • 1/4 duty - 1/2 bias and 1/4 duty - 1/3 bias drive schemes can be controlled from serial data (up to 96 segments). • Sleep mode and all segments off functions that are controlled from serial data • Segment output port/general-purpose output port function switching that is controlled from serial data • Serial data I/O supports CCB format communication with the system controller. • Direct display of display data without the use of a decoder provides high generality. • Independent VLCD for the LCD driver block (VLCD can be set to in the range VDD - 0.5 to 6.0 volts.) • Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays. • RC oscillator circuit 1.6 14.0 1.0 1.5 12 0.1 0.75 1 1.7max 13 48 • CCB is a trademark of SANYO ELECTRIC CO., LTD. 0.5 0.5 SANYO: SQFP48 • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN D2501TN (OT) No. 6860-1/26 LC75864E, 75864W KI4 KI3 KI2 KI1 KS6 KS5 KS4 KS3 KS2/S24 KS1/S23 COM4 COM3 Pin Assignment KI5 VDD VLCD VLCD1 VLCD2 VSS TEST OSC DO CE CL DI 36 37 25 24 LC75864E (QIP48E) LC75864W (SQFP48) 48 13 12 P1/S1 P2/S2 P3/S3 P4/S4 S5 S6 S7 S8 S9 S10 S11 S12 1 COM2 COM1 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 Top view Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Input voltage Output voltage Output current Allowable power dissipation Symbol Conditions Ratings Unit VDD max VDD –0.3 to +7.0 VLCD max VLCD –0.3 to +7.0 VIN1 CE, CL, DI VIN2 OSC, TEST VIN3 VLCD1, VLCD2, KI1 to KI5 –0.3 to +7.0 –0.3 to VDD + 0.3 DO VOUT2 OSC VOUT3 S1 to S24, COM1 to COM4, KS1 to KS6, P1 to P4 IOUT1 S1 to S24 IOUT2 COM1 to COM4 3 IOUT3 KS1 to KS6 1 IOUT4 P1 to P4 5 Ta = 85°C V –0.3 to VLCD + 0.3 VOUT1 Pd max V –0.3 to +7.0 –0.3 to VDD + 0.3 V –0.3 to VLCD + 0.3 300 150 µA mA mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C No. 6860-2/26 LC75864E, 75864W Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V Parameter Supply voltage Input voltage Input high level voltage Input low level voltage Symbol Conditions Ratings min typ max VDD VDD 4.5 6.0 VLCD VLCD VDD – 0.5 6.0 VLCD1 VLCD1 2/3 VLCD VLCD VLCD2 VLCD2 1/3 VLCD VLCD VIH1 CE, CL, DI 0.8 VDD 6.0 VIH2 KI1 to KI5 0.6 VDD VLCD 0 0.2 VDD VIL CE, CL, DI, KI1 to KI5 Unit V V V V Recommended external resistance ROSC OSC 43 kΩ Recommended external capacitance COSC OSC 680 pF Guaranteed oscillation range fOSC OSC 25 50 100 kHz Data setup time tds CL, DI: Figure 2 160 ns Data hold time tdh CL, DI: Figure 2 160 ns CE wait time tcp CE, CL: Figure 2 160 ns CE setup time tcs CE, CL: Figure 2 160 ns CE hold time tch CE, CL: Figure 2 160 ns High level clock pulse width tøH CL: Figure 2 160 ns Low level clock pulse width tøL CL: Figure 2 160 ns Rise time tr CE, CL, DI: Figure 2 160 Fall time tf CE, CL, DI: Figure 2 160 ns ns DO output delay time tdc DO, RPU = 4.7 kΩ, CL = 10 pF*1: Figure 2 1.5 µs DO rise time tdr DO, RPU = 4.7 kΩ, CL = 10 pF*1: Figure 2 1.5 µs Note: *1. Since DO is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load capacitance CL. No. 6860-3/26 LC75864E, 75864W Electrical Characteristics for the Allowable Operating Ranges Parameter Hysteresis Power-down detection voltage Symbol VH Conditions IIH CE, CL, DI: VI = 6.0 V IIL CE, CL, DI: VI = 0 V Input floating voltage VIF KI1 to KI5 Pull-down resistance RPD KI1 to KI5: VDD = 5.0 V Output low level voltage Output middle level voltage*2 Oscillator frequency Current drain Unit max 0.1 VDD 2.5 Input high level current Output high level voltage typ CE, CL, DI, KI1 to KI5 VDET Input low level current Output off leakage current Ratings min 3.0 V 3.5 V 5.0 µA –5.0 µA 0.05 VDD V 50 100 250 kΩ 6.0 µA VLCD – 0.5 VLCD – 0.2 IOFFH DO: VO = 6.0 V VOH1 KS1 to KS6: IO = –500 µA VLCD – 1.0 VOH2 P1 to P4: IO = –1 mA VLCD – 1.0 VOH3 S1 to S24: IO = –20 µA VLCD – 1.0 VOH4 COM1 to COM4: IO = –100 µA VLCD – 1.0 VOL1 KS1 to KS6: IO = 25 µA VOL2 P1 to P4: IO = 1 mA 1.0 VOL3 S1 to S24: IO = 20 µA 1.0 VOL4 COM1 to COM4: IO = 100 µA 1.0 VOL5 DO: IO = 1 mA 0.2 V 0.5 0.1 1.5 0.5 VMID1 COM1 to COM4: 1/2 bias, IO = ±100 µA 1/2 VLCD – 1.0 VMID2 S1 to S24: 1/3 bias, IO = ±20 µA 2/3 VLCD – 1.0 2/3 VLCD + 1.0 VMID3 S1 to S24: 1/3 bias, IO = ±20 µA 1/3 VLCD – 1.0 1/3 VLCD + 1.0 VMID4 COM1 to COM4: 1/3 bias, IO = ±100 µA 2/3 VLCD – 1.0 2/3 VLCD + 1.0 VMID5 COM1 to COM4: 1/3 bias, IO = ±100 µA 1/3 VLCD – 1.0 1/3 VLCD + 1.0 fOSC OSC: ROSC = 43 kΩ, COSC = 680 pF IDD1 VDD: Sleep mode 40 50 V 1/2 VLCD + 1.0 60 V kHz 100 IDD2 VDD: VDD = 6.0 V, output open, fOSC = 50 kHz ILCD1 VLCD: Sleep mode ILCD2 ILCD3 270 540 VLCD: VLCD = 6.0 V, output open, 1/2 bias, fOSC = 50 kHz 100 200 VLCD: VLCD = 6.0 V, output open, 1/3 bias, fOSC = 50 kHz 60 120 5 µA Note: *2. Excluding the bias voltage generation divider resistor built into VLCD1 and VLCD2. (See Figure 1.) VLCD VLCD1 To the common segment driver VLCD2 Excluding these resistors. Figure 1 No. 6860-4/26 LC75864E, 75864W 1. When CL is stopped at the low level VIH1 CE VIL tøH CL tøL VIH1 50% VIL tr DI tf tcp tch tcs VIH1 VIL tds tdh tdc DO D0 tdr D1 2. When CL is stopped at the high level VIH1 CE VIL tøL tøH VIH1 50% VIL CL tf tr DI tch tcs VIL tds DO tcp VIH1 tdh D0 D1 tdc tdr Figure 2 No. 6860-5/26 LC75864E, 75864W S1/P1 S2/P2 S3/P3 S4/P4 S5 S22 COM1 COM2 COM3 COM4 Block Diagram VLCD SEGMENT DRIVER & LATCH VLCD1 COMMON DRIVER VLCD2 SHIFT REGISTER VSS TEST CLOCK GENERATOR OSC CONTROL REGISTER DO CCB INTERFACE DI KEY BUFFER CL CE VDD VDET KS6 KS5 KS4 KS3 S24/KS2 S23/KS1 KI5 KI4 KI3 KI2 KI1 KEY SCAN No. 6860-6/26 LC75864E, 75864W Pin Functions Pin Pin No. S1/P1 to S4/P4 1 to 4 S5 to S22 5 to 22 COM1 23 COM2 24 COM3 25 COM4 26 KS1/S23 27 KS2/S24 28 KS3 to KS6 29 to 32 KI1 to KI5 33 to 37 OSC 44 CE 46 CL 47 DI 48 DO Active I/O Handling when unused — O Open Common driver outputs The frame frequency fO is given by: fO = (fOSC/512) Hz. — O Open Key scan outputs Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. The KS1/S23 and KS2/S24 pins can be used as segment outputs when so specified by the control data. — O Open Key scan inputs These pins have built-in pull-down resistors. H I GND Oscillator connection An oscillator circuit is formed by connecting an external resistor and capacitor at this pin. — I/O VDD H I Function Segment outputs for displaying the display data transferred by serial data input. The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial data control. Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. I GND — I 45 CE: Chip enable CL: Synchronization clock DI: Transfer data DO: Output data — O Open TEST 43 This pin must be connected to ground. — I — VLCD1 40 Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to VLCD2 when a 1/2 bias drive scheme is used. — I Open VLCD2 41 Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to VLCD1 when a 1/2 bias drive scheme is used. — I Open VDD 38 Logic block power supply connection. Provide a voltage of between 4.5 and 6.0 V. — — — VLCD 39 LCD driver block power supply connection. Provide a voltage of between VDD – 0.5 and 6.0 V. — — — VSS 42 Power supply connection. Connect to ground. — — — No. 6860-7/26 LC75864E, 75864W Serial Data Input 1. When CL is stopped at the low level CE CL DI 0 1 0 0 0 0 1 0 D1 D2 D47 D48 0 Display data 0 0 0 0 0 D49 D50 D95 D96 0 Display data 0 0 0 0 0 D1 D2 D47 D48 0 Display data 0 0 0 0 0 D49 D50 D95 D96 0 Display data 0 0 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 S0 S1 K0 K1 P0 P1 P2 SC DR 0 DD Control data DO 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 0 0 Fixed data 0 0 0 0 0 0 1 DD Note: B0 to B3, A0 to A3 ... CCB address DD ... Direction data 2. When CL is stopped at the high level CE CL DI 0 1 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 0 A3 S0 S1 K0 K1 P0 P1 P2 SC DR 0 DD Control data DO 0 1 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 0 A3 0 0 0 Fixed data 0 0 0 0 0 0 1 DD Note: B0 to B3, A0 to A3 ... CCB address DD ... Direction data • • • • • • • CCB address......42H D1 to D96..........Display data S0, S1 ................Sleep control data K0, K1...............Key scan output/segment output selection data P0 to P2 .............Segment output port/general-purpose output port selection data SC......................Segment on/off control data DR .....................1/2 bias or 1/3 bias drive selection data No. 6860-8/26 LC75864E, 75864W Control Data Functions 1. S0, S1: Sleep control data These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS6 key scan outputs during key scan standby. Control data Output pin states during key scan standby Mode OSC oscillator Segment outputs Common outputs KS1 KS2 KS3 KS4 KS5 KS6 0 Normal Operating Operating H H H H H H 0 1 Sleep Stopped L L L L L L H 1 0 Sleep Stopped L L L L L H H 1 1 Sleep Stopped L H H H H H H S0 S1 0 Note: This assumes that the KS1/S23 and KS2/S24 output pins are selected for key scan output. 2. K0, K1: Key scan output/segment output selection data These control data bits switch the functions of the KS1/S23 and KS2/S24 output pins between key scan output and segment output. Control data Output pin state Maximum number of input keys K0 K1 KS1/S23 KS2/S24 0 0 KS1 KS2 30 0 1 S23 KS2 25 1 ✕ S23 S24 20 Notes: KSn (n = 1 , 2): Key scan output Sn (n = 23, 24): Segment output ✕: don’t care 3. P0 to P2: Segment output port/general-purpose output port selection data These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and the general-purpose output port. Control data Output pin state P0 P1 P2 S1/P1 S2/P2 S3/P3 S4/P4 0 0 0 S1 S2 S3 S4 0 0 1 P1 S2 S3 S4 0 1 0 P1 P2 S3 S4 0 1 1 P1 P2 P3 S4 1 0 0 P1 P2 P3 P4 Notes: Sn (n = 1 to 4): Segment output port Pn (n = 1 to 4): General-purpose output port The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports. Output pin Corresponding display data S1/P1 D1 S2/P2 D5 S3/P3 D9 S4/P4 D13 For example, if the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a high level (VLCD) when the display data D13 is 1, and will output a low level(VSS) when D13 is 0. 4. SC: Segment on/off control data This control data bit controls the on/off state of the segments. SC Display state 0 On 1 Off However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. No. 6860-9/26 LC75864E, 75864W 5. DR: 1/2 bias or 1/3 bias drive selection data This control data bit switches between LCD 1/2 bias or 1/3 bias drive. DR Drive scheme 0 1/3 bias drive 1 1/2 bias drive Display Data and Output Pin Correspondence Output pin COM1 COM2 COM3 COM4 Output pin COM1 COM2 COM3 COM4 S1/P1 D1 D2 D3 D4 S13 D49 D50 D51 D52 S2/P2 D5 D6 D7 D8 S14 D53 D54 D55 D56 S3/P3 D9 D10 D11 D12 S15 D57 D58 D59 D60 S4/P4 D13 D14 D15 D16 S16 D61 D62 D63 D64 S5 D17 D18 D19 D20 S17 D65 D66 D67 D68 S6 D21 D22 D23 D24 S18 D69 D70 D71 D72 S7 D25 D26 D27 D28 S19 D73 D74 D75 D76 S8 D29 D30 D31 D32 S20 D77 D78 D79 D80 S9 D33 D34 D35 D36 S21 D81 D82 D83 D84 S10 D37 D38 D39 D40 S22 D85 D86 D87 D88 S11 D41 D42 D43 D44 KS1/S23 D89 D90 D91 D92 S12 D45 D46 D47 D48 KS2/S24 D93 D94 D95 D96 Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S23, and KS2/S24 are selected for use as segment outputs. For example, the table below lists the segment output states for the S11 output pin. Display data Output pin state (S11) D41 D42 D43 D44 0 0 0 0 The LCD segments for COM1, COM2, COM3 and COM4 are off. 0 0 0 1 The LCD segment for COM4 is on. 0 0 1 0 The LCD segment for COM3 is on. 0 0 1 1 The LCD segments for COM3 and COM4 are on. 0 1 0 0 The LCD segment for COM2 is on. 0 1 0 1 The LCD segments for COM2 and COM4 are on. 0 1 1 0 The LCD segments for COM2 and COM3 are on. 0 1 1 1 The LCD segments for COM2, COM3 and COM4 are on. 1 0 0 0 The LCD segment for COM1 is on. 1 0 0 1 The LCD segments for COM1 and COM4 are on. 1 0 1 0 The LCD segments for COM1 and COM3 are on. 1 0 1 1 The LCD segments for COM1, COM3 and COM4 are on. 1 1 0 0 The LCD segments for COM1 and COM2 are on. 1 1 0 1 The LCD segments for COM1, COM2 and COM4 are on. 1 1 1 0 The LCD segments for COM1, COM2 and COM3 are on. 1 1 1 1 The LCD segments for COM1, COM2, COM3 and COM4 are on. No. 6860-10/26 LC75864E, 75864W Serial Data Output 1. When CL is stopped at the low level CE CL DI 1 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 DO X KD1 KD2 KD27 KD28 KD29 KD30 SA Output data Note: B0 to B3, A0 to A3 ... CCB address X: don’t care 2. When CL is stopped at the high level CE CL DI 1 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 DO X KD1 KD2 KD3 KD28 KD29 KD30 Output data Note: B0 to B3, A0 to A3 ... CCB address SA X X: don’t care • CCB address...............43H • KD1 to KD30 .............Key data • SA...............................Sleep acknowledge data Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. Output Data 1. KD1 to KD30: Key data When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits. KS1/S23 KI1 KI2 KI3 KI4 KI5 KD1 KD2 KD3 KD4 KD5 KS2/S24 KD6 KD7 KD8 KD9 KD10 KS3 KD11 KD12 KD13 KD14 KD15 KS4 KD16 KD17 KD18 KD19 KD20 KS5 KD21 KD22 KD23 KD24 KD25 KS6 KD26 KD27 KD28 KD29 KD30 When the KS1/S23 and KS2/S24 output pins are selected to be segment outputs by control data bits K0 and K1 and a key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to KD10 key data bits will be set to 0. 2. SA: Sleep acknowledge data This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep mode and 0 in normal mode. No. 6860-11/26 LC75864E, 75864W Sleep Mode Functions Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the S1/P1 to S4/P4 outputs can be used as general-purpose output ports according to the state of the P0 to P2 control data bits, even in sleep mode. (See the control data description for details.) Key Scan Operation Functions 1. Key scan timing The key scan period is 384 T (s). To reliably determine the on/off state of the keys, the LC75864E/W scans the keys twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on DO) 800 T (s) after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the keys again. Thus the LC75864E/W cannot detect a key press shorter than 800 T (s). KS1 *3 KS2 *3 KS3 *3 1 1 2 *3 2 3 *3 3 *3 T= KS4 *3 KS5 *3 4 4 5 5 KS6 *3 6 1 fosc *3 6 768T (s) Key on Note: *3. In sleep mode the high/low state of these pins is determined by the S0 and S1 bits in the control data. Key scan output signals are not output from pins that are set low. 2. In normal mode • The pins KS1 to KS6 are set high • When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. 1 • If a key is pressed for longer than 800 T (s) (where T = ) the LC75864E/W outputs a key data read request (a fOSC low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. • After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75864E/W performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10 kΩ). No. 6860-12/26 LC75864E, 75864W Key input 1 Key input 2 Key scan 800T(s) 800T(s) 800T(s) CE Serial data transfer Serial data transfer Key address (43H) Serial data transfer Key address Key address DI DO Key data read Key data read request Key data read Key data read Key data read request Key data read request T= 1 fosc 3. In sleep mode • The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the control data. (See the control data description for details.) • If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. 1 • If a key is pressed for longer than 800 T (s) (where T = ) the LC75864E/W outputs a key data read request (a fOSC low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. • After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75864E/W performs another key scan. However, this does not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10 kΩ). • Sleep mode key scan example Example: S0 = 0, S1 = 1 (sleep with only KS6 high) When any one of these keys is pressed, the oscillator on the OSC pin is started and the keys are scanned. Note *4. These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time. No. 6860-13/26 LC75864E, 75864W Key input (KS6 line) Key scan 800T(s) 800T(s) CE Serial data transfer Serial data transfer Key address (43H) Serial data transfer Key address DI T= 1 fosc DO Key data read Key data read request Key data read Key data read request Multiple Key Presses Although the LC75864E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data. No. 6860-14/26 LC75864E, 75864W 1/4 Duty, 1/2 Bias Drive Technique fosc 512 (Hz) COM1 VLCD VLCD1, VLCD2 0V COM2 VLCD VLCD1, VLCD2 0V COM3 VLCD VLCD1, VLCD2 0V COM4 VLCD VLCD1, VLCD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are turned off. VLCD VLCD1, VLCD2 0V LCD driver output when only LCD segments corresponding to COM1 are on VLCD VLCD1, VLCD2 0V LCD driver output when only LCD segments corresponding to COM2 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM1 and COM2 are on. VLCD VLCD1, VLCD2 0V LCD driver output when only LCD segments corresponding to COM3 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM1 and COM3 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM2 and COM3 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM1, COM2 and COM3 are on. VLCD VLCD1, VLCD2 0V LCD driver output when only LCD segments corresponding to COM4 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM2 and COM4 are on. VLCD VLCD1, VLCD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are on. VLCD VLCD1, VLCD2 0V 1/4 Duty, 1/2 Bias Waveforms No. 6860-15/26 LC75864E, 75864W 1/4 Duty, 1/3 Bias Drive Technique fosc 512 (Hz) VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V COM1 COM2 COM3 COM4 LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are turned off. LCD driver output when only LCD segments corresponding to COM1 are on LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM1 and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when LCD segments corresponding to COM1, COM2 and COM3 are on. LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are on. 1/4 Duty, 1/3 Bias Waveforms No. 6860-16/26 LC75864E, 75864W Voltage Detection Type Reset Circuit (VDET) This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET, which is 3.0 V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage VDD rise time when the logic block power is first applied and the logic block power supply voltage VDD fall time when the voltage drops are both at least 1 ms. (See Figure 3.) Power Supply Sequence The following sequences must be observed when power is turned on and off. (See Figure 3.) • Power on: Logic block power supply (VDD) on → LCD driver block power supply (VLCD) on. • Power off: LCD driver block power supply (VLCD) off → Logic block power supply (VDD) off. However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. System Reset The LC75864E/W supports the reset method described below. When a system reset is applied, display is turned off, key scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning become possible. 1. Reset method • Reset at power-on and power-down If at least 1 ms is assured as the logic block supply voltage VDD rise time when logic block power is applied, a system reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1 ms is assured as the logic block supply voltage VDD fall time when logic block power drops, a system reset will be applied in the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (the display data D1 to D96 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has been transferred. (See Figure 3.) t1 t2 t3 t4 VDD VDET VDET VLCD CE VIL Display and control data transfer D1 to D48 Internal data S0, S1, K0, K1 P0 to P2, SC, DR Undefined Defined Undefined Internal data (D49 to D96) Undefined Defined Undefined System reset period Note: • t1 ≥ 1 [ms] (Logic block power supply voltage VDD rise time) • t2 ≥ 0 • t3 ≥ 0 • t4 ≥ 1 [ms] (Logic block power supply voltage VDD fall time) Figure 3 No. 6860-17/26 LC75864E, 75864W S1/P1 S2/P2 S3/P3 S4/P4 S5 S22 COM1 COM2 COM3 COM4 2. LC75864E/W internal block states during the reset period • CLOCK GENERATOR Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined after the S0 and S1 control data bits are transferred. • COMMON DRIVER, SEGMENT DRIVER & LATCH Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state. • KEY SCAN Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled. • KEY BUFFER Reset is applied and all the key data is set to low. • CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER Since serial data transfer is possible, these circuits are not reset. VLCD SEGMENT DRIVER & LATCH VLCD1 COMMON DRIVER VLCD2 SHIFT REGISTER VSS TEST CLOCK GENERATOR OSC CONTROL REGISTER DO CCB INTERFACE DI KEY BUFFER CL CE VDD VDET KS6 KS5 KS4 KS3 S24/KS2 S23/KS1 KI5 KI4 KI3 KI2 KI1 KEY SCAN Blocks that are reset No. 6860-18/26 LC75864E, 75864W 3. Output pin states during the reset period Output pin S1/P1 to S4/P4 State during reset L*5 S5 to S22 L COM1 to COM4 L KS1/S23, KS2/S24 L*5 KS3 to KS5 ✕*6 KS6 H DO H*7 ✕: don’t care Note: * 5. These output pins are forcibly set to the segment output function and held low. * 6. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred. * 7. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period even if a key data read operation is performed. No. 6860-19/26 LC75864E, 75864W Sample Application Circuit 1 1/2 bias (for use with normal panels) (P1) (P2) (P3) (P4) OSC COM1 COM2 COM3 COM4 P1/S1 P2/S2 P3/S3 P4/S4 S5 *8 VSS TEST +5.5V VLCD VLCD1 LCD panel (up to 96 segments) VDD +5V VLCD2 C ≥ 0.047 µF CE CL DI K K K K K DO I I I I I 5 4 3 2 1 From the controller To the controller To the controller power supply S 2 4 / KKKKK SSSSS 6 5 4 3 2 S S22 2 3 / K S 1 (general-purpose output ports) Used with the backlight controller or other circuit. (S23) (S24) *9 Key matrix (up to 30 keys) Note: *8.Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75864E/W is reset by the VDET. *9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6860-20/26 LC75864E, 75864W Sample Application Circuit 2 1/2 bias (for use with large panels) (P1) (P2) (P3) (P4) OSC COM1 COM2 COM3 COM4 P1/S1 P2/S2 P3/S3 P4/S4 S5 *8 10 kΩ ≥ R ≥ 1 kΩ C ≥ 0.047 µF VSS TEST +5.5V VLCD R C VLCD2 CE CL DI K K K K K DO I I I I I 5 4 3 2 1 From the controller To the controller To the controller power supply R VLCD1 S 2 4 / KKKKK SSSSS 6 5 4 3 2 S S22 2 3 / K S 1 LCD panel (up to 96 segments) VDD +5V (general-purpose output ports) Used with the backlight controller or other circuit. (S23) (S24) *9 Key matrix (up to 30 keys) Note: *8.Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75864E/W is reset by the VDET. *9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6860-21/26 LC75864E, 75864W Sample Application Circuit 3 1/3 bias (for use with normal panels) (P1) (P2) (P3) (P4) OSC COM1 COM2 COM3 COM4 P1/S1 P2/S2 P3/S3 P4/S4 S5 *8 VSS TEST +5.5V VLCD VLCD1 C ≥ 0.047 µF VLCD2 C C CE CL DI K K K K K DO I I I I I 5 4 3 2 1 From the controller To the controller To the controller power supply LCD panel (up to 96 segments) VDD +5V S 2 4 / KKKKK SSSSS 6 5 4 3 2 S S22 2 3 / K S 1 (general-purpose output ports) Used with the backlight controller or other circuit. (S23) (S24) *9 Key matrix (up to 30 keys) Note: *8.Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75864E/W is reset by the VDET. *9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6860-22/26 LC75864E, 75864W Sample Application Circuit 4 1/3 bias (for use with large panels) (P1) (P2) (P3) (P4) VDD OSC COM1 COM2 COM3 COM4 P1/S1 P2/S2 P3/S3 P4/S4 S5 *8 10 kΩ ≥ R ≥ 1 kΩ C ≥ 0.047 µF VSS TEST VLCD +5.5V R VLCD1 R C C To the controller To the controller power supply VLCD2 R CE CL DI K K K K K DO I I I I I 5 4 3 2 1 From the controller LCD panel (up to 96 segments) +5V S 2 4 / KKKKK SSSSS 6 5 4 3 2 S S22 2 3 / K S 1 (general-purpose output ports) Used with the backlight controller or other circuit. (S23) (S24) *9 Key matrix (up to 30 keys) Note: *8.Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75864E/W is reset by the VDET. *9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. Notes on transferring display data from the controller The display data (D1 to D96) is transferred to the LC75864E/W in two operations. All of the display data should be transferred within 30 ms to maintain the quality of the displayed image. No. 6860-23/26 LC75864E, 75864W Notes on the controller key data read techniques 1. Timer based key data acquisition (1) Flowchart Key data read processing (2) Timing chart Key on Key on Key input Key scan t5 t6 t5 t5 CE t8 t8 t8 Key address DI t7 Key data read t7 t7 DO Key data read request t9 Controller determination (Key on) t9 Controller determination (Key on) t9 Controller determination (Key off) t9 Controller determination (Key on) Controller determination (Key off) t5: Key scan execution time when the key data agreed for two key scans. (800 T (s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1600 T (s)) 1 T= fOSC t7: Key address (43H) transfer time t8: Key data read time (3) Explanation In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t9 in this technique must satisfy the following condition. t9 > t6 + t7 + t8 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. No. 6860-24/26 LC75864E, 75864W 2. Interrupt based key data acquisition (1) Flowchart Key data read processing Wait for at least t10 (2) Timing chart Key on Key on Key input Key scan t5 t5 t5 t6 CE t8 t8 t8 t8 Key address DI t7 Key data read t7 t7 t7 DO Key data read request t10 t10 Controller determination (Key on) Controller determination (Key off) Controller determination (Key on) Controller determination (Key on) t10 t10 Controller determination (Key on) Controller determination (Key off) t5: Key scan execution time when the key data agreed for two key scans. (800 T (s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1600 T (s)) 1 T= fOSC t7: Key address (43H) transfer time t8: Key data read time No. 6860-25/26 LC75864E, 75864W (3)Explanation In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t10 has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must satisfy the following condition. t10 > t6 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. 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Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 2001. Specifications and information herein are subject to change without notice. PS No. 6860-26/26