Ordering number : EN*5130 CMOS LSI LC78620E Compact Disc Player DSP Preliminary Overview The LC78620E is a CMOS LSI that implements the signal processing and servo control required by compact disk players, laser disks, CD-V, CD-I and related products. The LC78620E provides several types of signal processing, including demodulation of the optical pickup EFM signal, de-interleaving, error detection and correction, and digital filters that can help reduce the cost of CD player units. It also processes a rich set of servo system commands sent from the control microprocessor. It also incorporates an EFM-PLL circuit and a one-bit D/A converter. Functions • Input signal processing: The LC78620E takes an HF signal as input, digitizes (slices) that signal at a precise level, converts that signal to an EFM signal, and generates a PLL clock with an average frequency of 4.3218 MHz by comparing the phases of that signal and an internal VCO. • Precise reference clock and necessary internal timing generation using an external 16.9344 MHz crystal oscillator • Disk motor speed control using a frame phase difference signal generated from the playback clock and the reference clock • Frame synchronization signal detection, protection and interpolation to assure stable data readout • EFM signal demodulation and conversion to 8-bit symbol data • Subcode data separation from the EFM demodulated signal and output of that data to an external microprocessor • Subcode Q signal output to a microprocessor over the serial I/O interface after performing a CRC error check • Demodulated EFM signal buffering in internal RAM to handle up to ±4 frames of disk rotational jitter • Demodulated EFM signal reordering in the prescribed order for data unscrambling and de-interleaving • Error detection, correction, and flag processing (error correction scheme: dual C1 plus dual C2 correction) • The LC78620E sets the C2 flags based on the C1 flags and a C2 check, and then performs signal interpolation or muting depending on the C2 flags. The interpolation circuit uses a quadruple interpolation scheme. The output value converges to the muting level when four or more consecutive C2 flags occur. • Support for command input from a control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8 bit serial input) • Built-in digital output circuits. • Arbitrary track counting to support high-speed data access • Zero cross muting • D/A converter outputs with data continuity improved by 8× oversampling digital filters. (These filters function as 4× oversampling filters during double-speed playback.) • Built-in third-order ∑∆ D/A converters (PWM output) • Built-in digital attenuator (8 bits – alpha, 239 steps) • Built-in digital de-emphasis • Built-in digital level and peak meter functions • Support for bilingual applications Features • 80-pin QIP (miniature, reduced space package) • Silicon gate CMOS process (for low power) • 5 V single-voltage power supply (for use in portable products) Package Dimensions unit: mm [LC78620E] SANYO: QIP80E 3174-QFP80E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 92895HA (OT) No. 5130-1/34 LC78620E Equivalent Circuit Block Diagram Pin Assignment No. 5130-2/34 LC78620E Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Ratings Unit Maximum supply voltage Parameter VDD max Symbol VSS – 0.3 to VSS + 7.0 V Maximum input voltage VIN max VSS – 0.3 to VDD + 0.3 V VOUT max VSS – 0.3 to VDD + 0.3 Maximum output voltage Allowable power dissipation Conditions Pd max 300 V mW Operating temperature Topr –20 to +75 °C Storage temperature Tstg –40 to +125 °C max Unit Allowable Operating Ranges at Ta = 25°C, VSS = 0 V Parameter Supply voltage Symbol VDD Conditions min typ 4.5 5.5 V DEFI, FZD, ASDACK, ASDFIN, ASDFIR, ASLRCK, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, DEMO, CS 0.7 VDD VDD V VIH (2) EFMIN 0.6 VDD VDD V VIL (1) DEFI, FZD, ASDACK, ASDFIN, ASDFIR, ASLRCK, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, DEMO, CS 0 0.3 VDD V VIL (2) EFMIN 0 0.4 VDD tset up COIN, RWC: Figure 1 400 ns Data hold time thold COIN, RWC: Figure 1 400 ns High level clock pulse width tWøH SBCK, CQCK: Figures 1, 2 and 3 400 ns Low level clock pulse width tWøL SBCK, CQCK: Figures 1, 2 and 3 400 Data read access time tRAC SQOUT, PW: Figures 2 and 3 Command transfer time tRWC RWC: Figure 1 Subcode Q read enable time tSQE WRQ: Figure 2, with no RWC signal Input high level voltage Input low level voltage Data setup time VIH (1) VDD, XVDD, LVDD, RVDD, VVDD V ns 0 400 1000 ns ns 11.2 ms 136 µs Subcode read cycle time tsc SFSY: Figure 3 Subcode read enable time tse SFSY: Figure 3 400 ns EFMIN 1.0 Vp-p XIN: Input capacitor coupled 1.0 VIN (1) Input level VIN (2) Operating frequency range Crystal oscillator frequency fop Vp-p EFMIN 10 MHz fX (1) XIN, XOUT: In 16M mode 16.9344 MHz fX (2) XIN, XOUT: In 32M mode 33.8688 MHz Note: Due to the structure of this LSI, an identical voltage must be supplied to all the power supply pins. Electrical Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V Parameter Current drain Input high level current Input low level current Output high level voltage Symbol Conditions min IDD typ max Unit 30 45 mA 5 µA 75 µA IIH (1) DEFI, EFMIN, FZD, ASDACK, ASDFIN, ASDFIR, ASLRCK, COIN, RES, HFL, TES, SBCK, RWC, CQCK: VIN = 5 V IIH (2) TAI, TEST1 to TEST5, DEMO, CS: VIN = VDD = 5.5 V 25 IIL DEFI, EFMIN, FZD, ASDACK, ASDFIN, ASDFIR, ASLRCK, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, DEMO, CS: VIN = 0 V –5 µA VOH (1) EFMO, EFMO, CLV+, CLV–, V/P, FOCS, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP–, EMPH, EFLG, FSX: IOH = –1 mA 4 V VOH (2) MUTEL, MUTER, LRCKO, DFORO, DFOLO, DACKO, TST10, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT: IOH = –0.5 mA 4 V V VOH (3) LASER: IOH = –1 mA 4.6 VOH (4) DOUT: IOH = –12 mA 4.5 VOH (5) LCHP, RCHP, LCHN, RCHN: IOH = –1mA 3.0 V 4.5 V Continued on next page. No. 5130-3/34 LC78620E Continued from preceding page. Parameter Output low level voltage Output off leakage current Charge pump output current Symbol Conditions VOL (1) EFMO, EFMO, CLV+, CLV–, V/P, FOCS, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP–, EMPH, EFLG, FSX: IOL = 1 mA 1 V VOL (2) MUTEL, MUTER, LRCKO, DFORO, DFOLO, DACKO, TST10, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT, LASER: IOL = 2 mA 0.4 V VOL (3) DOUT: IOL = 12 mA VOL (4) FST: IOL = 5 mA VOL (5) LCHP, RCHP, LCHN, RCHN: IOL = 1mA IOFF (1) PDO, CLV+, CLV–, JP+, JP–, FST: VOUT = 5 V IOFF (2) PDO, CLV+, CLV–, JP+, JP–: VOUT = 0 V min typ 0.5 max Unit 0.5 V 0.75 V 2.0 V 5 µA –5 µA IPDOH PDO: RISET = 68 kΩ 100 125 150 µA IPDOL PDO: RISET = 68 kΩ –150 –125 –100 µA typ max Unit 0.008 0.010 % Note: For guaranteed operation, the VCO oscillator frequency range adjustment resistor FR must be a 5.10 kΩ ±1.0% tolerance resistor. One-Bit D/A Converter Analog Characteristics at Ta = 25°C, VDD = LVDD = RVDD = 5 V, VSS = LVSS = RVSS = 0 V Parameter Total harmonic distortion Symbol Conditions THD + N LCHP, RCHP, LCHN, RCHN; 1 kHz: 0 dB data input, using the 20 kHz low-pass filter (AD725D built in) min Dynamic range DR LCHP, RCHP, LCHN, RCHN; 1 kHz: –60 dB data input, using the 20 kHz low-pass filter and the A filter (AD725D built in) 84 88 dB Signal-to-noise ratio S/N LCHP, RCHP, LCHN, RCHN; 1 kHz: 0 dB data input, using the 20 kHz low-pass filter and the A filter (AD725D built in) 98 100 dB Crosstalk CT LCHP, RCHP, LCHN, RCHN; 1 kHz: 0 dB data input, using the 20 kHz low-pass filter (AD725D built in) 96 98 dB Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit set to EE (hexadecimal). Figure 1 Command Input No. 5130-4/34 LC78620E Figure 2 Subcode Q Output Figure 3 Subcode Output No. 5130-5/34 LC78620E One-Bit D/A Converter Output Block Reference Circuit (normal speed playback) No. 5130-6/34 LC78620E Pin Functions Pin No. Symbol I/O 1 DEFI I Function Defect detection signal (DEF) input (Must be tied low if unused.) 2 TAI I Test input. A pull-down resistor is built in. 3 PDO O External VCO control phase comparator output 4 VVSS 5 ISET 6 VVDD 7 FR 8 VSS AI PLL pins Internal VCO ground. Normally 0 V. PDO output current adjustment resistor connection Internal VCO power supply. Normally 5 V. AI VCO frequency range adjustment Digital system ground. Normally 0 V. 9 EFMO O 10 EFMO O EFM signal inverted output Slice level control EFM signal output 11 EFMIN I 12 TEST2 I Test input. A pull-down resistor is built in. EFM signal input 13 CLV+ O Spindle servo control output. Acceleration when CLV+ is high, deceleration when CLV– is high 14 CLV– O Three-value output is also possible when specified by microprocessor command. 15 V/P O Rough servo/phase control automatic switching monitor output. Outputs a high level during rough servo and a low level during phase control. 16 FOCS O Focus servo on/off output. Focus servo is on when the output is low. 17 FST O Focus start pulse output. This is an open-drain output. 18 FZD I Focus error zero cross signal input. (Must be tied low if unused.) 19 HFL I Track detection signal input. This is a Schmitt input. 20 TES I Tracking error signal input. This is a Schmitt input. 21 PCK O EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked. 22 FSEQ O Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM signal and the internally generated synchronization signal agree. 23 TOFF O Tracking off output 24 TGL O Tracking gain switching output. Increase the gain when low. 25 THLD O Tracking hold output 26 TEST3 I Test input. A pull-down resistor is built in. 27 VDD 28 JP+ O 29 JP– O Track jump output. A high level output from JP+ indicates acceleration during an outward jump or deceleration during an inward jump. A high level output from JP– indicates acceleration during an inward jump or deceleration during an outward jump. Three-value output is also possible when specified by microprocessor command. 30 DEMO I Sound output function input used for end product adjustment manufacturing steps. A pull-down resistor is built in. 31 TEST4 I Test input. A pull-down resistor is built in. 32 EMPH O De-emphasis monitor pin. A high level indicates playback of a de-emphasis disk. 33 LRCKO O 34 DFORO O 35 DFOLO O 36 DACKO O 37 TST10 O 38 ASDACK I 39 ASDFIN I 40 ASDFIR I 41 ASLRCK I Digital system power supply. Normally 5 V. Word clock output Digital filter outputs Right channel data output Left channel data output Bit clock output Test output. Leave open. (Normally outputs a low level.) Bit clock input Left/right channel data input Antishock system inputs (Must be tied low if unused.) Test input. (Should be tied low for normal operation.) Word clock input Continued on next page. No. 5130-7/34 LC78620E Continued from preceding page. Pin No. Symbol I/O 42 LRSY O 43 CK2 O 44 ROMXA O Function Left/right clock output ROMXA application output signals Bit clock output (after reset) Inverted polarity clock output (during CK2CON mode) Interpolation data output (after reset) ROM data output (During ROMXA mode) 45 C2F O C2 flag output 46 MUTEL O Left channel mute output 47 LVDD 48 LCHP O Left channel P output 49 LCHN O Left channel N output 50 LVSS 51 RVSS 52 RCHN O Right channel N output 53 RCHP O Right channel P output O Right channel mute output 54 RVDD 55 MUTER Left channel power supply. Normally 5 V. One-bit D/A converter Left channel ground. Normally 0 V. Right channel ground. Normally 0 V. Right channel power supply. Normally 5 V. 56 DOUT O Digital output 57 SBSY O Subcode block synchronization signal 58 EFLG O C1, C2, single and double error correction monitor pin 59 PW O Subcode P, Q, R, S, T, U, V and W output 60 SFSY O Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state. 61 SBCK I Subcode readout clock input. This is a Schmitt input. (Must be tied low when unused.) 62 FSX O Output for the 7.35 kHz synchronization signal divided from the crystal oscillator 63 WRQ O Subcode Q output standby output 64 RWC I Read/write control input. This is a Schmitt input. 65 SQOUT O Subcode Q output 66 COIN I Command input from the control microprocessor 67 CQCK I Input for both the command input acquisition clock and the SQOUT pin subcode readout clock input. This is a Schmitt input. 68 RES I Chip reset input. This pin must be set low briefly after power is first applied. 69 TST11 O Test output. Leave open. (Normally outputs a low level.) 70 LASER O Laser on/off output. Controlled by serial data commands from the control microprocessor. 71 16M O 16.9344 MHz output. However, in 4× playback mode only, outputs 33.8688 MHz. 72 4.2M O 4.2336 MHz output 73 CONT O Supplementary control output. Controlled by serial data commands from the control microprocessor. 74 TEST5 I Test input. A pull-down resistor is built in. 75 CS I Chip select input. A pull-down resistor is built in. 76 XVSS 77 XIN I 78 XOUT O 79 XVDD 80 TEST1 Crystal oscillator ground. Normally 0 V. Connections for a 16.9344 MHz crystal oscillator. Use a 33.8688 MHz crystal oscillator in systems that support quad-speed playback. Crystal oscillator power supply. Normally 5 V. I Test input. A pull-down resistor is built in. No. 5130-8/34 LC78620E CD System Block Diagrams Pin Applications 1. HF Signal Input Circuit; Pin 11: EFMIN, pin 10: EFMO, pin 9: EFMO, pin 1: DEFI, pin 13: CLV+ An EFM signal (NRZ) sliced at an optimal level can be acquired by inputting the HF signal to EFMIN. The LC78620E handles defects as follows. When a high level is input to the DEFI pin (pin 1), the EFMO (pin 9) and EFMO (pin 10) pins (the slice level control outputs) go to the highimpedance state, and the slice level is held. However, note that this function is only valid in CLV phase control mode, that is, when the V/P pin (pin 15) is low. This function can be used in combination with the LA9230M and LA9231M DEF pins. Note: If the EFMIN and CLV+ signal lines are too close to each other, unwanted radiation can result in error rate degradation. We recommend laying a ground or VDD shield line between these two lines. 2. PLL Clock Generation Circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK Since the LC78620E includes a VCO circuit, a PLL circuit can be formed by connecting an external RC circuit. ISET is the charge pump reference current, PDO is the VCO circuit loop filter, and FR is a resistor that determines the VCO frequency range. (Reference values) R1 = 68 kΩ, C1 = 0.1 µF R2 = 680 kΩ, C2 = 0.1 µF R3 = 5.1 kΩ Note: We recommend using a ±1.0% tolerance (rank F) carbon firm resistor for R3. 3. VCO Monitor; Pin 21: PCK PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is divided from the VCO frequency. 4. Synchronization Detection Monitor; Pin 22: FSEQ Pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is thus a synchronization detection monitor. (It is held high for a single frame.) No. 5130-9/34 LC78620E 5. Servo Command Function; Pin 64: RWC, pin 66: COIN, pin 67: CQCK Commands can be executed by setting RWC high and inputting commands to the COIN pin in synchronization with the CQCK clock. Note that commands are executed on the falling edge of RWC. Focus start Track jump Muting control Disk motor control Miscellaneous control One-byte commands Track check Two-byte command (RWC set twice) Digital attenuator Two-byte command (RWC set once) • One-byte commands • Two-byte commands (RWC set twice) • Two-byte commands (RWC set once) No. 5130-10/34 LC78620E • Command noise rejection MSB LSB Command 1 1 1 0 1 1 1 1 COMMAND INPUT NOISE REDUCTION MODE 1 1 1 0 1 1 1 0 RESET NOISE EXCLUSION MODE RES = low ● This command reduces the noise on the CQCK clock signal. While this is effective for noise pulses shorter than 500 ns, the CQCK timings TWøL, TWøH, and tsetup (see pages 4 and 5, figures 1 and 2), must be set for at least 1 µs. 6. Focus Servo Circuit; Pin 16: FOCS, pin 17: FST, pin 18: FZD, pin 70: LASER MSB LSB Command 0 0 0 0 1 0 0 0 FOCUS START #1 1 0 1 0 0 0 1 0 FOCUS START #2 0 0 0 0 1 0 1 0 LASER ON 1 0 0 0 1 0 1 0 LASER OFF 1 1 1 1 1 1 1 0 NOTHING RES = low ● The FOCS, FST, and FZD pins are not required when the LC78620E is used in combination with the LA9230M or the LA9231M. FZD should be tied low when these pins are not used. The LA9230M and LA9231M focus start command is identical to the LC78620E FOCUS START #1 command. • NOTHING This command can be used to initialize the LC78620E by inputting FE (hexadecimal). Note that 00 (hexadecimal) is the reset command for the LA9230M and the LA9231M, and should be used with care since it clears the result of the automatic adjustment process and returns these chips to their initial states. • Laser control The LASER pin can be use as an extended output port. • Focus start When the LC78620E is used in combination with the LA9230M or the LA9231M, the focus start operation is executed completely on the servo side by commands from the control microprocessor. The following section describes this operation when the LC78620E is used in combination with the LA9230M or the LA9231M. When a focus start instruction (either FOCUS START #1 or FOCUS START #2) is input as a servo command, first the charge on capacitor C1 is discharged by FST and the objective lens is lowered. Next, the capacitor is charged by FOCS, and the lens is slowly raised. FZD falls when the lens reaches the focus point. When this signal is received, FOCS is reset and the focus servo turns on. After sending the command, the microprocessor should check the in-focus detection signal (the LA9210 DRF signal) to confirm focus before proceeding to the next part of the program. If focus is not achieved by the time C1 is fully charged, the microprocessor should issue another focus command and iterate the focus servo operation. No. 5130-11/34 LC78620E Values in parentheses are for the LASER START #2 command. The only difference is in the FST low period. Note: 1. An FZD falling edge will not be accepted during the period that FST is low. 2. After issuing a focus start command, initialization will be performed if RWC is set high. Therefore, do not issue the next command during focus start until the focus coil drive S curve has completed. 3. When focus cannot be achieved (i.e., when FZD does not go low) the FOCS signal will remain in the high state and the lens will remain raised, so the microprocessor should initialize the system by issuing a NOTHING command. 4. When the RESET pin is set low, the LASER pin is set high directly. 5. Focus start using the DEMO pin executes a mode #1 focus start. 7. CLV servo circuit; Pin 13: CLV+, pin 14: CLV–, pin 15: V/P MSB LSB Command 0 0 0 0 0 1 0 0 DISC MOTOR START (accelerate) 0 0 0 0 0 1 0 1 DISC MOTOR CLV (CLV) 0 0 0 0 0 1 1 0 DISC MOTOR BRAKE (decelerate) 0 0 0 0 0 1 1 1 DISC MOTOR STOP (stop) RES = low ● The CLV+ pin provides the signal that accelerates the disk in the forward direction and the CLV– pin provides the signal that decelerates the disk. Commands from the control microprocessor select one of four modes; accelerate, decelerate, CLV and stop. The table below lists the CLV+ and CLV– outputs in each of these modes. Mode CLV+ CLV– Accelerate High Low Decelerate Low High CLV * * Stop Low Low No. 5130-12/34 LC78620E Note: CLV servo control commands can set the TOFF pin low only in CLV mode. That pin will be at the high level at all other times. Control of the TOFF pin by microprocessor command is only valid in CLV mode. • CLV mode In CLV mode the LC78620E detects the disk speed from the HF signal and provides proper linear speed using several different control schemes by switching the DSP internal modes. The PWM reference period corresponds to a frequency of 7.35 kHz. The V/P pin outputs a high level during rough servo and a low level during phase control. Internal mode Rough servo (velocity too low) Rough servo (velocity too high) Phase control (PCK locked) CLV+ CLV– V/P High Low High Low High High PWM PWM Low • Rough servo gain switching MSB LSB Command 1 0 1 0 1 0 0 0 DISC 8 SET 1 0 1 0 1 0 0 1 DISC 12 SET RES = low ● For 8 cm disks, the rough servo mode CLV control gain can be set about 8.5 dB lower than the gain used for 12 cm disks. • Phase control gain switching MSB LSB Command 1 0 1 1 0 0 0 1 CLV PHASE COMPARATOR DIVISOR: 1/2 1 0 1 1 0 0 1 0 CLV PHASE COMPARATOR DIVISOR: 1/4 1 0 1 1 0 0 1 1 CLV PHASE COMPARATOR DIVISOR: 1/8 1 0 1 1 0 0 0 0 NO CLV PHASE COMPARATOR DIVISOR USED RES = low ● The phase control gain can be changed by changing the divisor used by the dividers in the stage immediately preceding the phase comparator. No. 5130-13/34 LC78620E • CLV three value output MSB LSB Command 1 0 1 1 0 1 0 0 CLV THREE VALUE OUTPUT 1 0 1 1 0 1 0 1 CLV TWO VALUE OUTPUT (the scheme used by previous products) RES = low ● The CLV three-value output command allows the CLV to be controlled by a single pin. • Internal brake modes MSB LSB 1 1 0 0 0 1 0 1 Command RES = low INTERNAL BRAKE ON 1 1 0 0 0 1 0 0 INTERNAL BRAKE OFF 1 0 1 0 0 0 1 1 INTERNAL BRAKE CONT 1 1 0 0 1 0 1 1 INTERNAL BRAKE CONTINUOUS MODE 1 1 0 0 1 0 1 0 RESET CONTINUOUS MODE 1 1 0 0 1 1 0 1 TON MODE DURING INTERNAL BRAKING 1 1 0 0 1 1 0 0 RESET TON MODE ● ● ● — Issuing the internal brake-on (C5H) command sets the LC78620E to internal brake mode. In this mode, the disk deceleration state can be monitored from the WRQ pin when a brake command (06H) is executed. — In this mode the disk deceleration state is determined by counting the EFM signal density in a single frame, and when the EFM signal count falls under four, the CLV– pin is dropped to low. At the same time the WRQ signal, which functions as a brake completion monitor, goes high. When the microprocessor detects a high level on the WRQ signal, it should issue a STOP command to fully stop the disk. In internal brake continuous mode, the CLV– pin high-level output braking operation continues even after the WRQ brake completion monitor goes high. Note that if errors occur in deceleration state determination due to noise in the EFM signal, the problem can be rectified by changing the EFM signal count from four to eight with the internal brake control command (A3H). — In internal braking TON mode, the TOFF pin is held low during internal brake operations. We recommend using this feature, since it is effective at preventing incorrect detection at the disk mirror surface. No. 5130-14/34 LC78620E Note: 1. If focus is lost during the execution of an internal brake command, the pickup must first be refocussed and then the internal brake command must be reissued. 2. Since incorrect deceleration state determination is possible depending on the EFM signal playback state (e.g., disk defects, access in progress), we recommend using these functions in combination with a microprocessor. 8. Track Jump Circuit; Pin 19: HFL, pin 20: TES, pin 23: TOFF, pin 24: TGL, pin 25: THLD, pin 28: JP+, pin 29: JP– • The LC78620E supports the two track count modes listed below. MSB Command RES = low 0 0 1 0 0 0 1 0 LSB NEW TRACK COUNT (using the TES/HFL combination) ● 0 0 1 0 0 0 1 1 EARLIER TRACK COUNT (directly counts the TES signal) The earlier track count function uses the TES signal directly as the internal track counter clock. To reduce counting errors resulting from noise on the rising and falling edges of the TES signal, the new track count function prevents noise induced errors by using the combination of the TES and HFL signals, and implements a more reliable track count function. However, dirt and scratches on the disk can result in HFL signal dropouts that may result in missing track count pulses. Thus care is required when using this function. No. 5130-15/34 LC78620E • TJ commands MSB LSB Command 1 0 1 0 0 0 0 0 OLD TRACK JUMP 1 0 1 0 0 0 0 1 NEW TRACK JUMP 0 0 0 1 0 0 0 1 1 TRACK JUMP IN #1 0 0 0 1 0 0 1 0 1 TRACK JUMP IN #2 0 0 1 1 0 0 0 1 1 TRACK JUMP IN #3 0 1 0 1 0 0 1 0 1 TRACK JUMP IN #4 0 0 0 1 0 0 0 0 2 TRACK JUMP IN 0 0 0 1 0 0 1 1 4 TRACK JUMP IN 0 0 0 1 0 1 0 0 16 TRACK JUMP IN 0 0 1 1 0 0 0 0 32 TRACK JUMP IN 0 0 0 1 0 1 0 1 64 TRACK JUMP IN 0 0 0 1 0 1 1 1 128 TRACK JUMP IN 0 0 0 1 1 0 0 1 1 TRACK JUMP OUT #1 0 0 0 1 1 0 1 0 1 TRACK JUMP OUT #2 0 0 1 1 1 0 0 1 1 TRACK JUMP OUT #3 0 1 0 1 1 0 1 0 1 TRACK JUMP OUT #4 0 0 0 1 1 0 0 0 2 TRACK JUMP OUT 0 0 0 1 1 0 1 1 4 TRACK JUMP OUT 0 0 0 1 1 1 0 0 16 TRACK JUMP OUT 0 0 1 1 1 0 0 0 32 TRACK JUMP OUT 0 0 0 1 1 1 0 1 64 TRACK JUMP OUT 0 0 0 1 1 1 1 1 128 TRACK JUMP OUT 0 0 0 1 0 1 1 0 256 TRACK CHECK 0 0 0 0 1 1 1 1 TOFF 1 0 0 0 1 1 1 1 TON 1 0 0 0 1 1 0 0 TRACK JUMP BRAKE 0 0 1 0 0 0 0 1 THLD PERIOD TOFF OUTPUT MODE 0 0 1 0 0 0 0 0 RESET THLD PERIOD TOFF OUTPUT MODE RES = low ● ● ● When the LC78620E receives a track jump instruction as a servo command, it first generates accelerating pulses (period a) and next generates deceleration pulses (period b). The passage of the braking period (period c) completes the specified jump. During the braking period, the LC78620E detects the beam slip direction from the TES and HFL inputs. TOFF is used to cut the components in the TE signal that aggravate slip. The jump destination track is captured by increasing the servo gain with TGL. In THLD period TOFF output mode the TOFF signal is held high during the period when THLD is high. Note: Of the modes related to disk motor control, the TOFF pin only goes low in CLV mode, and will be high during start, stop, and brake operations. Note that the TOFF pin can be turned on and off independently by microprocessor issued commands. However, this function is only valid when disk motor control is in CLV mode. No. 5130-16/34 LC78620E • Track jump modes The table lists the relationships between acceleration pulses, deceleration pulses, and the braking period. Standard track jump mode Command a b New track jump mode c a b c 1 TRACK JUMP IN (OUT) #1 233 µs 233 µs 60 ms 233 µs 233 µs 60 ms 1 TRACK JUMP IN (OUT) #2 0.5 track jump period 233 µs 60 ms 0.5 track jump period 0.5 track jump period 60 ms 1 TRACK JUMP IN (OUT) #3 0.5 track jump period 233 µs This period does not exist. 0.5 track jump period 0.5 track jump period This period does not exist. 1 TRACK JUMP IN (OUT) #4 0.5 track jump period 233 µs 60 ms; TOFF is low during the C period. 0.5 track jump period 0.5 track jump period 60 ms; TOFF is low during the C period. 2 TRACK JUMP IN (OUT) None None None 1 track jump period 1 track jump period This period does not exist. 4 TRACK JUMP IN (OUT) 2 track jump period 466 µs 60 ms 2 track jump period 2 track jump period 60 ms 16 TRACK JUMP IN (OUT) 9 track jump period 7 track jump period 60 ms 9 track jump period 9 track jump period 60 ms 32 TRACK JUMP IN (OUT) 18 track jump period 14 track jump period 60 ms 18 track jump period 14 track jump period 60 ms 64 TRACK JUMP IN (OUT) 36 track jump period 28 track jump period 60 ms 36 track jump period 28 track jump period 60 ms 128 TRACK JUMP IN (OUT) 72 track jump period 56 track jump period 60 ms 72 track jump period 56 track jump period 60 ms 256 TRACK CHECK TOFF goes high during the period when 256 tracks are passed over. The a and b pulses are not output. 60 ms TOFF goes high during the period when 256 tracks are passed over. The a and b pulses are not output. 60 ms TRACK JUMP BRAKE There are no a or b periods. 60ms There are no a and b periods. 60 ms Note: 1. As indicated in the table, actuator signals are not output during the 256 TRACK CHECK function. This is a mode in which the TES signal is counted in the tracking loop off state. Therefore, feed motor forwarding is required. 2. The servo command register is automatically reset after one cycle of the track jump sequence (a, b, c) completes. 3. If another track jump command is issued during a track jump operation, the content of that new command will be executed starting immediately. 4. The 1 TRACK JUMP #3 and 2 TRACK JUMP modes do not have a braking period (the C period). Since brake mode must be generated by an external circuit, care is required when using this mode. When the LC78620E is used in combination with the LA9230M or the LA9231M, since the THLD signal is generated by the LA9230M or the LA9231M, the THLD pin (pin 25) will be unused, i.e., have no connection. 5. Tracking brake The chart shows the relationships between the TES, HFL, and TOFF signals during the track jump C period. The TOFF signal is extracted from the HFL signal by TES signal edges. When the HFL signal is high, the pickup is over the mirror surface, and when low, the pickup is over data bits. Thus braking is applied based on the TOFF signal being high when the pickup is moving from a mirror region to a data region and being low when the pickup is moving from a data region to a mirror region. No. 5130-17/34 LC78620E • JP three-value output MSB LSB Command 1 0 1 1 0 1 1 0 JP THREE VALUE OUTPUT 1 0 1 1 0 1 1 1 JP TWO VALUE OUTPUT (earlier scheme) RES = low ● The JP three-value output command allows the track jump operation to be controlled from a single pin. • Track check mode MSB LSB Command 1 1 1 1 0 0 0 0 TRACK CHECK IN 1 1 1 1 1 0 0 0 TRACK CHECK OUT 1 1 1 1 1 1 1 1 TWO BYTE COMMAND RESET RES = low ● The LC78620E will count the specified number of tracks minus one when the microprocessor sends an arbitrary binary value in the range 8 to 254 after issuing either a track check in or a track check out command. Note: 1. When the desired track count has been input in binary, the track check operation is started by the fall of RWC. 2. During a track check operation the TOFF pin goes high and the tracking loop is turned off. Therefore, feed motor forwarding is required. 3. When a track check in/out command is issued the function of the WRQ signal switches from the normal mode subcode Q standby monitor function to the track check monitor function. This signal goes high when the track check is half completed, and goes low when the check finishes. The control microprocessor should monitor this signal for a low level to determine when the track check completes. 4. If a two-byte reset command is not issued, the track check operation will repeat. That is, to skip over 20,000 tracks, issue a track check 201 command once, and then count the WRQ signal 100 times. This will check 20,000 tracks. 5. After performing a track check operation, use the brake command to have the pickup lock onto the track. No. 5130-18/34 LC78620E 9. Error Flag Output; Pin 58: EFLG, pin 62: FSX The FSX signal is generated by dividing the crystal oscillator clock, and is a 7.35 kHz frame synchronization signal. The error correction state for each frame is output from EFLG. The playback OK/NG state can be easily determined from the extent of the high level that appears here. 10. Subcode P, Q and R to W Output Circuit; Pin 59: PW, pin 57: SBSY, pin 60: SFSY, pin 61: SBCK PW is the subcode signal output pin, and all the codes, P, Q, and R to W can be read out by sending eight clocks to the SBCK pin within 136 µs after the fall of SFSY. The signal that appears on the PW pin changes on the falling edge of SBCK. If a clock is not applied to SBCK, the P code will be output from PW. SFSY is a signal that is output for each subcode frame cycle, and the falling edge of this signal indicates standby for the output of the subcode symbol (P to W). Subcode data P is output on the fall of this signal. SBSY is a signal output for each subcode block. This signal goes high for the S0 and S1 synchronization signals. The fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode block. (EIAJ format) No. 5130-19/34 LC78620E 11. Subcode Q Output Circuit; Pin 63: WRQ, pin 64: RWC, pin 65: SQOUT, pin 67: CQCK, pin 75: CS MSB LSB Command 0 0 0 0 1 0 0 1 ADDRESS FREE 1 0 0 0 1 0 0 1 ADDRESS 1 RES = low ● Subcode Q can be read from the SQOUT pin by applying a clock to the CQCK pin. Of the eight bits in the subcode, the Q signal is used for song (track) access and display. The WRQ will be high only if the data passed the CRC error check and the subcode Q format internal address is 1*. The control microprocessor can read out data from SQOUT in the order shown below by detecting this high level and applying CQCK. When CQCK is applied the DSP disables register update internally. The microprocessor should give update permission by setting RWC high briefly after reading has completed. WRQ will fall to low at this time. Since WRQ falls to low 11.2 ms after going high, CQCK must be applied during the high period. Note that data is read out in an LSB first format. Note: * That state will be ignored if an address free command is sent. This is provided to handle CD-ROM applications. Note: 1. Normally, the WRQ pin indicates the subcode Q standby state. However, it is used for a different monitoring purpose in track check mode and during internal braking. (See the items on track counting and internal braking for details.) 2. The LC78620E becomes active when the CS pin is low, and subcode Q data is output from the SQOUT pin. When the CS pin is high, the SQOUT pin goes to the high-impedance state. No. 5130-20/34 LC78620E 12. Level Meter (LVM) Data and Peak Meter (PKM) data readout MSB LSB 0 0 1 0 1 0 1 1 Command RES = low PKM SET (LVM reset) 0 0 1 0 1 1 0 0 LVM SET (PKM reset) 0 0 1 0 1 1 0 1 PKM MASK SET 0 0 1 0 1 1 1 0 PKM MASK RESET ● ● • Level meter (LVM) — The LVM set (2CH) command sets the LC78620E to LVM mode. — LVM data is a 16-bit word in which the MSB indicates the L/R polarity and the low-order 15 bits are absolute value data. A one in the MSB indicates left channel data and a zero indicates right channel data. — LVM data is appended after the 80 bits of SubQ data, and can be read out by applying 96 clock cycles to the CQCK pin. Each time LVM data is read out the left/right channel state is inverted. Data is held independently for both the left and right channels. In particular, the largest value that occurs between readouts for each channel is held. • Peak meter (PKM) — The PKM set (2BH) command sets the LC78620E to PKM mode. — PKM data is a 16-bit word in which the MSB is always zero and the low-order 15 bits are absolute value data. This functions detects the maximum value that occurs in the data, whichever channel that value occurs in. — PKM data is read out in the same manner as LVM data. However, data is not updated as a result of the readout operation. — The absolute time for PKM mode SubQ data is computed by holding the absolute time (ATIME) detected after the maximum value occurred and sending that value. (Normal operation uses relative time.) — It is possible to set the LC78620E to ignore values larger than the already recorded value by issuing the PKM mask set command, even in PKM mode. This function is cleared by issuing a PKM mask reset command. (This is used in PK search in a memory track.) 13. Mute Control Circuit MSB LSB Command 0 0 0 0 0 0 0 1 MUTE: 0 dB 0 0 0 0 0 0 1 0 MUTE: –12 dB 0 0 0 0 0 0 1 1 MUTE: –∞ dB RES = low ● An attenuation of 12 dB (MUTE –12 dB) or full muting (MUTE ∞ dB) can be applied by issuing the appropriate command from the table. Since zero-cross muting is used, there is minimal noise associated with this function. Zero cross is defined for this function as the top seven bits being all ones or all zeros. No. 5130-21/34 LC78620E 14. Interpolation Circuit Outputting incorrect audio data that could not be corrected by the error detection and correction circuit would result in loud noises being output. To minimize this noise, the LC78620E replaces the incorrect data with linearly interpolated data based on the correct data on either side of the incorrect data. More precisely, the LC78620E uses this technique if C2 flags occurred up to three times in a row. If C2 flags occurred four or more times in a row, the LC78620E converges the output level to the muting level. However, when correct data is finally output following four or more C2 flag occurrences, the LC78620E replaces the 3 data items between the data output three items previously and the correct data with data linearly interpolated data. 15. Bilingual Function MSB Command RES = low 0 0 1 0 1 0 0 0 LSB STO CONT ● 0 0 1 0 1 0 0 1 Lch CONT 0 0 1 0 1 0 1 0 Rch CONT • Following a reset or when a stereo (28H) command has been issued, the left and right channel data is output to the left and right channels respectively. • When an Lch set (29H) command is issued, the left and right channels both output the left channel data. • When an Rch set (2AH) command is issued, the left and right channels both output the right channel data. 16. De-Emphasis; Pin 32: EMPH The preemphasis on/off bit in the subcode Q control information is output from the EMPH pin. When this pin is high, the LC78620E internal de-emphasis circuit operates and the digital filters and the D/A converter output deemphasized data. 17. Digital Attenuator Digital attenuation can be applied to the audio data by setting the RWC pin high and inputting the corresponding two-byte command to the COIN pin in synchronization with the CQCK clock. MSB LSB Command 1 0 0 0 0 0 0 1 ATT DATA SET 1 0 0 0 0 0 1 0 ATT 4 STEP UP 1 0 0 0 0 0 1 1 ATT 4 STEP DOWN 1 0 0 0 0 1 0 0 ATT 8 STEP UP 1 0 0 0 0 1 0 1 ATT 8 STEP DOWN 1 0 0 0 0 1 1 0 ATT 16 STEP UP 1 0 0 0 0 1 1 1 ATT 16 STEP DOWN RES = low DATA 00H set (MUTE –∞ dB) No. 5130-22/34 LC78620E • Attenuation setup Since the attenuation level is set to the muted state (a muting of –∞ is specified by an attenuation coefficient of 00H) after the attenuation level is reset, the attenuation coefficient must be directly set to EEH (using the ATT DATA SET command) to output audio signals. Note that the attenuation level can be set to one of 239 values from 00H to EEH. These two-byte commands differ from the two-byte commands used for track counting in that it is only necessary to set RWC once and a two-byte command reset is not required. (See the item on two-byte commands (RWC set once) on page 10.) After inputting the target attenuation level as a value in the range 00H to EEH, sending an attenuator step up/down command will cause the attenuation level to approach the target value in steps of 4, 8, or 16 units as specified in synchronization with rising edges on the LRSY input. However, the ATT DATA SET command sets the target value directly. If a new data value is input during the transition, the value begins to approach the new target value at that point. Note that the UP/DOWN distinction is significant here. Audio output level = 20 log ATT DATA [dB] 100H For example, the formula below calculates the time required for the attenuation level to increase from 00H to EEH when a 4STEP UP command is executed. Note that the control microprocessor must provide enough of a time margin for this operation to complete before issuing the next attenuation level set command. 238 level × 4STEP UP ≈ 21.6 ms 44.1 kHz (LRSY) Note: Setting the attenuation level to values of EFH or higher is disallowed to prevent overflows in one-bit D/A converter calculations from causing noise. • Mute output; Pin 46: MUTEL, pin 55: MUTER These pins output a high level when the attenuator coefficient is set to 00H and the data in each channel has been zero for a certain period. If data input occurs once again, these pins go low immediately. No. 5130-23/34 LC78620E 18. Digital Filter Outputs; Pin 33: LRCKO, pin 34: DFORO, pin 35: DFOLO, pin 36: DACKO Data for use with an external D/A converter is output MSB first from DFORO and DFOLO in synchronization with the falling edge of DACKO. These pins are provided so that an external D/A converter can be used if desired. • Although this output is from 8× oversampling filters for normal-speed playback, 4× oversampling filters are used in double-speed playback. • Digital filter block operation is not guaranteed in quad-speed playback. 19. One-bit D/A Converter • The LC78620E PWM block outputs a single data value in the range –3 to +3 once every 64fs period. To reduce carrier noise, this block adopts an output format in which each data switching block is adjusted so that the PWM output level does not invert. Also, the attenuator block detects 0 data and enters muting mode so that only a 0 value (a 50% duty signal) is output. This block outputs a positive-phase signal to the LCHP (RCHP) pin and a negative phase signal to the LCHN (RCHN) pin. High-quality analog signals can be acquired by taking the differences of these two output pairs using external low-pass filters. The LC78620E includes built-in suppression resistors in each of the LCHP/N and RCHP/N pins. • PWM output format • PWM output example No. 5130-24/34 LC78620E 20. CD-ROM Outputs; Pin 42: LRSY, pin 43: CK2, pin 44: ROMXA, pin 45: C2F Although the LC78620E is initially set up to output audio data from the interpolation circuit MSB first from the ROMXA pin in synchronization with the LRSY signal, the circuit can be switched to output CD-ROM data by issuing a CD-ROM XA command. Since this data has not been processed by the interpolation, muting, and other digital circuits, it is appropriate for input to a CD-ROM encoder LSI. CK2 is a 2.1168 MHz clock, and data is output on the CK2 falling edge. However, this clock polarity can be inverted by issuing a CK2 polarity inversion command. C2F is the flag information for the data in 8-bit units. Note that the CD-ROM XA reset command has the same function as the CONT pin (pin 73). MSB LSB 1 0 0 0 1 0 0 0 Command RES = low CD-ROM XA 1 0 0 0 1 0 1 1 CONT AND CD-ROM XA RESET 1 1 0 0 1 0 0 1 CK2 POLARITY INVERSION ● LC78620E CD-ROM encoder LSI (LC895XX) interface 21. Digital Output Circuit; Pin 56: DOUT This is an output pin for use with a digital audio interface. Data is output in the EIAJ format. This signal has been processed by the interpolation and muting circuits. This pin has a built-in driver circuit and can directly drive a transformer. MSB Command RES = low 0 1 0 0 0 0 1 0 LSB DOUT ON ● 0 1 0 0 0 0 1 1 DOUT OFF 0 1 0 0 0 0 0 0 UBIT ON 0 1 0 0 0 0 0 1 UBIT OFF ● • The DOUT pin can be locked at the low level by issuing a DOUT OFF command. • The UBIT information in the DOUT data can be locked at zero by issuing a UBIT OFF command. • The DOUT data can be switched to data for which interpolation and muting processing have not been performed by issuing a CD-ROM XA command. 22. Antishock Mode; Pin 38: ASDACK, pin 39: ASDFIN, pin 40: ASDFIR, pin 41: ASLRCK, pin 42: LRSY, pin 43: CK2, pin 44: ROMXA, pin 45: C2F • Antishock mode is a mode in which antishock processing is applied to data that has been output once. That data is returned and output once again as an audio playback signal. It is also possible to use only the audio playback block (the attenuator, 8× oversampling digital filter, and one-bit D/A converter circuits) and thus share the audio playback block with other systems by synchronizing the other system with this LSI’s clock. Note that de-emphasis on/off switching is controlled by the LC78620E subcode Q playback state. No. 5130-25/34 LC78620E • The ASDACK (pin 38), ASDFIN (pin 39), ASDFIR (pin 40), and ASLRCK (pin 41) pins must be held low if this mode is not used. MSB LSB 0 1 1 0 1 1 0 0 Command RES = low ANTIC ON ● 0 1 1 0 1 0 1 1 ANTIC OFF 0 1 1 0 1 1 1 1 DF NORMAL SPEED ON (only in antishock mode) 0 1 1 0 1 1 1 0 DF NORMAL SPEED OFF (only in antishock mode) ● • It is possible to input the signals from the ROMXA (pin 44), C2F (pin 45), LRSY (pin 42), and CK2 (pin 43) pins to an antishock LSI (the Sanyo LC89151) and re-input the signals output by the antishock LSI to the ASDFIN (pin 39), ASLRCK (pin 41), and ASDACK (pin 38) pins. These signals are then processed by the attenuator, 8× oversampling digital filter, and one-bit D/A converter circuits and output as audio signals. • In antishock systems, the signal-processing block must operate in double-speed playback mode for data output to the antishock LSI, and the audio playback block (the attenuator, 8× oversampling digital filter, and one-bit D/A converter circuits) must operate at normal speed. This means that the control microprocessor must issue both the ANTIC on command (6CH) as well as the DF normal speed on command (6FH). • The ANTIC off command (6BH) clears anti-shock mode. 23. CONT Pin; Pin 73: CONT MSB LSB Command 0 0 0 0 1 1 1 0 CONT SET 1 0 0 0 1 0 1 1 CONT AND CD-ROM XA RESET RES = low Low ● The CONT pin goes high when a CONT SET command is issued. 24. Clock Oscillator; Pin 77: XIN, pin 78: XOUT MSB LSB Command 1 0 0 0 1 1 1 0 OSC ON 1 0 0 0 1 1 0 1 OSC OFF 1 1 0 0 1 1 1 0 XTAL 16M 1 1 0 0 1 1 1 1 XTAL 32M 1 1 0 0 0 0 1 0 NORMAL-SPEED PLAYBACK 1 1 0 0 0 0 0 1 DOUBLE-SPEED PLAYBACK 1 1 0 0 1 0 0 0 QUAD-SPEED PLAYBACK RES = low ● ● ● No. 5130-26/34 LC78620E The clock that is used as the time base is generated by connecting a 16.9344 or 33.8688 MHz oscillator element between these pins. The OSC OFF command turns off both the VCO and crystal oscillators. Double- or quad-speed playback can be specified by microprocessor command. • Connect a 16.9344 MHz oscillator element between the XIN (pin 77) and XOUT (pin 78) pins for double-speed systems. The playback speed can be set by the normal-speed playback and double-speed playback commands. • Connect a 33.8688 MHz oscillator element between the X IN (pin 77) and XOUT (pin 78) pins for quad-speed systems. An XTAL32M command must be issued to intialize such systems. Then the playback speed can be set by the double-speed playback and quad-speed playback commands. • Recommended crystal and ceramic oscillator elements Manufacturer Product No. Load capacitance C1/C2 (C1 = C2) Damping resistor Rd Citizen Watch Co., Ltd. (crystal oscillator elements) CSA-309 (16.9344 MHz) 6 pF to 10 pF (±10%) 0Ω CSA-309 (33.8688 MHz) 16 pF (±10%) 0Ω TDK, Ltd. (ceramic oscillator elements) FCR 16.93M2G (16.93 MHz) 15 pF (±10%) 100 Ω (±10%) FCR 16.93MCG (16.93 MHz) 30 pF (Includes built-in capacitors) 47 Ω (±10%) Since the conditions for the load capacitors Cin and Cout used varies with the printed circuit board, this circuit must be tested on the printed circuit board actually used. 25. 16M and 4.2M Pins; Pin 71: 16M, pin 72: 4.2M In normal- and double-speed playback modes, the 16M pin buffer outputs the 16.9344 MHz external crystal oscillator 16.9344 MHz signal. In quad-speed mode, it outputs the 33.8688 MHz external crystal oscillator 33.8688 MHz signal. The 4.2M pin supplies the LA9231M or LA9231M system clock, normally outputting a 4.2336 MHz signal. When the oscillator is turned off both these pins will be fixed at either high or low. No. 5130-27/34 LC78620E 26. Reset Circuit; Pin 68: RES When power is first applied, this pin should be briefly set low and then set high. This will set the muting to –∞ dB and stop the disk motor. Constant linear velocity servo START STOP BRAKE 0 dB –12 db –∞ Q subcode address conditions Address 1 Address free Laser control ON (low) OFF (high) High Low Track jump mode Standard New Track count mode Standard New Digital attenuator DATA 0 Muting control CONT CLV DATA 00H to EEH OSC ON OFF XTAL 16M 32M Playback speed Normal speed Double speed Antishock mode ON OFF Digital filter normal speed ON OFF Quad speed Setting the RES pin low sets the LC78620E to the settings enclosed in boxes in the table. 27. Adjustment Process Sound Output Function; Pin 30: DEMO No. 5130-28/34 LC78620E The DEMO pin can be used when the LC78620E is used in combination with an LA9210M or LA9211M. By setting this pin high, muting can be set to 0 dB, the disk motor can be set to CLV, and a focus start operation can be performed, even without issuing any commands from the control microprocessor. Also, since the LASER pin becomes active, if the mechanism and servo systems are complete, an EFM signal can be acquired with only this equipment, and an audio signal can be produced without the presence of a microprocessor. However, since the digital attenuation is set to 100H, this technique is not appropriate for evaluating audio quality. 28. Other Pins; Pin 2:TAI, pin 80: TEST1, pin 12: TEST2, pin 26: TEST3, pin 31: TEST4, pin 74: TEST5, pin 40: ASDFIR These pins are used for testing the LSI’s internal circuits. Since the pins TAI and TEST1 to TEST5 have built-in pull-down resistors, they can be left open in normal operation. ASDFIR must be connected to ground in normal operation. 29. Circuit Block Operating Descriptions • RAM address control The LC78620E incorporates an 8-bit × 2k-word RAM on chip. This RAM has an EFM demodulated data jitter handling capacity of ±4 frames implemented using address control. The LC78620E continuously checks the remaining buffer capacity and controls the data write address to fall in the center of the buffer capacity by making fine adjustments to the frequency divisor in the PCK side of the CLV servo circuit. If the ±4 frame buffer capacity is exceeded, the LC78620E forcibly sets the write address to the ±0 position. However, since the errors that occur due to this operation cannot be handled with error flag processing, the IC applies muting to the output for a 128 frame period. Position –4 or less –3 Division ratio or processing Force to ±0 589 –2 589 –1 589 ±0 588 +1 587 +2 587 +3 587 +4 or more Increase ratio Standard ratio Decrease ratio Force to ±0 No. 5130-29/34 LC78620E • C1 and C2 Error Correction The LC78620E writes EFM demodulated data to internal RAM to compensate for jitter and then performs the following processing with uniform timing based on the crystal oscillator clock. First, the LC78620E performs C1 error checking and correction in the C1 block, determines the C1 flags, and writes the C1 flag register. Next, the LC78620E performs C2 error checking and correction in the C2 block, determines the C2 flags, and writes data to internal RAM. C1 flag Error correction and flag processing No errors No correction required · Flag reset 1 error Correction · Flag reset 2 errors Correction · Flag set 3 errors or more Correction not possible · Flag set C2 flag Error correction and flag processing No errors No correction required · Flag reset 1 error Correction · Flag reset 2 errors Depends on C1 flags*1 3 errors or more Depends on C1 flags*2 Note: 1. If the positions of the errors determined by the C2 check agree with those specified by the C1 flags, the correction is performed and the flags are cleared. However, if the number of C1 flags is 7 or higher, C2 correction may fail. In this case correction is not performed and the C1 flags are taken as the C2 flags without change. Error correction is not possible if one error position agrees and the other does not. Furthermore, if the number of C1 flags is 5 or under, the C1 check result can be seen as unreliable. Accordingly, the flags will be set in this case. Cases where the number of C1 flags is 6 or more are handled in the same way, and the C1 flags are taken as the C2 flags without change. When there is not even one agreement between the error positions, error correction is, of course, impossible. Here, if the number of C1 flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. In other cases, the C1 flags are taken as the C2 flags without change. 2. When data is determined to have three or more errors and be uncorrectable, correction is, of course, impossible. Here, if the number of C1 flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. In other cases the C1 flags are taken as the C2 flags without change. No. 5130-30/34 LC78620E 30. Command Summary Table Blank entry: Illegal command, #: Changed or added command, *: latching commands (mode setting commands), ● : Commands shared with an ASP (LA9230M/31M or other processor), Items in parentheses are ASP commands (provided for reference purposes) 00000000 (ADJ.reset) 0 0 1 0 0 0 0 0 * TOFF low in TJ mode 01000000 * UBIT ON 01100000 0 0 0 0 0 0 0 1 * MUTE 0 dB 0 0 1 0 0 0 0 1 * TOFF high in TJ mode 01000001 * UBIT OFF 01100001 0 0 0 0 0 0 1 0 * MUTE –12 dB 0 0 1 0 0 0 1 0 * New TRACK COUNT 01000010 * DOUT ON 01100010 0 0 0 0 0 0 1 1 * MUTE –∞ dB 0 0 1 0 0 0 1 1 * Old TRACK COUNT 01000011 * DOUT OFF 01100011 0 0 0 0 0 1 0 0 * DISC MTR START 0 0 1 0 0 1 0 0 01000100 01100100 0 0 0 0 0 1 0 1 * DISC MTR CLV 00100101 01000101 01100101 0 0 0 0 0 1 1 0 * DISC MTR BRAKE 0 0 1 0 0 1 1 0 01000110 01100110 0 0 0 0 0 1 1 1 * DISC MTR STOP 00100111 01000111 01100111 0 0 0 0 1 0 0 0 ● FOCUS START #1 0 0 1 0 1 0 0 0 * STO CONT 01001000 01101000 0 0 0 0 1 0 0 1 * ADDRESS FREE 0 0 1 0 1 0 0 1 * LCH CONT 01001001 01101001 0 0 0 0 1 0 1 0 * LASER ON 0 0 1 0 1 0 1 0 * RCH CONT 01001010 01101010 00001011 0 0 1 0 1 0 1 1 * PKM SET 01001011 0 1 1 0 1 0 1 1 * #ANTIC off 00001100 0 0 1 0 1 1 0 0 * LVM SET 01001100 0 1 1 0 1 1 0 0 * #ANTIC on 00001101 0 0 1 0 1 1 0 1 * PKM MSK SET 01001101 01101101 0 0 0 0 1 1 1 0 * CONT SET 0 0 1 0 1 1 1 0 * PKM MSK RESET 01001110 0 1 1 0 1 1 1 0 * #DF normal speed off 0 0 0 0 1 1 1 1 * TRACKING OFF 00101111 01001111 0 1 1 0 1 1 1 1 * #DF normal speed 00010000 2TJ IN 00110000 32TJ IN 01010000 01110000 00010001 1TJ IN #1 00110001 1TJ IN #3 01010001 00010010 1TJ IN #2 00110010 01010010 00010011 4TJ IN 00110011 01010011 01110011 00010100 16TJ IN 00110100 01010100 01110100 00010101 64TJ IN 00110101 01010101 01110101 00010110 256TC 00110110 01010110 01110110 00010111 128TJ IN 00110111 01010111 01110111 00011000 2TJ OUT 00111000 32TJ OUT 01011000 01111000 00011001 1TJ OUT #1 00111001 1TJ OUT #3 01011001 00011010 1TJ OUT #2 00111010 01011010 00011011 4TJ OUT 00111011 01011011 01111011 00011100 16TJ OUT 00111100 01011100 01111100 00011101 64TJ OUT 00111101 01011101 01111101 00111110 01011110 01111110 00111111 01011111 01111111 on 00011110 00011111 128TJ OUT 01110001 1TJ IN #4 01110010 01111001 1TJ OUT #4 01111010 Continued on next page. No. 5130-31/34 LC78620E Continued from preceding page. Blank entry: Illegal command, #: Changed or added command, *: latching commands (mode setting commands), ● : Commands shared with an ASP (LA9230M/31M or other processor), Items in parentheses are ASP commands (provided for reference purposes) 1 0 0 0 0 0 0 0 * #ATT 0 dB SET 1 0 1 0 0 0 0 0 * Old TRK JMP 11000000 1 0 0 0 0 0 0 1 * #ATT DATA SET 1 0 1 0 0 0 0 1 * New TRK JMP 11000001 * Double-speed playback 11100001 1 0 0 0 0 0 1 0 * #ATT 4STP UP 10100010 11000010 * Normal-speed playback 11100010 1 0 0 0 0 0 1 1 * #ATT 4STP DWN 1 0 1 0 0 0 1 1 * Internal BRKE CONT 11000011 1 0 0 0 0 1 0 0 * #ATT 8STP UP 10100100 11000100 * Internal BRK OFF 11100100 1 0 0 0 0 1 0 1 * #ATT 8STP DWN 10100101 11000101 * Internal BRK ON 11100101 1 0 0 0 0 1 1 0 * #ATT 16STP UP 10100110 11000110 1 0 0 0 0 1 1 1 * #ATT 16STP DWN 1 0 1 0 0 1 1 1 11000111 1 0 0 0 1 0 0 0 * CDROMXA 1 0 1 0 1 0 0 0 * DISC 8 SET 11001000 * Quad-speed playback 11101000 1 0 0 0 1 0 0 1 * ADDRESS “1” 1 0 1 0 1 0 0 1 * DISC 12 SET 11001001 * #CK2 polarity inverted 11101001 1 0 0 0 1 0 1 0 * LASER OFF 10101010 11001010 * Internal BRK-DMC 1 1 1 0 1 0 1 0 low 1 0 0 0 1 0 1 1 * CONT, ROMXA RST 10101011 11001011 * Internal BRK-DMC 1 1 1 0 1 0 1 1 high 10001100 10101100 11001100 * TOFF during internal BRK 11101100 1 0 0 0 1 1 0 1 * OSC OFF 10101101 11001101 * TON during internal BRK 11101101 1 0 0 0 1 1 1 0 * OSC ON 10101110 11001110 * XTAL16M 1 1 1 0 1 1 1 0 * Command noise OFF 1 0 0 0 1 1 1 1 * TRACKING ON 10101111 11001111 * XTAL32M 1 1 1 0 1 1 1 1 * Command noise ON 1 0 0 1 0 0 0 0 (* F.OFF.ADJ.ST) 1 0 1 1 0 0 0 0 * CLV-PH 1/1 mode 11010000 1 1 1 1 0 0 0 0 * ● TRCK CHECK IN (2BYTEDETECT) 1 0 0 1 0 0 0 1 (* F.OFF.ADJ.OFF) 1 0 1 1 0 0 0 1 * CLV-PH 1/2 mode 11010001 11110001 1 0 0 1 0 0 1 0 (* T.OFF.ADJ.ST) 1 0 1 1 0 0 1 0 * CLV-PH 1/4 mode 11010010 11110010 1 0 0 1 0 0 1 1 (* T.OFF.ADJ.OFF) 1 0 1 1 0 0 1 1 * CLV-PH 1/8 mode 11010011 11110011 1 0 0 1 0 1 0 0 (* LSR.ON) 1 0 1 1 0 1 0 0 * CLV3ST output ON 1 1 0 1 0 1 0 0 11110100 TRACK JMP BRK FOCS START #2 11100000 11100011 11100110 11100111 1 0 0 1 0 1 0 1 (* LSR.OF/F.SV.ON) 1 0 1 1 0 1 0 1 * CLV3ST output OFF 11010101 11110101 1 0 0 1 0 1 1 0 (* LSR.OF/F.SV.OF) 1 0 1 1 0 1 1 0 * JP3ST output ON 11010110 11110110 1 0 0 1 0 1 1 1 (* SP.8CM) 1 0 1 1 0 1 1 1 * JP3ST output OFF 1 1 0 1 0 1 1 1 11110111 1 0 0 1 1 0 0 0 (* SP.12CM) 10111000 11011000 1 1 1 1 1 0 0 0 * ● TRCK CHECK OUT (2BYTE DETECT) 1 0 0 1 1 0 0 1 (* SP.OFF) 10111001 11011001 11111001 1 0 0 1 1 0 1 0 (* SLED.ON) 10111010 11011010 11111010 1 0 0 1 1 0 1 1 (* SLED.OFF) 10111011 11011011 11111011 1 0 0 1 1 1 0 0 (* EF.BAL.START) 10111100 11011100 11111100 1 0 0 1 1 1 0 1 (* T.SERVO.OFF) 10111101 11011101 11111101 1 0 0 1 1 1 1 0 (* T.SERVO.ON) 10111110 11011110 1 1 1 1 1 1 1 0 # ● NOTHING 10011111 10111111 11011111 1 1 1 1 1 1 1 1 * ● 2BYTE CMD RST No. 5130-32/34 LC78620E 31. Sample Application Circuit No. 5130-33/34 LC78620E 32. CD-DSP Functional Comparison Product Function EFM-PLL LC7860KA LC7861NE→ LC7861KE LC7867E When paired with When paired with When paired with an analog ASP an analog ASP an analog ASP 16 KRAM External Playback speed Normal ● Double LC7868E → LC7868KE When paired with an analog ASP ● Quad Double ● Normal LC7869E LC78681E → LC78681KE When paired with When paired with an analog ASP an analog ASP ● Quad Normal ● Double LC78620E Built-in VCO ● Quad Quad Digital output ✕ ● ● ● ● ● ● Interpolation 2 4 4 4 4 4 4 Zero-cross muting ✕ ● ● ● ● ● ● Level meter Peak meter ✕ ✕ ✕ ● ● ● ● Bilingual ✕ ✕ ✕ ● ● ● ● Digital attenuator ✕ ✕ ✕ ✕ ✕ ✕ ● 2fs ● ● — — — — — 4fs — — — ● — — — 8fs — — — — ● — ● Digital de-emphasis ✕ ✕ ✕ ● ● ✕ ● 1 bit DAC ✕ ✕ ✕ ✕ ✕ ✕ ● ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1995. Specifications and information herein are subject to change without notice. PS No. 5130-34/34