Ordering number : EN*5236 CMOS LSI LC78845Q Sample Rate Converter for Digital Audio Preliminary Overview Package Dimensions The LC78845Q is a synchronous sample rate converter for digital audio signals. unit: mm 3156-QFP48E Features [LC78845Q] • Converts data sampled at 32 or 48 kHz to 44.1-kHz sampled data. • Passes 44.1-kHz sampled data trough without change. • Supports 384fs and 512fs system clock rates. • 8× oversampling filters • Soft muting function • Built-in PLL circuit SANYO: QIP48E Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Maximum supply voltage Conditions Ratings VDD max I/O voltages VI, VO Unit –0.3 to +7.0 V –0.3 to VDD + 0.3 V Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C DC Characteristics Parameter Symbol Conditions Input voltage range VIN Input high-level voltage VIH Input low-level voltage VIL Output high-level voltage VOH IOH = –1 µA Output low-level voltage VOL IOL = 1 µA Ta = –30 to +70°C min typ 0 max VDD 0.7 VDD Unit V V 0.3 VDD VDD – 0.05 V V VSS + 0.05 V This LSI can easily use CCB that is SANYO’s original bus format. • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN 22896HA (OT) No. 5236-1/10 LC78845Q AC Characteristics 1. Audio data input Parameter Symbol Conditions min typ max Unit BCLKI pulse width tBKW 50 ns DATAI setup time tDS 20 ns DATAI hold time tDH 20 ns LRCKI hold time tLH 25 ns LRCKI setup time tLS 25 ns 2. Audio data output Parameter Symbol BCLKO pulse width tBWO DATAO output delay time tDAD Conditions min typ max Unit 25 ns 100 ns DATAO setup time tDSO 50 DATAO hold time tDHO 50 LRCKO output delay time tLRD LRCKO setup time tLSO 50 ns LRCKO hold time tLHO 50 ns WCLKO setup time tWSO 50 ns WCLKO hold time tWHO 50 ns ns ns 25 ns No. 5236-2/10 LC78845Q 3. Serial input (CCB = low) Parameter CL pulse width Symbol Conditions min typ max Unit tCLW 50 ns DI setup time tDS 20 ns DI hold time tDH 20 ns CE pulse width tCEW 50 ns CE setup time tCS 20 ns CE hold time tCH 20 DO0 to DO7 output delay time ns tDOD 25 ns max Unit 4. Serial input (CCB = high) Parameter CL pulse width Symbol Conditions min typ tCLW 50 ns DI setup time tDS 20 ns DI hold time tDH 20 ns CE setup time tCS 20 ns CE hold time tCH 20 ns DO0 to DO7 output delay time with respect to the rise of CE tDOD 25 ns No. 5236-3/10 LC78845Q Pin Assignment Although the DVDD and AVDD pins in this IC are given different names to correspond to the internal circuit structure, they are connected internally through the circuit substrate. As a result, if different voltages are applied to these pins, abnormal currents will flow in the chip. Since this can cause latchup, power supplies with identical voltages and identical power-on timings must be used. Pin Functions Pin No. Symbol Overview Function 1 MKSEL DF master clock selection Low: 384fs, high: 512fs 2 INITB Reset input Low: initialization operation 3 MCK1 DF master clock input 4 BCLKI Audio signal input 5 DGND Digital system ground 6 DGND Digital system ground 7 DVDD Digital system power supply 8 LRCKI 9 DATAI 10 CCB 11 SPSEL Audio signal bit clock input pin Audio signal input Audio signal left/right clock and data input pins Serial input format specification Selects the input format for data from the microprocessor input pins. Serial/parallel control Allows certain of the setting pins to be set from serial data over the microprocessor interface. Low: serial, high: parallel (states set by input pins) Continued on next page. No. 5236-4/10 LC78845Q Continued from preceding page. Pin No. Symbol 12 CE 13 CL 14 DI 15 DO7 16 DO6 17 DO5 18 DGND Digital system ground 19 DVDD Digital system power supply 20 DO4 21 DO3 22 DO2 23 DO1 24 DO0 25 DATAO 26 LRCKO 27 WCLKO 28 BCLKO 29 DGND Overview Function Data enable signal input Microprocessor input pins Shift clock input Address/data input Output of 8-bit parallel data according to microprocessor input Parallel data output Parallel data output Output of 8-bit parallel data according to microprocessor input Audio signal output Audio signal outputs (data, left/right clock, word clock, and bit clock) Digital system ground 30 N.C 31 AGND 32 VCO PLL control Low-pass filter connection 33 VIN PLL control Free-running setting 34 R PLL control VCO band adjustment 35 STOP Oscillator stop signal input Low: oscillator stopped, high: PLL running 36 UNLK Unlock detection output Outputs a high level when the PLL circuit is unlocked. 37 MCK2 Synchronization clock output Outputs the clock generated by the VCO. 38 AVDD Analog system power supply 39 AVDD Analog system power supply 40 MUTE Muting Low: muting off, high: muting on 41 FSEL3 Output data fs selection Low: fs data, high: 2fs data 42 TEST1 Test pin Must be held low during normal operation. 43 DVDD Digital system power supply 44 DVDD Digital system power supply 45 FSEL2 46 FSEL1 47 TEST2 48 TEST3 — Analog system ground Input signal fs selection Selects the fs for the input signal. Test pins Must be held low during normal operation. No. 5236-5/10 LC78845Q Block Diagram Note: 1. 2. 3. 4. 5. BCLKI, LRCKI, DATAI BCLKO, LRCKO, DATAO, WCLKO R, VIN, VCO, UNLK MKSEL, FSEL1, FSEL2, MUTE, STOP CCB, SPSEL, CE, CL, DI No. 5236-6/10 LC78845Q Input and Output Formats 1. Input format Audio data is input through the audio data input pins (BCLKI, LRCKI, and DATAI) in the following format. MKSEL = L: fBCK = 48fs MKSEL = H: fBCK = 64fs 2. Output format 1 Audio data is output through the audio data output pins (BCLKO, WCLKO, LRCKO, and DATAO) in the following format. BCLKO = 64fs (fixed) LRCKO = fs (fixed) WCLKO = 2fs (fixed) 3. Output format 2 (When the input fs is 44.1 kHz) When data sampled at 44.1 kHz is input, that data is output directly without change. The WCLKO output is held low in this case. No. 5236-7/10 LC78845Q Pin Settings 1. Input master clock setup (when SPSEL is high) Input the master clock for the internal digital filters to MCK1 (pin 3). Also, set whether that clock is 384fs or 512fs with MKSEL (pin 1). Pin L H MKSEL 384fs 512fs 2. Input data fs setting (when SPSEL is high) The input data sampling frequency must be set. FSEL1 and FSEL2 (pins 46 and 45) are used for this setting. Data sampled at a 32 or 48 kHz sampling frequency is converted to data with a 44.1 kHz sampling frequency. If data sampled at 44.1 kHz is input, it is passed through unchanged. Sampling frequency FSEL1 FSEL2 44.1 kHz 0 ✕ 48 kHz 1 0 32 kHz 1 1 3. Output data setup The output data can be switched between fs and 2fs. FSEL3 (pin 41) is used to change this setting. Pin L H FSEL3 fs 2fs 4. Setup from serial input The MKSEL, FSEL1, FSEL2, MUTE, and STOP settings can be set using the serial bus by setting SPSEL (pin 11) low. The 8 bits of input data is output in parallel regardless of the SPSEL setting. Serial input format 1 (CCB = high) Serial input format 2 (CCB = low) No. 5236-8/10 LC78845Q Data INITB = H SPSEL = L INITB = L B0 to B3 A0 to A3 LSI selection Address — — D0 D1 D2 D3 D4 D5 to D7 MKSEL FSEL1 FSEL2 MUTE STOP — L L L H L H The data and the signals correspond as listed in the tables. Since the external pins (MKSEL etc.) set by the serial input are unused, applications must assure that these pins do not become floating. If initialization is performed, set the initial values listed in the table. 5. Muting A soft muting function is applied to the data if the MUTE pin (pin 40) is set high when data with a 32 or 48 kHz sampling frequency is input. The input signal values are gradually attenuated so that the data reaches –∞ 1024/fs (seconds) later. When the soft muting function is turned off, the amplitude becomes the same as that of the input 1024/fs (seconds) later. For input data with a 44.1 sampling frequency, the data is forcibly set to 0 on the next rising edge of the LRCK signal after the MUTE signal goes from low to high. Similarly, data is output on the next rising edge of the LRCK signal after the MUTE signal goes from high to low. 6. Initialization When power is first applied, the LSI must be initialized when the pin settings are changed. Initialization is performed by holding INITB (pin 2) low for at least 1 µs in the state where the MCK1 signal is input after the power supply voltage has stabilized. No. 5236-9/10 LC78845Q 7. PLL block The PLL block generates a 14.112 MHz master clock (MCK2) that is used for all three frequencies; 32, 44.1, and 48 kHz, when either 32 or 48 kHz is specified as the input data sampling frequency. • STOP pin setting STOP Function L The VCO is stopped. H The VCO operates. • UNLK pin UNLK Function L Indicates that the PLL circuit is locked. H Indicates that the PLL circuit is in the unlocked state. The UNLK pin is high during unlocked periods and during the 1024/fs (seconds) required for the unlocked to locked transition. The LSI performs the same processing during the locked to unlocked transition as it does when MUTE is high. • External circuits Symbol Value R1 150 R2 5.1 k R3 5.1 k R4 24 k C1 0.02 C2 0.1 Unit Ω µF ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1996. Specifications and information herein are subject to change without notice. PS No. 5236-10/10