Ordering number : EN4346B CMOS LSI LC79400D Dot Matrix LCD Driver Overview Package Dimensions The LC79400D is a large-scale dot matrix LCD segment driver LSI. Display data transferred from the controller (4-bit parallel format) is processed through 80-bit latching and a LCD drive signal is generated. The LC79400D can be used in conjunction with common driver LC7943D (QIP80D) as well as LC79430D (QIP100D) and LC79431D (QIP100D) to drive a widescreen LCD panel. unit : mm 3180-QFP100D [LC73701M] Features • On-chip LCD drive circuit (80 bits) • Display duty selection ranging from 1/64 to 1/256 • Supports use of chip disable pin for lower large panel power supply dissipation • Supports externally supplied bias voltage • Operating power supply voltage/operating temperature include VDD (logic block) : 5 V ±10 % / –20 to +75 °C VDD-VEE (LCD block) : 12 V to 32 V / –20 to +75°C • Data transfer clock provides maximum 3.0 MHz and supports bidirectional shift • 4-bit parallel data input • CMOS process • 100-pin flat plastic package SANYO: MFP18 Specifications Absolute Maximum Ratings at Ta = 25±2°C, VSS = 0 V Parameter Symbol Maximum supply voltage (logic) VDD max Maximum supply voltage (LCD) VDD - VEE max*1 Maximum input voltage Storage temperature range VI max Tstg Conditions Ratings Unit –0.3 to +7.0 V 0 to 35 V –0.3 to VDD + 0.3 V –40 to +125 °C Note:1. The voltages V1, V3, V4, V7, VDD and VEE must obey the relationships: VDD ≥ V1 > V3 > V4 > VEE, VDD – V3 ≤ 7V, V4 – VEE ≤ 7V. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 73096HA (OT)/21593JN A8-9571 No. 4346-1/8 LC79400D Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V Parameter Symbol Supply voltage (logic) VDD Supply voltage (LCD) VDD - VEE Input high-level voltage VIH Input low-level voltage VIL Conditions min *2, *3 DI1 to 4, CP, LOAD, CDR, CDL R/L, M, DISP OFF typ max Unit 4.5 5.5 V 12 32 V 0.8 VDD V DI1 to 4, CP, LOAD, CDR, CDL 0.2 VDD R/L, M, DISP OFF V CP (shift clock) fCP CP CP (pulse width) fWC CP 100 ns LOAD pulse width tWL LOAD 100 ns ns 3.0 MHz Setup time tSETUP DI1 to 4 → CP 80 Hold time tHOLD DI1 to 4 → CP 80 ns CP → LOAD LOAD → CP Rise/Fall time tCL1 CP → LOAD 0 ns tCL2 CP → LOAD 100 ns tLC LOAD → CP 63 tR CP 50 ns tF CP 50 ns tRL LOAD 50 ns tFL LOAD 50 ns ns Note:2. The voltages V1, V3, V4, V7, VDD and VEE must obey the relationships: VDD ≥ V1 > V3 > V4 > VEE, VDD – V3 ≤ 7V, V4 – VEE ≤ 7V. 3. When applying power, apply power to the LCD drive block after applying power to the logic block or apply power to both the blocks simultaneously. When turning off power, turn off power to the logic block after turning off power to the LCD drive block or turn off power to both the blocks simultaneously. Electrical Characteristics at Ta = 25±2°C, VSS = 0 V, VDD = 5 V±10% Parameter Input high-level current Input low-level current Symbol IIH IIL Conditions VIN = VSS; LOAD, CP, CDR (CDL), VOH IOH = –400 µA; CDL (CDR) VOL IOL = 400 µA; CDL (CDR) RON2 Standby current dissipation IST ISS*5 Operation current dissipation ISS*6 Input capacity CI max Unit 1 µA –1 µA R/L, DI1 to DI4, M, DISP OFF Output low-level voltage RON1 typ R/L, DI1 to DI4, M, DISP OFF Output high-level voltage Driver on resistor min VIN = VDD; LOAD, CP, CDR (CDL), VDD – 0.4 VDD – VEE = 30 V, VDE – VO = 0.5 V*4; O1 to O80 VDD – VEE = 20 V, VDE – VO = 0.5 V*4; O1 to O80 V 0.4 V 1.5 3.0 kΩ 2.0 3.5 kΩ 200 µA 4.0 mA 0.1 mA CDR (CDL) = VDD, VDD – VEE = 30 V CP = 3.0 MHz, no-load output: VSS VDD – VEE = 30 V, CP = 3 MHz, LOAD = 14 kHz, M = 35 Hz; VSS VDD – VEE = 30 V, CP = 3 MHz, LOAD = 14 kHz, M = 35 Hz; VEE f = 3.0 MHz; CP 5 pF Note:4. VDE = V1 or V3 or V4 or VEE, V1 = VDD, V3 = 15/17 (VDD-VEE), V4 = 2/17 (VDD-VEE) 5. ISS current flows from VDD to VSS. 6. IEE current flows from VDD to VEE. Switching Characteristics at Ta = 25±2°C, VSS = 0 V, VDD = 5 V±10% Parameter Output delay time Symbol tD Conditions Load = 15 pF; CDR (CDL) min typ max Unit 200 ns No. 4346-2/8 LC79400D Pin Assignment A00971 Equivalent Circuit Block Diagram A00970 No. 4346-3/8 LC79400D Pin Descriptions Pin No Pin name Input/Output Functions 90 VDD 92 VSS 83 VEE VDD and VEE: Power supply for LCD drive circuit 86 V1 LCD drive level power supply VDD and VSS: Power supply for logic section Power supply 85 V3 84 V4 Power supply V1 and VEE : Select level 97 CP Input 81 CDR Input/Output Chip disable pin 100 CDL Input/Output H level : Data not accepted V3 and V4 : Nonselect level Display data shift clock (triggering on the trailing edge) L level : Data accepted 99 LOAD Input 93 DI4 Input 94 DI3 95 DI2 96 DI1 Pin Name Input/Output R/L Pin Description CDR Input L Control input pin for the IC’s internal disable F/F. CDL Output CDL Input H Output pin of the IC’s internal disable F/F. Connects to the next stage CDR pin when establishing a cascade connection. Control input pin for the IC’s internal disable F/F. CDR Output Output pin of the IC’s internal disable F/F. Connects to the next stage CDL pin when establishing a cascade connection. Display data latch clock (triggering on the trailing edge). On the trailing edge, output levels switch in response to the particular combination of display data, M and DISP OFF signals. R/L Input data and latch address L H 88 M Input LCD drive output alternating signal 91 R/L Input Input pin which performs input/output switching for CDR and CDL pins and directional shift for 4-bit parallel input data. 1 O1 Output 2 O2 LCD drive output The combination of display data, M signal, and DISP OFF signal can be used to create output levels as shown below. M Q DISP OFF Output 79 O79 L L H V3 80 O80 L H H V1 89 DISP OFF Input H L H V4 H H H VEE * * L V1 *Don’t care (To be set to either "H" or "L") Input pin which controls output pins O1 to O80. V1 level is output from O1 to O80 pin output during the low level input interval (See logic table). No. 4346-4/8 LC79400D Operation Timing (for R/L = H) A00974 No. 4346-5/8 LC79400D Time Chart (1/200 Duty 1/15 Bias)Switching Characteristics A00975 No. 4346-6/8 Sample Application A00976 LC79400D No. 4346-7/8 LC79400D Switching Characteristics A00973 ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 4346-8/8