Ordering number: EN 6158 CMOS IC LC7940YD,7941YD Dot-matrix LCD Drivers Overview Package Dimensions The LC7940YD and LC7941YD are segment driver ICs for driving large, dot–matrix LCD displays. They read 4– bit parallel or serial input, display data from a controller into an 80–bit latch, and then generate LCD drive signals corresponding to that data. unit: mm 3180–QIP100D [LC7940YD, LC7941YD] 23.2 20.0 • • • • 1.6 0.3 0.15 80 81 51 0.65 50 15.6 31 100 30 21.6 0.8 1 2.45max 80 built–in LCD display drive circuits 1/8 to l/128display duty cycle Serial or 4–bit parallel data input Chip disable for low power dissipation for large–sized panels Bias supply voltags can be supplied externally Operating supply voltage and ambient temperature - 2.7 to 5.5 V logic supply ( VDD) at Ta = –20 to +85°C - 8 to 20V LCD supply (VDD – VEE ) at Ta = –20 to +85 °C CMOS process 100–pin flat plastic package 1.6 • • • • 0.65 0.575 17.2 14.0 Features 0.825 The LC7940YD and LC7941YD feature mirror–image pin assignments, allowing them to be used together to increase component density. They are designed to be used with the LC7942YD common driver to drive large LCD panels. 2.15 0.8 SANYO : QFP100D (QIP100D) Specifications Absolute Maximum Ratings at Ta = 25 ± 2°C, VSS = 0 V Parameter Logic supply voltge LCD supply voltage, See Note below. Input voltage Symbol Ratings Unit VDD max –0.3 to +7.0 V VDD – VEE max 0 to 22 V VI max –0.3 to VDD + 03 V ■ Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. ■ SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co., Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 63099RM (ID) No. 6158—1/11 LC7940YD, LC7941YD Parameter Symbol Ratings Unit Operating temperature range Topr –20 to +85 °C Storage temperature range Tstg –40 to +125 °C Note VDD ≥ V1> V3 > V4 > VEE Recommended Operating Condltions at Ta = –20 to + 85°C, VSS = 0V Ratings Parameter Symbol Conditions Unit min Logic supply voltage VDD LCD supply voltage VDD – VEE See Notes 1 and 2. typ max 2.7 – 5.5 V 8 – 20 V HIGH–level input voltage VIH CP, CDl, DI1 to DI3, M, SDl, P/S, DISPOFF and LOAD 0.8VDD – – V LOW–level inpvt voltage VIL CP, CDI, Dl1 to DI3, M, SDl, P/S,DISPOFF and LOAD – – 0.2VDD V CP shift clock frequency fCP – 3.3 CP pulsewidth tWC 100 – – ns LOAD pulsewidth tWL 100 – – ns DIn and SDI to CP setup time tSETUP 80 – – ns DIn and SDI to CP hold time tHOLD 80 – – ns MHz tCL1 0 – – ns tCL2 100 – – ns LOAD to CP time tLC 100 – – ns CP rise time tR – – 50 ns CP fall time tF – – 50 ns LOAD rise time tRL – – 50 ns LOAD fall time tFL – – 50 ns CP to LOAD time Notes 1. VDD ≥ Vl > V3 > V4 > VEE 2. At turn ON, the LCD supply should be energized after or simultaneously with the logic supply. At turn OFF, the logic supply should be cut after or simultaneously with the LCD supply. Electrlcai Characterfstlcs at Ta = 25 ± 2°C,VSS = 0V, VDD = 2.7 to 5.5 V Ratings Parameter Symbol Conditions Unit min typ max HIGH–level input current IIH VIN =VDD; LOAD, CP, CDI, P/S, DI1 to DI3, SDl, M, and DISPOFF – – 1 µA LOW–level input current IIL VIN = VSS; LOAD, CP, CDl, P/S, DI1 to DI3, SDI, M, and DISPOFF – – –1 µA CDO HIGH–level output voltage VOH IOH = –400 µA VDD – 0.4 – – V CDO LOW–levef output voltage VOL IOL = 400 µA – – 0.4 V O1 to O80 driver ON resistance RON VDD – VEE = 18 V, |VDE – VO|= 0.25 V. See note – 2 4 kΩ No. 6158—2/11 LC7940YD, LC7941YD Ratings Parameter Symbol Conditions Unit min typ max IST CDI = VDD, VDD – VEE = 18 V, fCP = 3.3 MHz, no output load ; VSS – – 200 µA ISS VDD – VEE = 18 V, fCP = 3.3 MHz, ILOAD= 5.156 kHz, fM = 52 Hz ;VSS – – 1.0 mA VDD to VEE operating supply current IEE VDD – VEE = 18V, fCP = 3.3 MHz, fLOAD = 5,156 kHz, fM = 52 Hz ; VEE – – 0.1 mA CP input capacitance CI fCP = 3.3 MHz ; CP – 5 – pF VDD to VSS standby supply current VDD to VSS operating supply current Note VDD = V1 or V3, or V4 or VEE, V1 = VDD, V3 = 9/11 × (VDD – VEE), V4 = 2/11 × (VDD – VEE) Switching Characteristics at Ta = 25 ± 2°C,VSS = 0 V, VDD = 2.7 to 5.5 V Ratings Parameter Symbol Conditions Unit min CDO output delay time tD CL = 30 pF typ – max – 200 ns Switching Characteristics Waveform tR tWC tF tWC 0.8VDD CP 0.2VDD tSET UP tHOLD SDI DI1 to 3 tCL (1) tRL tCL (2) tFL tLC LOAD tWL tD tD CDO No. 6158—3/11 LC7940YD, LC7941YD NC 051 052 053 054 055 056 057 058 059 060 061 062 063 064 065 066 067 068 069 070 071 072 073 074 075 076 077 078 079 080 Pad Layout (Top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 050 CDO 82 49 049 NC 83 48 048 DISP OFF 84 47 047 P/S 85 46 046 VSS 86 45 045 VEE 87 44 044 V4 88 43 043 V3 89 42 042 NC 90 41 041 VDD 91 40 040 V1 92 39 039 M 93 38 038 DI1 94 37 037 DI2 95 36 036 DI3 96 35 035 SDI 97 34 034 LOAD 98 33 033 CDI 99 32 032 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 031 CP 01 02 03 04 05 06 07 08 09 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 026 027 028 029 030 01 02 03 04 05 06 07 08 09 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 026 027 028 029 030 CP LC7940YD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 031 82 49 032 LOAD 83 48 033 SDI 84 47 034 DI3 85 46 035 DI2 86 45 036 DI1 87 44 037 M 88 43 038 V1 89 42 039 VDD 90 41 040 NC 91 40 041 V3 92 39 042 V4 93 38 043 VEE 94 37 044 VSS 95 36 045 P/S 96 35 046 DISP OFF 97 34 047 NC 98 33 048 CDO 99 32 049 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 050 052 053 054 055 056 057 058 059 060 061 062 063 064 065 066 067 068 069 070 071 072 073 074 075 076 077 078 079 080 NC LC7941YD 051 CDI No. 6158—4/11 LC7940YD, LC7941YD Block Diagram 01 02 03 079 080 V1 V3 4 Level LCD Drive Circuit VDD V4 (80 bits) VSS VEE 80 Level Shifter (80 bits) M DISP OFF 80 2nd Latch (80 bits) 80 1st Latch (80 bits) SDI DI3 DI2 4 20 4 bits Address Decoder Data Bus Interface DI1 P/S SER/PAR Control CLK Address Counter (7 bits) Chip Disable & Latch Control CDO CDI CP LOAD Pin Functions Pin No. Synbol LC7940YD LC7941YD 91 90 VDD 86 95 VSS 87 94 VEE I/O Functions Supply VDD – VSS is the logic supply. VDD – VEE is the LCD supply. Supply LCD panel drive voltage supplies V1 and VEE are selected levels. V3 and V4 are not–selected levels. 92 89 V1 89 92 V3 88 93 V4 l00 81 CP I Display data Input clock (falling–edge trigger). 99 82 CDI I Chip disable. Data is read in when LOW, and not road in when HIGH. 98 83 LOAD I Display data latch clock (falling–edge trigger). On the falling edge, the LCD drive signals set by the display data are output. 97 84 SDI I Serial data input. No. 6158—5/11 LC7940YD, LC7941YD Pin No. Synbol I/O Functions LC7940YD LC7941YD 96 85 DI3 4–bit parallel data input pins. 95 86 DI2 Data input I 94 87 D11 LCD driver outputs SDI O4 O8 O80 DI3 O3 O7 O79 DI2 O2 O6 O78 DI1 O1 O5 O77 In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW. 93 88 M I LCD panel drive voltage output alternation control signal. 85 96 P/S I Data input mode select. 4–bit parallel input when HIGH, and serial input when LOW 82 99 CDO O Cascade connection pin for extension segment drivers. Data is read out when HIGH. Goes LOW after data is read out. Connected to the CDI input of the next chip. LCD drive outputs. The output drive level is determined by the display data, M signal and DISP OFF input as shown below. 1 to 80 80 to 1 Ol to O80 O M Q DISP OFF Output LOW LOW HIGH V3 LOW HIGH HIGH V1 HIGH LOW HIGH V4 HIGH HIGH HIGH VEE × × LOW V1 Note x = don’t care (tied HIGH or LOW) 84 97 DISPOFF 81 91 NC 83 98 NC 90 100 NC I O1 to O80 output control input pin. When LOW, V1 is output on the O1 to 080 outputs, See the truth table. – No connection. No. 6158—6/11 7R R R R R VEE – + – + – + – + LA5311M –11 to –13V VDD controller 6 V5 V4 V3 V2 V1 ED2 4 V1 V2 V5 VEE CL2 01 DI01 DI064 01 064 CP 4 V1 V2 V5 VEE 036 LC7942YD M 4 CP OD2 DI01 LC7942YD M CL1 M 4 V1 V3 V4 VEE 100 M LC7941YD (LC7941YD) V1 V3 V4 VEE LC7940YD M V1 V4 VEE V1 V3 V4 V3 VEE CDI CDO V1 V4 LC7941YD V1 V3 V4 VEE LC7940YD M VEE V1 V3 V4 (LC7940YD) LC7941YD M M LC7941YD (LC7941YD) V3 VEE V1 V3 V4 VEE LC7940YD LCD panel (640 × 200 pixels) (LC7941YD) 640 1280 (LC7940YD) LC7941YD 639 1279 FLM CDO 482 1122 CDI 481 1121 (LC7940YD) LC7941YD VEE M 480 1120 ED1 V4 V1 V3 479 1119 OD1 M M 322 962 V3 321 961 VEE CDI M CDO V4 VEE V1 V3 V4 V1 (LC7940YD) LC7941YD M M VEE V3 M V1 V3 V4 VEE LOAD CP OD2 ED2 LC7941YD (LC7941YD) LC7940YD 162 802 V1 161 801 V4 160 800 M 320 960 CP SDI LOAD 159 799 CP SDI LOAD 2 642 CP SDI LOAD 319 959 OD1 ED1 CP LOAD 1 641 2 CDI CP SDI LOAD 4 4 CP SDI LOAD LC7940YD, LC7941YD Application Notes LCD Panel 1 No. 6158—7/11 7R R R R R VEE – + – + – + – + LA5311M –11 to –13V VDD CP LOAD M V5 V4 V3 V2 V1 4bit Data controller FLM 4bit Data 6 4 DI01 01 01 4 4 V1 V2 V5 VEE CP 036 LC7942YD-#1 M DI01 CP 064 LC7942YD-#1 M 4 4 V1 V3 V4 VEE 100 100 LC7941YD-#8 LC7941YD-#8 2 2 4 4 4 LC7941YD-#2 2 4 LC7941YD-#2 LCD panel (640 × 200 pixels) 2 2 2 4 4 CDO CDO M V1 V3 V4 VEE 01 01 LC7941YD-#1 080 080 4 2 4 CP LOAD 4 4bit Data CDI CDI 4bit Data V1 V3 V4 VEE CP LOAD LC7941YD-#1 M 2 LC7940YD, LC7941YD LCD Panel 2 No. 6158—8/11 LC7940YD, LC7941YD 100 × 240–pixel LCD Panel Application A 100 × 240–pixel LCD panel requires the following drivers. • 3 × LC7940YD (or LC7941YD) drivers • 2 × LC7942YD drivers An example using l/l00 duty cycle is shown below. (m,n) : pixel address 1,79 Segment line (n) Common line (m) Frame signel DI01 01 RS/LS 02 LC7942YD 1,1 1,2 2,1 2,2 1,80 1,82 1,81 1,160 --- 63,1 63,2 64,1 64,2 DI01 01 RS/LS 02 65,1 65,2 66,1 66,2 ----- 64,80 64,81 65,80 65,81 ----- --- 1,240 2,240 --- --- 063 1,161 --- --- LCD panel (100 × 240 pixels) DI064 064 #1 CP M 1,79 --- 64,160 64,161 65,160 65,161 ----- 64,240 65,240 LC7942YD 100,1 100,2 01 02 --- 100,79 100,80 100,81 100,82 --- --- --- --- 036 --- #2 CP M 100,160 100,161 --- 100,240 DI064 O37 to O64 are open. 080 LC7940YD #2 CDO (LC7941YD) P/S DI1 DI2 DI3 SDI CP LOAD M M LOAD CDI CP LC7940YD #2 CDO (LC7941YD) SDI 01 DI3 080 DI2 02 DI1 CDI P/S M LOAD CDO CP SDI DI3 DI2 DI1 P/S #1 01 Data shift clock Serial data Alternating signal 080 LC7940YD (LC7941YD) CDI Data latch clock 079 1. The LC7942YD chips are cascaded by connecting DIO64 on chip I to DIO1 on chip 2. For a 100–bit shift register, 037 to 064 on chip 2 are left open. 2. The LC7940YD (or LC7941YD) chips are cascaded by connecting CDO on chip I to CDI on chip 2, and CDO on chip 2 to CDI on chip 3. CDI on chip I is tied to GND, and CDO on chip 3 is not used. This configuration allows the input of 240–bit serial data. No. 6158—9/11 LC7940YD, LC7941YD 100 x 240-pixel LCD Panel Timing Diagram M LOAD CP SDI 1,1 1,2 --- 1,79 1,80 1,81 --- 1,160 1,161 --- 1,240 #1 SDO #2 #3 Chip 2 data read Chip 1 data read Chip 3 data read 1 line (240 bits) M LOAD CP SDI 1,1 1,2 --- 1,239 1,240 1st line data read 2,1 --- 2,240 3,1 --- 100,240 2nd line data read 1 frame (100 × 240 bits) M #1 DIO1 #1 2,1 --- 98,1 99,1 100,1 1,1 --- 99,1 100,1 02 1,2 2,2 --- 98,2 99,2 100,2 1,2 --- 99,2 100,2 080 1,80 2,80 --- 98,80 99,80 100,80 1,80 --- 99,80 100,80 01 1,81 2,81 --- 98,81 99,81 100,81 1,81 --- 99,81 100,81 080 1,160 2,160 --- 98,160 99,160 100,160 1,160 --- 99,160 100,160 01 1,161 2,161 --- 98,161 99,161 100,161 1,161 --- 99,161 100,161 1,240 2,240 --- 98,240 99,240 100,240 1,240 --- 99,240 100,240 --- #3 1,1 --- #2 01 LCD drive output data LOAD 080 No. 6158—10/11 LC7940YD, LC7941YD Segment Data Not Multiples of 4 Example. LCD panel (100 × 230 pixels) --- --01 080 01 01 080 LC7940YD #2 LC7940YD #1 080 LC7940YD #3 LOAD SDI m,1 m,2 --- ,228 m,229 m,230 If this timing data is sent, data elements (m, 229), (m, 230), (m+1, 229), (m+1. 230)... will not appear in the output (O69 and O70 on chip 3). This is because the LC7940YD (or LC7941YD) converts serial/parallel data m+1,1 m+1,2 ,228 m+1,229 m+1,230 in 4–bit units, which also decreases power dissipation . For data that is not a multiple of 4, like 230, the following scheme is used. LOAD SDI m,1 m,2 --- ,228 m,229 Vaild display data m,230 m,231 m,232 Dummy data Multiple of 4 In this case, (m, 231) is output on O71 on chip 3, and (m, 232) on O72 on chip 3. However, these outputs are not connected to the panel and are, therefore, invalid. ■ Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. ■ SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. ■ In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. ■ No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co. , Ltd. ■ Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. ■ Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1999. Specifications and information herein are subject to change without notice. No. 6158—11/11