CMOS LSI No. LC82151 *5601 Single-Chip Facsimile Controller Preliminary Overview The LC82151 is a facsimile controller that integrates the main functions required by facsimile systems on a single chip. The LC82151 includes a FAX modem with ADPCM and HDLC functions, image processing functions that can create high-quality binary image data without external memory, a CODEC accelerator, a CPU and CPU peripheral circuits, general-purpose I/O ports, and other functions. A facsimile system with excellent costperformance characteristics can be created easily by providing ROM and RAM. Functions • CPU and peripheral circuits – High-speed 16-bit CPU (65C816) operating at 7.4 MHz – 16-MB program address space – CODEC accelerator – Two-channel DMA controller – Four 16-bit timers – 16-bit watchdog timer – TPH interface – Serial I/O interface – Parallel I/O: 10 to 43 pins • Image processing – Processes 2048 pixels per line – Processing speed: 540 ns per pixel (maximum) – Built-in 8-bit A/D converter (Includes a sensor signal delay function.) – Sensor drive circuit (Supports CCDs and all major CIS devices.) – Distortion correction (White distortion: 8-pixel averaging correction, black correction: Allows the black correction subtraction data to be set.) – γ-correction (Supports user-defined correction curves.) – Simple binary conversion processing (fixed threshold and density-adaptive threshold) – Halftone processing error diffusion method (64 levels) – Image reduction (decimation, fine black line retention, and fine white line retention) • Modem – Group 3 FAX modem ITU-T V.29 (9600, 7200, and 4800 bps) ITU-T V.27ter (4800 and 2400 bps) ITU-T V.21ch2 (300 bps) – Simultaneous high/low-speed wait function – Short training function (ITU-T V.27ter only) – HDLC function (for all transmission speeds) – Synthesizer function – Caller ID function Bell 202 (1200 bps) ITU-T V.23 (1200 bps) – ADPCM function Encoding: 2, 3, or 4 bits Sampling frequencies: 9.6, 7.2, 4.8, and 3.6 kHz – RTC low-voltage backup – 5-V single-voltage power supply Package Dimension unit: mm 3214-SQFP144 [LC82151] SANYO: SQFP144 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 43097 (OT) No. 5601-1/8 LC82151 Block Diagram AIN, ATAP, TEMP, SH, RS, ACLK1, ACLK2, ASAMP, DAREFH, DAREFL Ø2, RES, R/W, IRQ, VP, RDY, BE, NMI, VPA, VDA, ABCNT RD, WR ROMCS, RAMCS, IOCS, MCS BREQ, BACK, EXRDY PA7 to PA0 PB2 to PB0 TO0 TO1 RTC, CTS, DSR, DTR, RI, DCD TD, RD PCK/SCLK, PDATA/TXD, EXCLK, LATCH/RXD, STB0 to STB3, HVON PROTECT XTAL1, XTAL2, XOUT,CLKIN, RESET, BACKUP TEST2 to TEST0 TESTOUT CPU 65C816 Image processing PXD7 to PXD0 PDREQ, PDACK TXA, RXA, PGCO, PGCI, VREF, RIN, VCOI, PHASEO, EYED, EYECLK, EYESYNC CPU interface Modem PIO CODEC accelerator Timer RTC SIO DMAC WDT Interrupt controller INT2 INT8 TPH interface DRAM controller RAS CAS ROSC1 ROSC2 D7 to D0 A19 to A0 No. 5601-2/8 LC82151 Pin Assignment Type I Input pins B Bidirectional pins O Output pins P Power pins Pin No. Pin I/O 1 VSS P Ground ICE vector address signal NC No connection Pin function 2 VP I 3 RDY O ICE ready signal 4 VPA I ICE valid program address signal 5 VDA I ICE valid data address signal 6 A19 O 7 A18 O 8 A17 O Address bus 9 A16 O 10 D7 B 11 D6 B 12 D5 B 13 D4 B 14 D3 B 15 D2 B 16 D1 B 17 D0 B 18 VDD P 19 VSS P Ground 20 RD O Read signal from the CPU Data bus Power supply 21 WR O Write signal from the CPU 22 ROMCS O Program ROM chip select signal 23 RAMCS O Working RAM chip select signal 24 IOCS O External I/O chip select signal 25 MCS O External I/O chip select signal 26 RAS/PG1 B DRAM row address strobe/general-purpose port G 27 CAS/PG2 B DRAM column address strobe/general-purpose port G 28 PA7 B 29 PA6 B 30 PA5 B 31 PA4 B 32 PA3 B 33 PA2 B 34 PA1 B 35 PA0 B 36 VSS P 37 VDD P Power supply 38 RIN I PLL bias input 39 PHASEO O PLL phase detector output 40 VCOI I PLL voltage-controlled oscillator input 41 INT8/PB7 B 42 INT2/PB6 B 43 BACK/PB5 B 44 BREQ/PB4 B CPU bus request signal/general-purpose port B 45 EXRDY/PB3 B External ready input/general-purpose port B 46 PB2 B 47 PB1 B 48 PB0 B 49 NMI I Non-maskable interrupt request signal 50 TEST2 I Test pin General-purpose port A Ground External interrupt request signal/general-purpose port B CPU bus acknowledge signal/general-purpose port B General-purpose port B Continued on next page. No. 5601-3/8 LC82151 Continued from preceding page. Pin No. Pin I/O 51 TEST1 I 52 TEST0 I 53 TESTOUT I Pin function Test pins 54 VDD P Power supply 55 VSS P Ground 56 ROSC1 I 57 ROSC2 O 58 BACKUP I Low power mode input 59 RESET I System reset signal 60 AVDD P Analog system power supply 61 AVSS P Analog system ground 62 AIN I Sensor signal input 63 TEMP I Thermistor input 64 ATAP O A/D converter reference voltage output 65 DAREFH I D/A converter high-level reference voltage input 66 DAREFL I D/A converter low-level reference voltage input 67 TXA O Modem analog transmit output 68 RXA I Modem analog receive input 69 PGCO O Modem gain adjustment output 70 PGCI I Modem gain adjustment input 71 VREF I Modem analog block reference input Ground RTC crystal oscillator connections 72 VSS P 73 VDD P Power supply 74 SH O Image sensor start pulse 75 RS O Image sensor reset pulse 76 ACLK1 O 77 ACLK2 O 78 ASAMP O 79 PXD7/PC7 B 80 PXD6/PC6 B 81 PXD5/PC5 B 82 PXD4/PC4 B 83 PXD3/PC3 B 84 PXD2/PC2 B 85 PXD1/PC1 B 86 PXD0/PC0 B 87 PDREQ/PF7 B Image data DMA request signal/general-purpose port F 88 PDACK/PF6 B Image data DMA acknowledge signal/general-purpose port F 89 EYED/PF5 B Eye pattern data output/general-purpose port F 90 VDD P Power supply 91 VSS P Ground 92 EYECLK/PF4 B Eye pattern data clock/general-purpose port F 93 EYESYNC/PF3 B Eye pattern data synchronizing signal/general-purpose port F 94 TO1/PF2 B 95 TO0/PF1 B 96 PCK/SCLK/PE7 B 97 PDATA/TXD/PE6 B Thermal head serial output data/serial I/O send data/general-purpose port E 98 EXCLK/PE5 B Thermal head control external clock/general-purpose port E 99 LATCH/RXD/PE4 B Thermal head data latch signal/serial I/O receive data/general-purpose port E 100 STB3/PE3 B 101 STB2/PE2 B 102 STB1/PE1 B 103 STB0/PE0 B 104 HVON/PF0 B Head power on/off control signal/general-purpose port F 105 PROTECT/PG0 B Head protection abnormality indication signal input/general-purpose port G Image sensor data transfer clocks Built-in A/D converter sampling point monitor signal Image data output/general-purpose port C Timer outputs/general-purpose port F Thermal head data transfer clock/serial I/O clock/general-purpose port E Thermal head strobe signal/general-purpose port E Continued on next page. No. 5601-4/8 LC82151 Continued from preceding page. Pin No. Pin I/O 106 XTAL1 I Pin function 107 XTAL2 O 108 VSS P Ground 109 VDD P Power supply 110 XOUT O Crystal oscillator clock output 111 CLKIN I System clock input 112 A15 B 113 A14 B 114 A13 B 115 A12 B 116 A11 B 117 A10 B 118 A9 B 119 A8 B 120 TD/PD7 B Serial port transmit data output/general-purpose port D 121 RD/PD6 B Serial port receive data input/general-purpose port D 122 RTS/PD5 B Request to send signal/general-purpose port D 123 CTS/PD4 B Clear to send signal/general-purpose port D 124 DSR/PD3 B Data set ready/general-purpose port D 125 DTR/PD2 B Data terminal ready/general-purpose port D 126 VDD P Power supply 127 VSS P Ground 128 RI/PD1 B Ring indicator/general-purpose port D 129 DCD/PD0 B Data carrier detect/general-purpose port D 130 A7 B 131 A6 B 132 A5 B 133 A4 B 134 A3 B 135 A2 B 136 A1 B 137 A0 B 138 ABCNT O ICE bus control signal 139 BE O ICE bus enable signal System clock crystal oscillator element connection (29.4912 MHz) Address bus Address bus 140 ø2 O ICE system clock 141 RES O ICE reset signal 142 RWB I ICE read/write signal 143 IRQ O ICE interrupt request signal 144 VDD P Power supply No. 5601-5/8 LC82151 Sample Application NCU Public telephone network Document Fluorescent lamp Telephone Stepping motor Lens Image sensor Facsimile controller RAM Motor driver Temperature sensor ROM LC82151 Cutter Thermal head To LCD Stepping motor Paper To key matrix No. 5601-6/8 LC82151 Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage VDD max Input and output voltage VI, VO Allowable power dissipation Pd max Conditions Ratings Unit –0.3 to +7.0 V –0.3 to VDD +0.3 V Ta ≤ 70°C 550 mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C Soldering temperature Manual soldering (3 seconds) 350 °C Reflow soldering (10 seconds) 235 °C Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V Parameter Symbol Conditions Ratings min typ Unit max Supply voltage VDD 4.5 5.5 V Input voltage VIN 0 VDD V Electrical Characteristics at Ta = –30 to +70°C, VDD = 4.5 to 5.5 V Parameter Symbol Input high-level voltage VIH1 Input low-level voltage VIL1 Input leakage current IL Conditions Ratings min typ Unit max 2.2 V –10 Output high-level voltage VOH IOH = –4mA Output low-level voltage VOL IOL = 4mA Output leakage current IOZ When outputs are high impedance 0.8 V +10 µA 2.4 V –10 0.4 V +10 µA IPOZ PHASEO = 2 V 7 15 27 mA INOZ PHASEO = 2 V –8 –15 –28 mA Vref input voltage VREF VREF Vref impedance VREF VREF Charge pump output current VDD/2 V 1 MΩ Input voltage range VIA RXA, PGCI VDD × 0.2 VDD × 0.8 Operating voltage range VOA TXA, PGCO VDD × 0.2 VDD × 0.8 Output impedance RO TXA, PGCO Oscillator frequency Current drain 7.0 fCLK1 XTAL1, XTAL2, CLKIN fCLK2 ROSC1, ROSC 2 IDD1 Operating IDD2 In backup mode, VDD = 2.5 V, BACKUP = 0 V V kΩ 29.4912 MHz 32.768 kHz 100 mA 5 µA Power on Timing Applications must control the timing of the power on sequence carefully. Although AVSS and VSS are completely isolated internally in the LC82151, AVDD and VDD are connected through the substrate. This means that there must be no potential difference between AVDD and VDD. Also, the power supply voltage rise and fall times must be under 3 ms. Analog Characteristic D/A Converter Parameter Symbol Conditions Ratings min typ Resolution Unit max 6 Reference resistors value DAREFL, DAREFH bit 5.0 kΩ A/D Converter at an ATAP potential of 4.2 V A/D Converter Parameter Resolution Symbol Conditions Ratings min typ Unit max 8 bit Linearity error ±1 LSB Differential linearity error ±1 LSB No. 5601-7/8 LC82151 ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 1997. Specifications and information herein are subject to change without notice. No. 5601-8/8