Ordering number : ENN*6750 CMOS IC LC86E6560 8-Bit Single Chip Microcontroller with the UVEPROM Preliminary Overview The LC86E6560 is a CMOS 8-bit single chip microcontroller with UVERPOM for the LC866500 series. This microcontroller has the function and the pin description of the LC866500 series mask ROM version, and 60K-byte EPROM. The program data is rewritable. It is suitable to develop the program. Features (1) Option switching by EPROM data The option function of the LC866500 series can be specified by the EPROM data. LC86E6560 can be checked the functions of the trial pieces using the mass production board. (2) Internal EPROM capacity : 61696 bytes (3) Internal RAM capacity : 1152 bytes Used EPROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86E6560. Mask ROM version LC866560 LC866556 EPROM capacity 61440 bytes 57344 bytes RAM capacity 1152 bytes 1152 bytes (4) Operating supply voltage : 4.5V to 6.0V (5) Instruction cycle time : 1.0µs to 366µs (6) Operating temperature : +10°C to +40°C (7) The pin compatible with the LC866500 series mask ROM devices (8) Applicable mask ROM version : LC866560/LC866556 (9) Factory shipment : QFC100S (with window) Ver.1.02 21897 91400 RM (IM) SK No.6750-1/21 LC86E6560 Notice for use LC86E6560 is provided for the first release and small shipping of the LC866500 series. At using, take notice of the followings. (1) A point of difference LC86E6560 and LC866500 series. Item Operation after reset releasing Pull-down resistor of the following pins •S0/T0 - S6/T6 •S7/T7 - S15/T15 •S16 -S31 •S32 - S47 •S48 -S51 Operating temperature range (Topg) Power dissipation LC86E6560 The option is specified until 3ms after going to a ‘H’ level to the reset terminal by degrees. The program is executed from 00H of the program counter. Pull-down resistor provided/not provided Not provided Provided (fixed) Provided (fixed) Not provided Not provided LC866560/56 The program is executed from 00H of the program counter immediately after going to a ‘H’ level to the reset terminal. 10°C to 40°C -30°C to 70°C Pull-down resistor provided/not provided Specified by the option Provided (fixed) Specified by the option Specified by the option Not provided Refer to ‘electrical characteristics’ on the semiconductor news. LC86E6560 uses 256 bytes that is addressed on FF00H to FFFFH in the program memory as the option configuration data area. This option configuration cannot execute all options which LC866500 series have. Next tables show the options that correspond and not correspond to LC86E6560. • A kind of the option corresponding of the LC86E6560 A kind of option Input/output form of input/output ports Pins, Circuits Port 0 Port 1 *1 Port 3 *1 Contents of the option 1. N-channel open drain output 2. CMOS output *1 1. Pull-up MOS Tr. provided 2. Pull-up MOS Tr. not provided *2 : Programmable pull-up MOS Tr. 1. Input : N-channel open drain Output : Programmable pull-up MOS Tr. 2. Input :CMOS Output : Programmable pull-up MOS Tr. 1. Input : N-channel open drain Output : Programmable pull-up MOS Tr. 2. Input :CMOS Output *1) Specified in a bit *2) Specified in nibble unit. The port of N-channel open drain output does not have the Pull-up MOS Tr.. • A kind of the option not corresponding of the LC86E6560 A kind of option Pull-down resistor of the high voltage withstand output terminals Pins, Circuits •S0/T0 to S6/T6 •S16 to S31 •S32 to S47 LC86E6560 Not provided Provided (fixed) Not provided LC866560/56 Specified by the option Specified by the option Specified by the option (2) Option The option data is created by the option specified program “SU86K.EXE”. The created option data is linked to the program area by linkage loader “L86K.EXE”. (3) ROM space LC86E6560 and LC866500 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the option specified data area. These program memory capacity are 61440 bytes that is addressed on 0000H to EFFFH. No.6750-2/21 LC86E6560 0FFFFH 0FF00H The option specified area 256 bytes 0EFFFH 0DFFFH 0CFFFH 0BFFFH 0AFFFH 9FFFH 8FFFH 7FFFH 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH Program area 60K bytes 1FFFH 0000H LC866560 The option specified area Program area 56K bytes LC866556 No.6750-3/21 LC86E6560 How to use (1) Preparation A complete evaluation (EVA) file must be converted to an INTEL-HEX formatted (HEX) file for program to the LC86E6560. An EVA2HEX.EXE. can convert a EVA file to a HEX file. Program the file that converted by the EVA2HEX to the LC86E6560. (2) How to program for the EPROM LC86E6560 can be programmed by the EPROM programmer with attachment ; W86EP6548Q. • Recommended EPROM programmer Productor Advantest Andou AVAL Minato electronics EPROM programmer R4945, R4944, R4943 AF-9704 PKW-1100, PKW-3000 MODEL1890A • ”27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to “0 to 0FFFFH” and a jumper (DASEC) must be set to ‘OFF’ at programming. (3) How to use the data security function “Data security” is the disabled function to read the data of the EPROM. The following is the process in order to execute the data security. 1. Set ‘ON’ the jumper of attachment. 2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data security. It is not a trouble of the EPROM programmer or the LSI. Notes • Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above. • The programming by a sequential operation “BLANK⇒PROGRAM⇒VERIFY” cannot be executed data security at the sequence 2 above. • Set to ‘OFF’ the jumper after executing the data security. Data security 1 pin mark of LSI 1 pin Not data security W86EP6548Q (4) How to eliminate The programming data can be erased by using the EPROM eraser. (5) Shielding The UVEPROM (ultraviolet erasable programmable ROM) is in it. Put the seal on the window in use. No.6750-4/21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 S48/PG0 S49/PG1 S50/PG2 S51/PG3 P00 P01 P02 P03 VSS2 VDD2 P04 P05 P06 P07 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/BUZZ P17/PWM0 P30 P31 P32 P33 P34 P35 P36 P37 P70/INT0 RES XT1/P74 XT2/P75 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P71/INT1 P72/INT2/T0IN P73/INT3/T0IN S0/T0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 VDD4 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 S20/PC4 VP LC86E6560 Pin Assignment 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S19/PC3 S18/PC2 S17/PC1 S16/PC0 VDD3 S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8 S7/T7 S6/T6 S5/T5 S4/T4 S3/T3 S2/T2 S1/T1 SANYO : QFC100S No.6750-5/21 LC86E6560 System Block Diagram Interrupt Control IR Standby Control RC A15-A0 D7-D0 TA CE OE DASEC EPROM Control Colck Generator CF PLA EPROM (48KB) X’tal PC Base Timer Bus Interface ACC SIO0 Port 1 B Register SIO1 Port 3 C Register Timer 0 Port 7 ALU Timer 1 Port 8 ADC PSW INT0 to 3 Noise Filter RAR SIO Automatic transmission RAM RAM 128 bytes Stack Pointer Port 0 VFD controller Watchdog Timer High voltage Output No.6750-6/21 LC86E6560 Pin Description Pin Name I/O VSS1, 2 VDD1, 2, 3, 4 VP PORT 0 P00 - P07 I/O Power pin (-) *4 Power pin (+) *4 Power pin (+) for the VFD output pull-down resist •8-bit input/output port Input/output in nibble units •Input for port0 interrupt •Input for HOLD release •15V withstand at N-channel open drain output PORT 1 P10 - P17 I/O PORT 3 P30 - P37 I/O •8-bit input/output port Input/output can be specified in bit unit. •Other pin functions P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input/bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer1 output (PWM0 output) •8-bit input/output port Output form : Input/output in bit unit CMOS/N-channel open •15V withstand at N-channel open drain output drain (each bit) •4-bit input/output port Input/output in bit unit •2-bit input port •Other pin functions P70 : INT0 input/HOLD release/N-channel Tr. output for watchdog timer P71 : INT1 input/HOLD release input P72 : INT2 input/timer0 event input P73 : INT3 input with noise filter/timer0 event input P74 : 32.768kHz crystal oscillation terminal XT1 P75 : 32.768kHz crystal oscillation terminal XT2 •Interrupt received form, vector address rising falling rising/ H level L level Vector falling 03H enable enable disable enable enable INT0 0BH enable enable disable enable enable INT1 13H enable enable enable disable disable INT2 1BH enable enable enable disable disable INT3 •4-bit input/output port Input/output in bit unit •4-bit input port •Other function AD input port (8 port pins) Output for VFD display controller segment/timing in common •Output for VFD display controller segment /timing with internal pull-down resistor in common •Internal pull-down resistor output PORT 7 P70 - P73 I/O I P74 - P75 PORT 8 I I/O P80 -P83 P84 -P87 S0/T0 to S6/T6 S7/T7 to S15/T15 O *6 O *7 Function description EPROM mode Option •Pull-up resistor : Provided/not provided (each nibble) •Output form : CMOS/N-channel open drain (each bit) Output form : CMOS/N-channel open drain (each bit) - Data line D0 to D7 - EPROM control signal DASEC(*1) OE (*2) CE (*3) - TA (*5) (Continue) No.6750-7/21 LC86E6560 Pin Name I/O S16 to S31 I/O *8 S32 to S47 I/O *9 S48 to S51 I/O *9 RES I XT1/ P74 I XT2/P75 O CF1 CF2 I O Function description Option •Output for VFD display controller segment •Other function S16 : High voltage input port PC0 S17 : High voltage input port PC1 S18 : High voltage input port PC2 S19 : High voltage input port PC3 S20 : High voltage input port PC4 S21 : High voltage input port PC5 S22 : High voltage input port PC6 S23 : High voltage input port PC7 S24 : High voltage input port PD0 S25 : High voltage input port PD1 S26 : High voltage input port PD2 S27 : High voltage input port PD3 S28 : High voltage input port PD4 S29 : High voltage input port PD5 S30 : High voltage input port PD6 S31 : High voltage input port PD7 •Output for VFD display controller segment •Other function S32 : High voltage input port PE0 S33 : High voltage input port PE1 S34 : High voltage input port PE2 S35 : High voltage input port PE3 S36 : High voltage input port PE4 S37 : High voltage input port PE5 S38 : High voltage input port PE6 S39 : High voltage input port PE7 S40 : High voltage input/output port PF0 S41 : High voltage input/output port PF1 S42 : High voltage input/output port PF2 S43 : High voltage input/output port PF3 S44 : High voltage input/output port PF4 S45 : High voltage input/output port PF5 S46 : High voltage input/output port PF6 S47 : High voltage input/output port PF7 •Output for VFD display controller segment •Other function S48 : High voltage input/output port PG0 S49 : High voltage input/output port PG1 S50 : High voltage input/output port PG2 S51 : High voltage input/output port PG3 Reset pin •Input pin for 32.768kHz crystal oscillation •Other function XT1 : Input port P74 In case of non use, connect to VDD1. •Output pin for 32.768kHz crystal oscillation •Other function XT2 : Input port P75 In case of non use, connect to VDD1 at using as port or unconnect at using as oscillation. Input pin for ceramic resonator oscillation Output pin for ceramic resonator oscillation - EPROM mode Address input A15 to A0 - - - - - - - - - - - - * All of port options (except pull-up resistor of port 0) can be specified in bit unit. (Continue) No.6750-8/21 LC86E6560 *1 *2 *3 *4 *5 *6 *7 *8 *9 Memory select input for data security Output enable input Chip enable input Connect like the following figure to reduce noise into a VDD1 terminal. Shorted the VSS1 terminal to the VSS2 terminal and to make the back-up time long. TA!EPROM control signal input S0/T0 to S6/T6 : not provided the pull-down resistor S7/T7 to S15/T155 : provided the pull-down resistor (fixed) S16 to S31 : provided the pull-down resistor (fixed) S32 to S51 : not provided the pull-down resistor LSI VDD1 Power Supply Back-up capacitor VDD2 VDD3 VFD powers VDD4 VSS1 VSS2 No.6750-9/21 LC86E6560 1. Absolute Maximum Ratings at VSS1=VSS2=0V and Ta=25°C Parameter Symbol Supply voltage VDDMAX Input voltage VI(1) Output voltage VI(2) VO Input/output voltage VIO(1) VIO(2) High level output current Peak output current Total output current Low level output current Peak output current Total output current Maximum power dissipation Operating temperature range Storage temperature range VIO(3) IOPH(1) IOPH(2) IOPH(3) ∑IOAH(1) ∑IOAH(2) ∑IOAH(3) ∑IOAH(4) ∑IOAH(5) ∑IOAH(6) IOPL(1) IOPL(2) ∑IOAL(1) ∑IOAL(2) ∑IOAL(3) Pdmax Pins Conditions VDD1, VDD2 VDD3, VDD4 •Ports P74 , 75 •Ports 80, 81, 82, 83 •Port 8 • RES VP S0/T0 to S15/T15 •Port 1 •Ports 70, 71, 72, 73 •Ports 84, 85, 86, 87 •Ports 0, 3 at CMOS output option Ports 0, 3 at N-ch open drain output option S16 to S51 Ports 0, 1, 3 VDD1=VDD2 =VDD3=VDD4 S0/T0 to S15/T15 S16 to S51 Port 0 Ports 1, 3 S0/T0 to S15/T15 S16 to S27 S28 to S39 S40 to S51 Ports 0, 1, 3 •Ports 70, 71, 72, 73 •Ports 84, 85, 86, 87 Port 0 Ports 1, 3, 70 •Ports 71, 72, 73 •Ports 84, 85, 86, 87 QFC100S VDD[V] min. -0.3 Ratings typ. max. 7.0 -0.3 VDD+0.3 VDD-4.5 VDD-4.5 VDD+0.3 VDD+0.3 -0.3 VDD+0.3 -0.3 15 VDD-4.5 VDD+0.3 •CMOS output •For each pin. At each pin. -10 -30 At each pin. The total all pins. The total all pins. The total all pins. -15 -30 -30 -55 The total all pins. The total all pins. The total all pins. At each pin. At each pin. -60 -60 -60 unit V mA 20 15 The total all pins. The total all pins. The total all pins. 60 50 20 Ta=+10 to +40°C 500 mW Topr +10 +40 °C Tstg -55 +125 °C No.6750-10/21 LC86E6560 2. Recommended Operating Range at Ta=+10°C to +40°C, VSS1=VSS2=0V Parameter Symbol Pins Operating supply voltage range Hold voltage VDD(1) VHD VDD1=VDD2 Pull-down voltage Input high voltage VP VP VIH(1) Port 0 at CMOS output option Port 0 at N-ch open drain output •Port 1 •Ports 72, 73 •Port 3 at CMOS output option Port 3 at N-ch open drain output •Port 70 Port input /interrupt •Port 71 • RES Port 70 Watchdog timer •Port 8 •Ports P74 , 75 S16 to S51 VIH(2) VIH(3) VIH(4) VIH(5) VIH(6) VIH(7) VIH(8) Input low voltage VIL(1) VIL(2) VIL(3) VIL(4) VIL(5) VIL(6) VIL(7) Operation cycle time VDD1=VDD2= VDD3=VDD4 Port 0 at CMOS output option Port 0 at N-ch open drain output •Ports 1, 3 •Ports 72, 73 •Port 70 Port input /interrupt •Port 71 • RES Port 70 Watchdog timer •Port 8 •Ports P74 , 75 S16 to S51 Conditions VDD[V] 0.98µs≤tCYC min. 4.5 Ratings typ. max. 6.0 unit V ≤400µs RAMs and registers hold voltage at HOLD mode. 4.5 - 6.0 2.0 6.0 -35 VDD Output disable 4.5 - 6.0 0.33VDD VDD Output disable +1.0 4.5 - 6.0 0.75VDD 13.5 Output disable 4.5 - 6.0 0.75VDD VDD Output disable Tr. OFF Output disable 4.5 - 6.0 0.75VDD 13.5 4.5 - 6.0 0.75VDD VDD Output disable 4.5 - 6.0 0.9VDD VDD Output disable 4.5 - 6.0 0.75VDD VDD Output P- channel Tr. OFF Output disable 4.5 - 6.0 0.33VDD VDD 4.5 - 6.0 VSS 0.2VDD Output disable 4.5 - 6.0 VSS 0.25VDD Output disable 4.5 - 6.0 VSS 0.25VDD Output disable 4.5 - 6.0 VSS 0.25VDD Output disable 4.5 - 6.0 VSS Output disable 4.5 - 6.0 VSS 0.8VDD -1.0 0.25VDD Output P- channel Tr. OFF 4.5 - 6.0 VP 0.2VDD 4.5 - 6.0 0.98 400 tCYC +1.0 V V µs (Continue) No.6750-11/21 LC86E6560 Parameter Oscillation frequency range (Note 1) Oscillation stabilizing time period (Note 1) (Note 1) Symbol Pins FmCF(1) CF1, CF2 FmCF(2) CF1, CF2 FmRC FsXtal XT1, XT2 tmsCF(1) CF1, CF2 tmsCF(2) CF1, CF2 tssXtal XT1, XT2 Conditions 6MHz (ceramic resonator oscillation) Refer to figure 1 3MHz (ceramic resonator oscillation) Refer to figure 1 RC oscillation 32.768kHz (X’tal oscillation) Refer to figure 2 6MHz (ceramic resonator oscillation) Refer to figure 3 3MHz (ceramic resonator oscillation) Refer to figure 3 32.768kHz (X’tal oscillation) Refer to figure 3 VDD[V] min. Ratings typ. 4.5 - 6.0 6 4.5 - 6.0 3 4.5 - 6.0 4.5 - 6.0 4.5 - 6.0 0.3 0.8 32.768 max. unit MHz 3.0 kHz ms 4.5 - 6.0 4.5 - 6.0 s The oscillation constant is shown on table 1. No.6750-12/21 LC86E6560 3. Electrical Characteristics at Ta=+10°C to +40°C, VSS1=VSS2=0V Parameter Input high current Input low current Output high voltage Output low voltage Pull-up MOS Tr. resistance Symbol Pins Conditions IIH(1) Ports 0, 3 of open drain output IIH(2) •Port 0 without pull-up MOS Tr. •Ports 1, 3 IIH(3) •Ports 70, 71, 72, 73 •Port 8 IIH(4) IIH(5) IIH(6) RES Ports P74 , 75 S32 to S51 without pull-down resistor •Ports 1, 3 •Port 0 without pull-up MOS Tr. •Output disable •VIN=13.5V (including the offleak current of the output Tr.) •Output disable •Pull-up MOS Tr. OFF. •VIN=VDD (including the offleak current of the output Tr.) •Output disable •VIN=VDD (including the offleak current of the output Tr.) VIN=VDD VIN=VDD •Output P-channel Tr. OFF •VIN=VDD •Output disable •Pull-up MOS Tr. OFF •VIN=VSS (including the offleak current of the output Tr.) •Output disable •VIN=VSS (including the offleak current of the output Tr.) VIN=VSS VIN=VSS IOH=-1.0mA IOH=-0.1mA IOH=-20mA •IOH=-1mA •The current of any unmeasurement pin is not over 1 mA. IOH=-5mA The current of any unmeasurement pin is not over 1mA. IOL=10mA IOL=1.6mA IOL=1mA IOL=1.6mA IIL(1) IIL(2) •Ports 70, 71, 72, 73 •Port 8 IIL(3) IIL(4) VOH(1) VOH(2) VOH(3) VOH(4) RES Ports P74 , 75 Ports 0, 1, 3 of CMOS output S0/T0 to S15/T15 VOH(5) VOH(6) S16 to S51 VOL(1) VOL(2) VOL(3) VOL(4) Ports 0, 1, 3 Rpu Port 70 •Ports 71, 72, 73 •Ports 84, 85, 86, 87 Ports 0, 1, 3 VOH=0.9VDD VDD[V] 4.5 - 6.0 min. Ratings typ. max. 5 4.5 - 6.0 1 4.5 - 6.0 1 4.5 - 6.0 4.5 - 6.0 4.5 - 6.0 1 1 1 4.5 - 6.0 -1 4.5 - 6.0 -1 4.5 - 6.0 -1 4.5 - 6.0 -1 4.5 - 6.0 VDD-1 4.5 - 6.0 VDD-0.5 4.5 - 6.0 VDD-1.8 4.5 - 6.0 VDD-1 unit µA V 4.5 - 6.0 VDD-1.8 4.5 - 6.0 VDD-1 4.5 - 6.0 4.5 - 6.0 4.5 - 6.0 4.5 - 6.0 4.5 - 6.0 15 40 1.5 0.4 0.4 0.4 V 70 kΩ (Continue) No.6750-13/21 LC86E6560 Parameter Pins Conditions IOFF(2) S0/T0 to S6/T6, S32 to S51 without pull-down resistor Resistance of the low level hold Tr. Rinpd S16 to S51 High voltage pull-down resistor Rpd •S7/T7 to S15/T15 •S16 to S31 VP pull-down resistor Hysteresis voltage Rvppd Vp VHIS Pin capacitance CP •Port 1 •Ports 70, 71, 72, 73, 75 • RES All pins •Output P-ch Tr. OFF •VOUT=VSS •Output P-ch Tr. OFF •VOUT=VDD-40V •Output P-ch Tr. OFF •Using as input ports •Output P-ch Tr. OFF •VOUT=3V •Vp=-30V •VSS=GND •Vp=-30V Output disable Output offleakage current Symbol IOFF(1) •f=1MHz Unmeasurement terminals for input are set to VSS level. •Ta=25°C VDD[V] 4.5 - 6.0 min. -1 4.5 - 6.0 -30 4.5 - 6.0 Ratings typ. max. unit µA 200 kΩ 5.0 60 100 200 5.0 60 100 200 4.5 - 6.0 0.1VDD V 4.5 - 6.0 10 pF Serial output Serial input Symbol Cycle Low Level pulse width High Level pulse width Cycle Low Level pulse width High Level pulse width Data set up time tCKCY(1) tCKL(1) Data hold time tCKI Output delay time (Serial clock is external clock) Output delay time (Serial clock is internal clock) tCKO(1) Input clock Parameter Output clock Serial clock 4. Serial Input/Output Characteristics at Ta=+10°C to +40°C, VSS1=VSS2=0V Pins •SCK0 •SCK1 Conditions Refer to figure 5. VDD[V] 4.5 - 6.0 tCKH(1) tCKCY(2) tCKL(2) tCKO(2) Ratings typ. max. unit tCYC 1 •SCK0 •SCK1 tCKH(2) tICK min. 2 1 •SI0, SI1 •SB0, SB1 •SO0, SO1 •SB0, SB1 •Use pull-up resistor (1kΩ) when open drain output. •Refer to figure 5. •Data set-up to SCK0, 1. •Data hold from SCK0, 1. •Refer to figure 5. 4.5 - 6.0 •Use pull-up resistor (1kΩ) when open drain output. •Data hold from SCK0, 1. •Refer to figure 5. 4.5 - 6.0 7/12tCYC +0.2 4.5 - 6.0 1/3tCYC +0.2 2 1/2tCKCY 1/2tCKCY 4.5 - 6.0 µs 0.1 0.1 No.6750-14/21 LC86E6560 5. Pulse Input Conditions at Ta=+10°C to +40°C, VSS1=VSS2=0V Parameter Symbol High/low level pulse width tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) Pins •INT0, INT1 •INT2/T0IN INT3/T0IN (The noise rejection clock is selected to 1/1.) INT3/T0IN (The noise rejection clock is selected to 1/16.) INT3/T0IN (The noise rejection clock is selected to 1/64.) RES Conditions VDD[V] 4.5 - 6.0 min. 1 4.5 - 6.0 2 •Interrupt acceptable •Timer0-countable 4.5 - 6.0 32 •Interrupt acceptable •Timer0-countable 4.5 - 6.0 128 Reset acceptable 4.5 - 6.0 200 •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable Ratings typ. max. unit tCYC µs 6. AD Converter Characteristics at Ta=+10°C to +40°C, VSS1=VSS2=0V Parameter Resolution Absolute precision (Note 2) Conversion time Analog input voltage range Analog port input current Symbol Pins Conditions N ET tCAD VAIN IAINH IAINL AD conversion time =16×tCYC (ADCR2=0) (Note 3) AD conversion time =32×tCYC (ADCR2=1) (Note 3) AN0 - AN7 VAIN=VDD VAIN=VSS VDD[V] 4.5 - 6.0 4.5 - 6.0 4.5 - 6.0 min. Ratings typ. 8 max. unit ±1.5 bit LSB 15.68 65.28 µs (tCYC= 0.98µs) (tCYC= 4.08µs) 31.36 130.56 (tCYC= 0.98µs) (tCYC= 4.08µs) 4.5 - 6.0 VSS VDD V 4.5 - 6.0 4.5 - 6.0 1 µA -1 4.5 - 6.0 (Note 2) Absolute precision does not include quantizing error (±1/2LSB). (Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital conversion value to the register. No.6750-15/21 LC86E6560 7. Current Dissipation Characteristics at Ta=+10°C to +40°C, VSS1=VSS2=0V Parameter Current dissipation during basic operation (Note 4) Symbol IDDOP(1) IDDOP(2) IDDOP(3) IDDOP(4) Pins Conditions •FmCF=6MHz Ceramic resonator oscillation •Internal RC oscillation stops •FmX’tal=32.768kHz X’tal oscillation •System clock : CF oscillation •1/1 divided •FmCF=3MHz Ceramic resonator oscillation •Internal RC oscillation stops •FmX’tal=32.768kHz X’tal oscillation •System clock : CF oscillation •1/2 divided •FmCF=0Hz (When oscillation stops.) •FmX’tal=32.768kHz X’tal oscillation •System clock : RC oscillation •1/2 divided •FmCF=0Hz (When oscillation stops.) •FmX’tal=32.768kHz X’tal oscillation •System clock : X’tal oscillation •Internal RC oscillation stops. •1/2 divided Ratings typ. 14 max. 33 4.5 - 6.0 6 18 4.5 - 6.0 4 13 4.5 - 6.0 3 10 VDD[V] 4.5 - 6.0 min. unit mA (Continue) No.6750-16/21 LC86E6560 Parameter Symbol Current dissipation in HALT mode (Note 4) IDDHALT(1) IDDHALT(2) IDDHALT(3) IDDHALT(4) Current dissipation in HOLD mode (Note 4) (Note 4) IDDHOLD(1) Pins Conditions •HALT mode •FmCF=6MHz Ceramic resonator oscillation •Internal RC oscillation stops •FmX’tal=32.768kHz X’tal oscillation •System clock : CF oscillation •1/1 divided •HALT mode •FmCF=3MHz Ceramic resonator oscillation •Internal RC oscillation stops •FmX’tal=32.768kHz X’tal oscillation •System clock : CF oscillation •1/2 divided •HALT mode •FmCF=0Hz (When oscillation stops.) •FmX’tal=32.768kHz X’tal oscillation •System clock : RC oscillation •1/2 divided •HALT mode •FmCF=0Hz (When oscillation stops.) •FmX’tal=32.768kHz X’tal oscillation •System clock : X’tal oscillation •Internal RC oscillation stops. •1/2 divided HOLD mode Ratings typ. 5 max. 14 4.5 - 6.0 2.2 7 mA 4.5 - 6.0 400 1600 µA 4.5 - 6.0 25 100 4.5 - 6.0 0.05 30 VDD[V] 4.5 - 6.0 min. unit mA µA The currents of output transistors and pull-up MOS transistors are ignored. No.6750-17/21 LC86E6560 Table 1. Ceramic resonator oscillation recommended constant (main clock) Oscillation type 6MHz ceramic resonator oscillation 3MHz ceramic resonator oscillation Maker Murata Kyocera Murata Kyocera Oscillator C1 C2 TBD * Both C1 and C2 must use K rank (±10%) and SL characteristics. Table 2. Crystal oscillation recommended constant (sub clock) Oscillation type 32.768kHz crytal oscillation Maker Oscillator C3 C4 Rd Rf * Both C3 and C4 must be a J rank (±5%) and CH characteristics. (K rank (±10%), SL characteristics parts can be used for the applications which do not require oscillation accuracy.) (Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. •If you use other oscillators herein, we provide no guarantee for the characteristics. CF1 CF2 XT1 XT2 Rf Rd CF C1 C2 Figure 1 Ceramic oscillation circuit C3 Figure 2 X’tal C4 Crystal oscillation circuit No.6750-18/21 LC86E6560 VDD VDD limit 0V Power supply Reset time RES Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode Unfixed Reset Instruction execution mode OCR6=1 Instruction execution mode <Reset time and oscillation stable time> HOLD release signal Valid Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode HOLD Instruction execution mode <HOLD release signal and oscillation stable time> Figure 3 Oscillation stabilizing time No.6750-19/21 LC86E6560 VDD RRES (Note) Fix the value of CRES, RRES that is sure to reset until 200µs, after Power supply has been over inferior limit of supply voltage. RES CRES Figure 4 Reset circuit 0.5VDD <AC timing point> VDD tCKCY tCKL tCKH SCK0 SCK1 1kΩ tICK tCKI SI0 SI1 tCKO 50pF SO0, SO1 SB0, SB1 <Timing> Figure 5 tPIL Figure 6 <Test load> Serial input / output test condition tPIH Pulse input timing condition No.6750-20/21 LC86E6560 PS No.6750-21/21