It 8 BIT SINGLE CHIP MICROCONTROLLER LC87F57C8A Preliminary LC87F57C8A 8-Bit Single Chip Microcontroller incorporating 128K-byte FEPROM and 3K-byte RAM on chip. Overview The LC87F57C8A is 8-bit single chip microcontroller with the following one-chip features: - CPU : Operable at a minimum bus cycle time of 100ns - On-chip Flash ROM Capacity : 128K bytes (on-board rewritable) - On-chip RAM Capacity : 3K bytes - two high performance 16-bit timer/counters (can be divided into 8 bit timers) - four 8-bit timers with prescalers - timer for use as date/time clock - one synchronous serial I/O port (with automatic block transmit/receive function) - one asynchronous/synchronous serial I/O port - 12-bit PWM × 2 - 12-channel × 8-bit AD converter - high speed 8-bit parallel interface - high speed clock counter - system clock divider - 20-source 10-vectored interrupt system Features (1) Read Only Memory (Flash ROM) - single 5V power supply, on-board writeable - block erase in 128 byte units - 131072 × 8 bits (LC87F57C8A) (2) Bus Cycle Time - 100ns (10MHz) Note: Bus cycle time indicates the speed to read ROM. ♦ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ♦ Anyone purchasing any products described or contained herein for an above-mentioned use shall: 1) Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: 2) Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ♦ Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This product incorporates technology licensed from Silicon Storage Technology Inc. This catalog provides information as of Feb 2002. Specifications and information herein are subject to change without notice. SANYO Electric Co., Ltd. Semiconductor Company. System-Business Div. 1-1-1, Sakata Oizumi-Machi, Gunma, JAPAN Ver.1.00 Apr 03 Microcomputer Business Unit T.Kitamura 1/27 LC87F57C8A (3) Minimum Instruction Cycle Time : 300ns (10MHz) (4) Ports - Input/output ports Input/output programmable for each bit individually Data direction programmable in nibble units - Input ports - PWM output ports - Oscillator pins - Reset pin - Power supply 43 (P1n, P2n, P70 to P73, P8n, PAn, PBn, PCn) 8 (P0n) 2 (XT1, XT2) 2 (PWM0, PWM1) 2 (CF1, CF2) 1 (RES) 6 (VSS1 to 3, VDD1 to 3) (5) Timer - Timer 0 : 16-bit timer/counter with capture register Mode 0: Two 8-bit timers with programmable 8-bit prescaler and 8-bit capture register Mode 1: 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit counter with 8-bit capture register Mode 2: 16-bit timer with 8-bit programmable prescaler and 16-bit capture register Mode 3: 16-bit counter with 16-bit capture register - Timer 1 : PWM/16-bit timer/counter with toggle output Mode 0: 8-bit timer (with toggle output) + 8-bit timer/counter (with toggle output) Mode 1: Two 8-bit PWM Mode 2: 16-bit timer/counter (with toggle output) Toggle output is also possible by using the lower order 8 bits. Mode 3: 16 bit timer (with toggle output) The lower order 8 bits can be used as PWM output. - Timer 4: - Timer 5: - Timer 6: - Timer 7: 8-bit timer with 6-bit prescaler 8-bit timer with 6-bit prescaler 8-bit timer with 6-bit prescaler 8-bit timer with 6-bit prescaler - Base timer 1. Clock for the base timer is selectable from sub-clock (32.768kHz crystal oscillation), system clock or programmable prescaler output of timer 0. 2. There can be five separate interrupt sources. (6) High speed clock counter 1. Maximum of 20MHz possible (when using a 10MHz main clock). 2. Real-time output (7) Serial interface - SIO 0: 8 bit synchronous serial interface 1. LSB first/MSB first-function available 2. An internal 8-bit baud-rate generator (maximum transmit clock period 4/3 TCYC) 3. Consecutive automatic data communication (1 - 256 bits) - SIO 1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 - 512 TCYC) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud-rate 8 - 2048 TCYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 TCYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) 2/27 Ver.1.00 LC87F57C8A (8) AD converter - 12-channel × 8-bit AD converter (9) PWM - 2 channel × synchronous variable 12 bit PWM (10) Parallel interface - RS, RD , WR , CS0 outputs (polarity can be toggled) - read/write possible in 1 TCYC (11) Remote receiver circuit (share with P73/INT3/T0IN terminal) - Noise rejection function (The filtering time of the noise rejection filter (1TCYC/32 TCYC/128 TCYC) can be switched by program.) (12) Watchdog timer - External RC circuit is required. - Interrupt or system reset is activated when the timer overflows. (13) Interrupts - 20-source and 10-vectored interrupt function: 1. Three interrupt priorities, low (L), high (H) and highest (X) are supported with multi-level nesting possible. During interrupt handling, an equal or lower level interrupt request is refused. 2. If interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. Vector Selectable Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L Interrupt signal 1 00003H INT0 2 0000BH INT1 3 00013H INT2/T0L/INT4 4 0001BH INT3/INT5/Base timer 5 00023H T0H 6 0002BH T1L/T1H 7 00033H SIO0 8 0003BH SIO1 9 00043H ADC/T6/T7 10 0004BH Port 0/T4/T5/PWM0, PWM1 • Priority Level: X > H > L • For equal priority levels, vector with lowest address takes precedence. (14) Subroutine stack levels - A maximum of 1536 levels (set stack inside RAM) (15) Multiplication and division - 16 bits × 8 bits (5 instruction-cycle times) - 24 bits × 16 bits (12 instruction-cycle times) - 16 bits ÷ 8 bits (8 instruction-cycle times) - 24 bits ÷ 16 bits (12 instruction-cycle times) (16) Oscillation circuits - Built-in RC oscillation circuit used for the system clock - CF oscillation circuit used for the system clock - Crystal oscillation circuit used for the system clock - Built-in frequency variable RC oscillation circuit used for the system clock (17) System clock divider - operable on the lowest power consumption - Minimum instruction cycle time (300ns, 600ns, 1.2µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be switched by program (when using 10MHz main clock) Ver.1.00 3/27 LC87F57C8A 4/27 Ver.1.00 LC87F57C8A (18) Standby function - HALT mode The HALT mode stops program execution while the peripheral circuits keep operating and minimizes power consumption. This operation mode can be released by a system reset or an interrupt request. - HOLD mode The HOLD mode stops program execution and all oscillation circuits: CF, RC and Crystal oscillations. This mode can be released by the following conditions. 1. Supply "L" level to the reset terminal (RES) 2. Supply the selected level to at lease one of INT0, INT1, INT2, INT4 INT5. 3. Supply an interrupt condition to Port 0. - X’tal HOLD mode The X’tal HOLD mode stops program execution and all peripheral circuits except for the base timer. The crystal oscillator maintains its state at HOLD mode inception. This mode can be released by the following conditions. 1. Supply "L" level to the reset terminal (RES). 2. Supply the selected level to at least one of INT0, INT1, INT2, INT4, INT5 3. Supply an interrupt condition to Port 0. 4. Supply an interrupt condition to the base timer circuit. (19) Shipping form - QIP64E - SQFP64 (20) Development tools - Evaluation (EVA) chip : LC876093 - Emulator : EVA62S + ECB876600A + SUB875700 + POD64QFP or POD64SQFP - Flash ROM writer adapter :W87F50256Q(QIP64E),W87F57256SQ(SQFP64) Ver.1.00 5/27 LC87F57C8A PB1/D1 PB0/D0 VSS3 VDD3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PA2/CS0# PA3/WR# PA4/RD# PA5/RS Pin Assignment 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P70/INT0/T0LCP/AN8 49 32 PB2/D2 P71/INT1/T0HCP/AN9 50 31 PB3/D3 P72/INT2/T0IN 51 30 PB4/D4 P73/INT3/T0IN 52 29 PB5/D5 RES# 53 28 PB6/D6 XT1/AN10 54 27 PB7/D7 XT2/AN11 55 26 P27/INT5/T1IN VSS1 56 25 P26/INT5/T1IN CF1 57 24 P25/INT5/T1IN CF2 58 23 P24/INT5/T1IN VDD1 59 22 P23/INT4/T1IN P80/AN0 60 21 P22/INT4/T1IN P81/AN1 61 20 P21/INT4/T1IN P82/AN2 62 19 P20/INT4/T1IN P10/SO0 63 18 P07/AN7 P11/SI0/SB0 64 17 P06/AN6 6/27 P05/AN5 P04/AN4 P03/AN3 VDD2 10 11 12 13 14 15 16 P02 9 P01 8 P00 7 VSS2 6 PWM0 P14/SI1/SB1 5 PWM1 P13/SO1 4 P17/T1PWMH/BUZ 3 P15/SCK1 2 P16/T1PWML 1 P12/SCK0 LC87F5700A QIP64E SQFP64 Ver.1.00 LC87F57C8A QIP /SQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Ver.1.00 NAME P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PWM1 PWM0 VDD2 VSS2 P00 P01 P02 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P20/INT4/T1IN P21/INT4/T1IN P22/INT4/T1IN P23/INT4/T1IN P24/INT5/T1IN P25/INT5/T1IN P26/INT5/T1IN P27/INT5/T1IN PB7/D7 PB6/D6 PB5/D5 PB4/D4 PB3/D3 PB2/D2 QIP /SQFP 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME PB1/D1 PB0/D0 VSS3 VDD3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PA2/CS0# PA3/WR# PA4/RD# PA5/RS P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P73/INT3/T0IN RES# XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P10/SO0 P11/SI0/SB0 7/27 LC87F57C8A System Block Diagram IR Interrupt Control PLA Flash ROM Standby Control RC Xtal Clock Generator CF PC MRC SIO0 Bus Interface ACC SIO1 Port 0 B Register Timer 0 Port 1 C Register Timer 1 Port 7 ALU Timer 4 Port 8 Timer 5 ADC PWM0 INT0-3 Noise Rejection Filter PWM1 Base Timer Timer 6 Port 2 INT4,,5 Parallel interface Port A Port B Port C PSW RAR RAM Stack Pointer Watch Dog Timer Timer 7 8/27 Ver.1.00 LC87F57C8A Pin Description Name VSS1, VSS2 VSS3 VDD1, VDD2 VDD3 Port 0 P00 - P07 I/O - Power terminal (-) Option No - Power terminal (+) No • 8-bit input/output port • Data direction programmable in nibble units • Pull-up resistor provided/not provided (specified in nibble units) • HOLD release input • Port 0 interrupt input • AD converter input port : AN3 (P03)- AN7 (P07) •8-bit input/output port • Data direction programmable for each bit individually • Pull-up resistor provided/not provided (specified by bit) • Other functions P10: SIO0 data output P11: SIO0 data input, bus input/output P12: SIO0 clock input/output P13: SIO1 data output P14: SIO1 data input, bus input/output P15: SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output • 8-bit input/output port • Data direction programmable for each bit individually • Pull-up resistor provided/not provided (specified by bit) • Other functions P20-P23: INT4 input/HOLD release input/Timer 1 event input/Timer 0L capture input/Timer 0H capture input P24-P27: NT5 input/HOLD release input/Timer 1 event input/Timer 0L capture input/Timer 0H capture input Yes I/O Port 1 P10 - P17 I/O Port 2 P20 - P27 I/O Function description • Interrupt detection style Rising INT4 INT5 Port 7 P70 - P73 I/O enable enable Falling enable enable Rising/ falling enable enable H level L level disable disable disable disable • 4-bit input/output port • Data direction programmable for each bit individually • Pull-up resistor provided/not provided (specified by bit) • Other functions P70: INT0 input/HOLD release input/Timer 0L capture input/Output for watchdog timer P71: INT1 input/HOLD release input/Timer 0H capture input P72: INT2 input/HOLD release input/Timer 0 event input/Timer0L capture input P73: INT3 input with noise filter/Timer 0 event input/Timer 0H capture input • Interrupt detection style Rising Falling INT0 INT1 INT2 INT3 enable enable enable enable enable enable enable enable Rising/ falling disable disable enable enable H level L level enable enable disable disable enable enable disable disable Yes Yes No • AD converter input port : AN8 (P70), AN9 (P71) (Continued) Ver.1.00 9/27 LC87F57C8A Name I/O Port 8 P80 - P82 I/O Port A PA2 - PA5 I/O Function description • 3-bit input/output port • Data direction programmable for each bit individually • Other functions P80-P82 : AD converter input port • 4-bit input/output port • Data direction programmable for each bit individually • Pull-up resistor provided/not provided (specified by bit) • Other functions PA2: Parallel interface output CS0 Option No Yes PA3: Parallel interface output WR Port B PB0 - PB7 I/O Port C PC0 - PC7 I/O PWM0 PWM1 RES O O I XT1 I XT2 I/O CF1 CF2 I O 10/27 PA4: Parallel interface output RD PA5: Parallel interface output RS • 8-bit input/output port • Data direction programmable for each bit individually • Pull-up resistor provided/not provided (specified by bit) • Other functions PB0-PB7 : Parallel interface data input/output, address output • 8-bit input/output port • Data direction programmable for each bit individually • Pull-up resistor provided/not provided (specified by bit) • Other functions PC0-PC7 : Parallel interface address output PWM0 output port PWM1 output port Reset terminal • Input terminal for 32.768kHz X'tal oscillation • Other function AN10 : AD converter input port General input port When not in use, connect terminal to VDD1. • Output terminal for 32.768kHz X'tal oscillation • Other function AN11 : AD converter input port General input port When not in use, set as oscillation and leave terminal open Input terminal for ceramic resonator Output terminal for ceramic resonator Yes Yes No No No No No No No Ver.1.00 LC87F57C8A Port Output Configuration Output configuration and pull-up resistor options are shown in the following table. Input is possible even when a port is in output mode. Terminal Option applies to: Option P00 - P07 each bit P10 - P17 P20 - P27 each bit PA2 - PA5 PB0 - PB7(*) PC0 - PC7 P70 P71 - P73 P80 - P82 PWM0, PWM1 XT1 XT2 each bit 1 2 1 2 1 2 - None None None None None None Output Format Pull-up resistor CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Programmable (Note 1) None Programmable Programmable Programmable Programmable Nch-open drain CMOS Nch-open drain CMOS Input only Output for 32.768kHz crystal oscillation Programmable Programmable None None None None Note 1 Programmable pull-up resistor of Port 0 is specified in nibble units (P00 - P03, P04 - P07). (*) When in parallel interface mode, PB0 - PB7 output format is CMOS, regardless of any selected option. Note: To reduce VDD signal noise and to increase the duration of the backup battery supply, VSS1, VSS2, and VSS3 should connect to each other and they should also be grounded. Example 1 : During backup in hold mode, port output ‘H’ level is supplied from the back-up capacitor. LSI Power Supply Back-up capacitor VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 Ver.1.00 11/27 LC87F57C8A Example 2 : During backup in hold mode, output is not held high and its value in unsettled. LSI Power Supply Back-up capacitor VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 12/27 Ver.1.00 LC87F57C8A 1. Absolute maximum ratings / Ta=25°C, VSS1=VSS2=VSS3=0V Parameter Symbol Supply voltage VDDMAX Input voltage Output voltage Input/Output voltage VI(1) VO(1) VIO(1) High level output current Peak output current Total output current Low level output current Peak output current Total output current Maximum power consumption Operating temperature range Storage temperature range Ver.1.00 IOPH(1) IOPH(2) ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) ΣIOAH(4) ΣIOAH(5) IOPL(1) IOPL(2) IOPL(3) ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) ΣIOAL(4) ΣIOAL(5) ΣIOAL(6) Pdmax Pins VDD1, VDD2, VDD3 XT1, XT2, CF1 PWM0, PWM1 • Ports 0, 1, 2 • Ports 7, 8 • Ports A, B, C • PWM0, PWM1 • Ports 0, 1, 2 • Ports A, B, C • PWM0, PWM1 P71-P73 P71-P73 • Port 1 • PWM0, PWM1 Port 0 Ports B,2 Ports A, C • P02-P07 • Ports 1, 2 • Ports A, B, C • PWM0, PWM1 P00, P01 Ports 7, 8 Port 7 Port 8 • Port 1 • PWM0, PWM1 Port 0 Ports B,2 Ports A, C QIP64E SQFP64 Conditions VDD1=VDD2 =VDD3 VDD[V] Limits min. typ. -0.3 -0.3 -0.3 -0.3 • CMOS output • For each pin. -10 For each pin. Total of all pins Total of all pins -5 -5 -30 Total of all pins Total of all pins Total of all pins For each pin. -20 -20 -20 max. +6.5 unit V VDD+0.3 VDD+0.3 VDD+0.3 mA 20 For each pin. For each pin. Total of all pins Total of all pins Total of all pins 30 5 15 15 50 Total of all pins Total of all pins Total of all pins Ta= -20 to +70°C Topg -20 70 40 40 429 271 70 Tstg -55 125 mW °C 13/27 LC87F57C8A 2. Recommended operating range / Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Symbol Operating supply voltage range VDD(1) HOLD voltage VHD Input high voltage VIH(1) VIH(2) VIH(3) VIH(4) Input low voltage VIL(1) VIL(2) VIL(5) VIL(6) Operation cycle time tCYC External system clock frequency FEXCF(1) 14/27 Pins VDD1=VDD2 =VDD3 VDD1=VDD2 =VDD3 • Ports 1, 2 • P71-P73 • P70 port input /interrupt • Ports 0, 8 • Ports A, B, C Port 70 Watchdog timer XT1, XT2, CF1, RES • Ports 1, 2 • P71-P73 • P70 port input /interrupt • Ports 0, 8 • Ports A, B, C Port 70 Watchdog Timer XT1, XT2, CF1, RES CF1 Conditions VDD[V] 0.294µs ≤ tCYC ≤ 200µs 0.588µs ≤ tCYC ≤ 200µs Except for on-board rewriting RAM and register data are kept in HOLD mode. Except for on-board rewriting • Leave CF2 pin open • System clock divider set to 1/1 • External clock DUTY=50±5% • Leave CF2 pin open • System clock divider set to 1/1 • External clock DUTY=50±5% • Leave CF2 pin open • System clock divider set to 1/2 • Leave CF2 pin open • System clock divider set to 1/2 Limits min. 4.5 typ. max. 5.5 2.5 5.5 2.0 5.5 2.5 - 5.5 0.3VDD +0.7 VDD 2.5 - 5.5 0.3VDD +0.7 VDD 2.5 - 5.5 0.9VDD VDD 2.5 - 5.5 0.75VDD VDD unit V 2.5 - 5.5 VSS 0.1VDD +0.4 2.5 - 5.5 VSS 0.15VDD +0.4 2.5 - 5.5 VSS 0.8VDD -1.0 2.5 - 5.5 VSS 0.25VDD 4.5 - 5.5 2.5 - 5.5 0.294 0.588 200 200 µs 4.5 - 5.5 0.1 10 MHz 2.5 - 5.5 0.1 5 4.5 - 5.5 0.2 20.4 2.5 - 5.5 0.1 10 Ver.1.00 LC87F57C8A Parameter Symbol Pins Oscillation frequency FmCF(1) CF1, CF2 Range FmCF(2) CF1, CF2 (Note1) FmRC FmMRC FsX’tal XT1, XT2 Conditions 10MHz ceramic resonator oscillation Refer to figure 1 5MHz ceramic resonator oscillation Refer to figure 1 RC oscillation Frequency variable RC oscillation source oscillation 32.768kHz crystal resonator oscillation Refer to figure 2 VDD[V] 4.5- 5.5 min. 2.5 - 5.5 2.5 - 5.5 2.5 - 5.5 2.5 - 5.5 Limits typ. max 10 unit MHz 5 0.3 1.0 50 32.7 68 2.0 kHz (Note 1) The oscillation parameters are shown on Tables 1 and 2. (Note 2) VDD∞4.5V is required for on-board flash ROM rewriting. Ver.1.00 15/27 LC87F57C8A 3. Electrical characteristics / Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Input high current Input low current Output high voltage Output low voltage Symbol IIH(1) Pins IIH(2) • Ports 0, 1, 2 • Ports 7, 8 • Ports A, B, C • RES • PWM0, PWM1 XT1, XT2 IIH(3) CF1 IIL(1) IIL(2) • Ports 0, 1, 2 • Ports 7, 8 • Ports A, B, C • RES • PWM0, PWM1 XT1, XT2 IIL(3) CF1 VOH(1) • Ports 0, 1, 2 • Ports B, C • PWM0, PWM1 Port A VOH(2) VOH(3) VOH(4) VOH(5) VOL(1) VOL(2) P71-P73 • Ports 0, 1, 2 • Ports B, C • PWM0, PWM1 VOL(3) Conditions • Output disable • Pull-up resistor OFF • VIN=VDD (including the off-leak current of the output Tr.) • Using as an input port • VIN=VDD VIN=VDD VDD[V] 2.5 - 5.5 Limits min. typ. max. 1 2.5 - 5.5 1 2.5 - 5.5 15 • Output disable • Pull-up resistor OFF • VIN=VSS (including the off-leak current of the output Tr.) • Using as an input port • VIN=VSS VIN=VSS 2.5 - 5.5 -1 2.5 - 5.5 -1 2.5 - 5.5 -15 IOH=-1.0mA 4.5 - 5.5 VDD-1 IOH=-0.1mA IOH=-5.0mA IOH=-0.4mA IOH=-0.4mA IOL=10mA 2.5 - 5.5 4.5 - 5.5 2.5 - 5.5 4.5 - 5.5 4.5 - 5.5 VDD-0.5 IOL=1.6mA 4.5 - 5.5 0.4 IOL=1mA 2.5 - 5.5 0.4 unit µA V VDD-1 VDD-0.5 VDD-1 1.5 VOL(4) P00, P01 IOL=30mA 4.5 - 5.5 1.5 VOL(5) Ports 7, 8 IOL=1mA 2.5 - 5.5 0.4 Port A IOL=15mA 4.5 - 5.5 1.5 IOL=2mA 2.5 - 5.5 0.4 VOH=0.9VDD 2.5 - 5.5 V VOL(6) VOL(7) VOL(8) Pull-up resistor Rpu • Ports 0, 1, 2 • Port 7 • Ports A, B, C Hysteresis voltage VHIS Pin capacitance CP • RES • Port 1 • Port 2 • Port 7 All pins 16/27 • All pins except the measured terminal : VIN=VSS • f=1MHz • Ta=25°C 15 40 70 kΩ 2.5 - 5.5 0.1VDD V 2.5 - 5.5 10 pF Ver.1.00 LC87F57C8A 4. Serial input/output characteristics / Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Serial clock Input clock Parameter Symbol Pins Low level pulse width tSCKL(1) 1 tSCKLA(1) 1 tSCKH(1) 1 tSCKHA(1) SCK1(P15) Output clock Refer to figure 6 2.5 - 5.5 Cycle tSCK(2) Low level pulse width High level pulse width Cycle tSCKL(2) 1 tSCKH(2) 1 tSCK(3) High level pulse width typ. SCK0(P12), • CMOS output • Refer to figure 6 2.5 - 5.5 4/3 tSCK 1/2 SCK0(P12) SIO0 3/4 tSCKH(3) 1/2 tSCKHA(2) SCK0(P12) SIO0 • CMOS output • Refer to figure 6 2 Cycle tSCK(4) Low level pulse width High level pulse width Data set-up time tSCKL(4) 1/2 tSCKH(4) 1/2 Data hold time thDI Output delay time tdD0 Ver.1.00 unit tCYC 2 tSCKL(3) tsDI max. 3(SIO0) tSCKLA(2) Serial input Limits min. 2 tSCK(1) Low level pulse width Serial output Refer to figure 6 VDD[V] 2.5 - 5.5 Cycle High level pulse width SCK0(P12) Conditions SCK1(P15) SB0(P11), SB1(P14), SI0 SI1 SO0(P10), SO1(P13), SB0(P11), SB1(P14), • Data set-up to SI0CLK • Data hold from SI0CLK • Refer to figure 6 • Data hold from SI0CLK • Time delay from SI0CLK trailing edge to the SO data change in the open drain • Refer to figure 6 2.5 - 5.5 2.5 - 5.5 2 tCYC tSCK 0.03 µs 0.03 2.5 - 5.5 1/3tCYC +0.05 17/27 LC87F57C8A 5. Parallel Input/Output Characteristics / Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Note: If Port A terminals will be used as RS, WR , RD or CS , then it should be set to CMOS format by option data. Refer to figures 8 and 9 for parallel output timing. Parameter Symbol Pins Conditions tsA(2) • WR (PA3), PB0-PB7 • RD (PA4), PC0-PC7 RD (PA4), PC0-PC7 From address set-up until control signal changes thA(1) RD (PA4), PC0-PC7 thA(2) WR (PA3), PC0-PC7 From change of RD 2.5 - 5.5 until address change From change of WR 2.5 - 5.5 until address change From change of RS, 2.5 - 5.5 CS until change in Write cycle, tC(1) Read cycle Address set-up tsA(1) time Address hold time RS set-up time tsRS(1) WR (PA3), RS(PA5), CS (PAX) VDD[V] 2.5 - 5.5 Limits min. 2.5 - 5.5 1/3tCYC -30ns 2.5 - 5.5 2/3tCYC -30ns 1/6tCYC typ. 1 max. unit tCYC tCYC & ns 5 ns 1/6tCYC -15ns tCYC & ns WR CS tsRS(2) RD (PA4), RS(PA5) tsRS(3) RD (PA4), RS(PA5) tsCS(1) RD (PA4), CS (PAX) set-up time tsCS(2) RS hold time 2.5 - 5.5 2.5 - 5.5 From change in until change in WR (PA3), CS (PAX) From change in until change in CS 2.5 - 5.5 RD CS 2.5 - 5.5 WR 1/6tCYC -15ns 1/3tCYC -15ns 1/3tCYC -15ns 2/3tCYC -15ns CS (PAX) From change in WR 2.5 - 5.5 until change in RS From change in RD 2.5 - 5.5 until change in RS, RD (PA4), RS(PA5), CS 2.5 - 5.5 0 ns 2.5 - 5.5 1/6tCYC tCYC & ns 0 ns thRS(1) WR (PA3), RS(PA5) thRS(2) RD (PA4), RS(PA5), thRS(3) from change of RS until change in RD 0 ns 1/6tCYC tCYC & ns CS (PAX) CS thCS(1) RD (PA4), RS(PA5) From change in RD until change in CS thCS(2) WR (PA3), RS(PA5) tWRH(1) WR (PA3) From change in WR 2.5 - 5.5 until change in CS 2.5 - 5.5 tWRH(2) WR (PA3) 2.5 - 5.5 tWRL(1) WR (PA3) 2.5 - 5.5 tWRL(2) WR (PA3) 2.5 - 5.5 hold time WR ’H’ pulse width WR ’L’ pulse width 1/6tCYC -5ns 2/3tCYC -5ns 1/6tCYC -5ns 1/3tCYC -5ns 1/6 tCYC 2/3 tCYC 1/6 tCYC 1/3 tCYC tCYC & ns (Continued) 18/27 Ver.1.00 LC87F57C8A Parameter RD Symbol Pins tRDH(1) RD (PA4) tRDH(2) RD (PA4) tRDL(1) RD (PA4) tRDL(2) RD (PA4) Conditions ’H’ pulse width RD ’L’ pulse width Data write tdDT(1) maximum delay tdDT(2) RD (PA4), PB0-PB7 The time delay RD (PA4), PB0-PB7 Input data set-up time tsDTR(1) RD (PA4), PB0-PB7 Input data hold time thDTR(1) RD (PA4), PB0-PB7 Output data set-up time tsDTW(1) RD (PA4), PB0-PB7 tsDTW(2) RD (PA4), PB0-PB7 Output data hold time allowed, from RD leading edge until input data set-up (Note 1) From input data setup to RD leading edge. (Note 2) From RD leading edge until input data hold From output data setup until WR leading edge Limits VDD[V] min. 2.5 - 5.5 1/6tCYC -5ns 2.5 - 5.5 1/3tCYC -5ns 2.5 - 5.5 1/3tCYC -5ns 2.5 - 5.5 1/2tCYC -5ns 2.5 - 5.5 typ. 1/6 tCYC 1/3 tCYC 1/3 tCYC 1/2 tCYC max. unit tCYC & ns 1/6tCYC -15ns 2.5 - 5.5 1/3tCYC -15ns 2.5 - 5.5 40 ns 2.5 - 5.5 0 ns 2.5 - 5.5 1/3tCYC -30ns 2.5 - 5.5 1/3tCYC -30ns 2.5 - 5.5 0 thDTW(1) RD (PA4), PB0-PB7 From WR leading edge until output data 2.5 - 5.5 thDTW(2) hold tCYC & ns ns 0 Note 1 : Time until incorrect data of Low disappears. Note 2 : Incorrect data of Low is not output in the period between tRDL(1) - tdDT(1). 6. Pulse input conditions / Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Symbol Pins Conditions High/low level pulse width tPIH(1) tPIL(1) INT0(P70), INT1(P71), INT2(P72) INT4(P20-P23) INT5(P24-P27) INT3(P73) (The noise rejection clock is selected to 1/1.) INT3(P73) (The noise rejection clock is selected to 1/32.) • Interrupt acceptable • Timer 0 and 1 event input acceptable tPIH(2) tPIL(2) tPIH(3) tPIL(3) Ver.1.00 tPIH(4) tPIL(4) INT3(P73) (The noise rejection clock is selected to 1/128.) tPIL(5) RES • Interrupt acceptable • Timer 0 event input acceptable • Interrupt acceptable • Timer 0 event input acceptable • Interrupt acceptable • Timer 0 event input acceptable Reset acceptable VDD[V ] 2.5 - 5.5 Limits min. typ. 1 2.5 - 5.5 2 2.5 - 5.5 64 2.5 - 5.5 256 2.5 - 5.5 200 max. unit tCYC µs 19/27 LC87F57C8A 7. AD converter characteristics / Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Resolution Absolute precision Conversion time Symbol N ET TCAD Pins AN0(P80) - AN2(P82) AN3(P03) - AN7(P07) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) Conditions (Note 2) AD conversion time=32 × tCYC (ADCR2=0) (Note 3) VDD[V] 3.0 - 5.5 3.0 - 5.5 4.5 - 5.5 3.0 - 5.5 AD conversion time=64 × tCYC (ADCR2=1) (Note 3) 4.5 - 5.5 VAIN IAINH IAINL VAIN=VDD VAIN=VSS 15.10 (tCYC= 0.588µs) 31.36 (tCYC= 0.980µs) typ. 8 max. ±1.5 unit bit LSB 97.92 µs (tCYC= 3.06µs) 97.92 (tCYC= 3.06µs) 18.82 97.92 (tCYC= 0.294µs) (tCYC= 1.53µs) 62.72 97.92 (tCYC= 0.980µs) (tCYC= 1.53µs) 3.0 - 5.5 VSS VDD V 3.0 - 5.5 3.0 - 5.5 1 µA -1 3.0 - 5.5 Analog input voltage range Analog port input current Limits min. (Note 2) Absolute precision excludes the quantizing error (±1/2 LSB). (Note 3) The conversion time is the time from executing the AD conversion instruction to setting the complete digital conversion value in the register. 20/27 Ver.1.00 LC87F57C8A 8. Current dissipation characteristics / Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Symbol Current drain during IDDOP(1) basic operation (Note 4) IDDOP(2) IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6) IDDOP(7) IDDOP(8) IDDOP(9) IDDOP(10) Pins Conditions VDD1 =VDD2 =VDD3 • FmCF=10MHz by ceramic resonator • FmX’tal=32.768kHz by crystal oscillation • System clock : CF oscillation (10MHz) • Internal RC oscillation stops • frequency variable RC oscillation stops • 1/1 divided • CF1=20MHz by external clock • FmX’tal=32.768kHz by crystal oscillation • System clock : CF1 oscillation (20MHz) • Internal RC oscillation stops • frequency variable RC oscillation stops • 1/2 divided • FmCF=5MHz by ceramic resonator • FmX'tal=32.768kHz by crystal oscillation • System clock : CF oscillation (5MHz) • Internal RC oscillation stops • frequency variable RC oscillation stops • 1/1divided • FmCF=0Hz (when oscillation stops) • FmX'tal=32.768kHz by crystal oscillation • System clock : RC oscillation • frequency variable RC oscillation stops • 1/2 divided • FmCF=0Hz (when oscillation stops) • FmX'al=32.768kHz by crystal oscillation • System clock :1MHz with frequency variable RC oscilatin • Internal RC oscillation stops • 1/2 divided • FmCF=0Hz (when oscillation stops) • FmX'al=32.768kHz by crystal oscillation • System clock : X'tal oscillation (32.768kHz) • Internal RC oscillation stops • frequency variable RC oscillation stops • 1/2 divided VDD[V] 4.5 - 5.5 Limits min. typ. 18 2.5 - 5.5 19 36 4.5 - 5.5 10 22 2.5 - 4.5 5 15 4.5 - 5.5 2 8 2.5 - 4.5 1 5 4.5 – 5.5 2.5 13 2.5 - 4.5 1.8 9 4.5 – 5.5 50 150 2.5 - 4.5 30 120 max. 35 unit mA µA (Continued) Ver.1.00 21/27 LC87F57C8A Parameter Symbol Current drain in IDDHALT(1) HALT mode (Note 4) IDDHALT(2) IDDHALT(3) IDDHALT(4) IDDHALT(5) IDDHALT(6) IDDHALT(7) IDDHALT(8) IDDHALT(9) IDDHALT(10) Pins Conditions VDD1 =VDD2 =VDD3 • HALT mode • FmCF=10MHz by ceramic resonator • FmX’tal=32.768kHz by crystal oscillation • System clock : CF oscillation (10MHz) • Internal RC oscillation stops • frequency variable RC oscillation stops • 1/1 divided • HALT mode • CF1=20MHz by external clock • FmX’tal=32.768kHz by crystal oscillation • System clock : CF1 oscillation (20MHz) • Internal RC oscillation stops • frequency variable RC oscillation stops • 1/2 divided • HALT mode • FmCF=5MHz by ceramic resonator • FmX’tal=32.768kHz by crystal oscillation • System clock : CF oscillation (5MHz) • Internal RC oscillation stops • frequency variable RC oscillation stops • 1/1divided • HALT mode • FmCF=0Hz (when oscillation stops) • FmX’tal=32.768kHz by crystal oscillation • System clock : RC oscillation • frequency variable RC oscillation stops • 1/2 divided • HALT mode • FmCF=0Hz (when oscillation stops) • FmX'tal=32.768kHz by crystal oscillation • System clock : 1MHz with frequency variable RC oscilatin • Internal RC oscillation stops • 1/2 divided • HALT mode • FmCF=0Hz (when oscillation stops) • FmX'tal=32.768kHz by crystal oscillation • System clock : X'tal oscillation (32.768kHz) • Internal RC oscillation stops • frequency variable RC oscillation stops • 1/2 divided VDD[V] 4.5 - 5.5 Limits min. typ. 4 4.5 - 5.5 4.5 14 4.5 - 5.5 2 5 2.5 - 4.5 1 3.2 4.5 - 5.5 0.5 1.5 2.5 - 4.5 0.3 1 4.5 - 5.5 1.5 3.6 2.5 - 4.5 1.3 3.3 4.5 - 5.5 20 80 2.5 - 4.5 10 50 max. 10 unit mA µA (Continued) 22/27 Ver.1.00 LC87F57C8A Parameter Symbol Pins Conditions Current drain during HOLD mode IDDHOLD(1) VDD1 • HOLD mode • CF1=VDD or leave it open (when using external clock) • Time-base clock HOLD mode • CF1=VDD or leave it open (when using external clock) • FmX'tal=32.768kHz by crystal oscillation Current drain during time-base clock HOLD mode IDDHOLD(2) IDDHOLD(3) VDD1 IDDHOLD(4) VDD[V] 4.5 - 5.5 Limits min. typ. 0.05 2.5 – 4.5 0.01 15 4.5 - 5.5 15 70 2.5 – 4.5 5 40 max. 20 unit µA µA (Note 4) The current of the output transistors and pull-up MOS transistors are excluded. 9. F-ROM Write Characteristics / Ta=+10°C to +55°C, VSS1=VSS2=VSS3=0V Parameter Symbol On-board writing current IDDFW(1) Writing time tFW(1) Ver.1.00 Pins VDD1 Conditions • 128-byte writing • including erase time current • 128-byte writing • including data erase time • Excluding time to fetch 128 byte data VDD[V] 4.5 - 5.5 4.5 - 5.5 Limits min. typ. 30 max. 65 unit mA 5.0 10.0 mS 23/27 LC87F57C8A Main System Clock Oscillation Circuit Characteristics The characteristics in the table bellow is based on the following conditions: 1. Using the standard oscillation evaluation board SANYO has provided. 2. Using the external peripheral parts with the indicated value. 3. The recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. Table 1. Recommended circuit parameters for the main system clock using the ceramic resonator Frequency Manufacturer 10MHz 5MHz Oscillator CSLS10M0G53B0 MURATA MURATA Recommended circuit Operating parameters supply C1 C2 Rd1 voltage range (15pF) (15pF) CSTCE10M0G52(10pF) (10pF) R0 CSTLS5M00G53(15pF) (15pF) B0 CSTCR5M00G53 (15pF) (15pF) -R0 Oscillation stabilizing time typ max Note 0Ω 4.5 – 5.5V 0.03ms 0.30ms Internal C1,C2 0Ω 4.5 – 5.5V 0.03ms 0.30ms Internal C1,C2 0Ω 2.5 – 5.5V 0.03ms 0.30ms Internal C1,C2 0Ω 2.5 – 5.5V 0.03ms 0.30ms Internal C1,C2 *The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure4) Subsystem Clock Oscillation Circuit Characteristics The characteristics in the table bellow is based on the following conditions: 1. Using the standard oscillation evaluation board SANYO has provided. 2. Using the external peripheral parts with the indicated value. 3. The recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. Table 2. Recommended circuit parameters for the subsystem clock using the crystal oscillation Frequency Manufacturer 32.768kHz SEIKO EPSON Oscillator MC-306 Recommended circuit Parameters C3 C4 Rf Rd2 9pF 9pF OPEN 820kΩ Oscillation stabilizing time typ max 1.5s 3s Operating supply voltage range 2.5 – 5.5V Note *The oscillation stabilizing time is the period until the oscillation becomes stable, after executing the instruction which starts the sub-clock oscillator or after releasing a HOLD mode. (Refer to Figure4) (Notes) Since the oscillation frequency precision is affected by the circuit pattern, place the oscillation related parts as close to the oscillation pins as possible, using the shortest possible pattern length. CF1 CF2 XT1 Rd1 XT2 Rf Rd2 C1 CF C2 C3 C4 X’tal Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit 0.5VDD Figure 3 AC timing point 24/27 Ver.1.00 LC87F57C8A VDD Power Supply VDD limit GND Reset time RES# Internal RC oscillation tmsCF CF1,CF2 tmsXta XT1,XT2 Operation mode Unfixed Reset Instruction execution d Reset time and oscillation stabilizing time HOLD release signal VALID HOLD release signal Internal RC oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2 Operation mode HOLD HALT HOLD release signal and oscillation stabilizing time Figure 4 Oscillation stabilizing time Ver.1.00 25/27 LC87F57C8A VDD RRES (Note) Select CRES and RRES value to assure that at least 200µs reset time is generated after the VDD becomes higher than the minimum operating voltage. RES CRES Figure 5 Reset circuit SI0CLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Data RAM transmission period (only SIO0) tSCK tSCKL tSCKH SI0CLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transmission period (only SIO0) tSCKLA tSCKHA SI0CLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 6 Serial input/output test condition tPIL tPIH Figure 7 Pulse input timing condition 26/27 Ver.1.00 LC87F57C8A ・Parallel input/output timing waveform：Indirect Setting, Read Mode tC(1) read cycle ADR/DATA: addr tsA(1) CS#: tsRS(1) thRS(1) RS: tWRH(1) tWRL(1) tsRS(2) tRDL(1) thRS(2) WR#: tRDH(1) tsDTR(1) RD#: thDTR(1) tdDT(1) H DATAin data Note: If port A terminals will be used as RS, WR , RD or CS , then it should be set to CMOS format by option data. ・Parallel input/output timing waveform：Indirect Setting, Write Mode tC(1) write cycle data addr ADR/DATA: tsA(1) thDTW(1) CS#: tsRS(1) thRS(3) thRS(1) RS: tWRH(1) tWRL(1) tsRS(3) tsDTW(1) WR#: tWRL(2) RD#: DATAin Note: If Port A terminals will be used as RS, WR , RD or CS , then it should be set to CMOS format by option data. Figure 8 Indirect mode: Parallel Timing Diagram Ver.1.00 27/27 LC87F57C8A ・Parallel input/output timing waveform：Direct Setting, Read Mode tC(1) read cycle addr ADR: tsA(1) thA(1) tsCS(1) thCS(1) CS#: DATA: tRDL(2) WR#: tsDTR(1) tRDH(2) RD#: thDTR(1) tdDT(2) DATAin H data Note: If Port A terminals will be used as RS, WR , RD or CS , then it should be set to CMOS format by option data. ・Parallel input/output timing waveform：Direct Setting, Write Mode tC(1) write cycle addr ADR: tsA(2) thA(2) tsCS(2) thCS(2) CS#: DATA: data tsDTW(2) thDTW(2) WR#: tWRH(2) tWRL(2) RD#: DATAin: Note: If Port A terminals will be used as RS, WR , RD or CS , then it should be set to CMOS format by option data. Figure 9 Direct Mode: Parallel input/output Timing Diagrams 28/27 Ver.1.00 ©2002 SANYO