Ordering number : ENN6237
CMOS IC
LC895198
CD-ROM Decoder for 32× ATAPI (IDE) Drives
Overview
The LC895198 is a CD-ROM decoder that supports
ATAPI (IDE) and includes 1 MB of on-chip DRAM.
Functions
•
•
•
•
•
•
CD-ROM ECC function
Sub-code read function
Built-in ATAPI (IDE) I/F (register and other blocks)
CAV audio function
Built-in DVD-ROM I/F (8-bit width)
Built-in 1-Mbit DRAM
• Built-in CAV-AUDIO function
• Built-in intelligent functions (auto buffering, auto
decoding, CD-R support, etc.)
• Built-in subcode P to W buffering function (NO-ECC)
and CD-TEXT support
Package Dimensions
unit: mm
3237-LQFP120
[LC895198]
16.0
14.0
Features
0.4
14.0
0.4
0.125
(1.2)
120
1
0.1
(1.4)
0.15
1.6max
• 32× speed supported
16.6MBytes/s (with IORDY)
Operation frequency: 33.8688 MHz
• 32× speed supported
16.6MBytes/s (without IORDY)
Operation frequency: 36 MHz
• CD main channel, C2 flag, and subcode areas in buffer
RAM can be set freely by user
• Built-in batch transfer function (function for sending CD
main channel, C2 flag, subcode, etc., at one time)
• Built-in multi transfer function (function for sending
several blocks at one time)
16.0
(1.2)
0.5
(0.5)
SANYO: LQFP120
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter
Maximum supply voltage
Input/output voltage
Allowable power dissipation
Symbol
Conditions
Ratings
Unit
VDD max
Ta = 25°C
–0.3 to +7.0
V
VI, VO
Ta = 25°C
–0.3 to VDD + 0.3
V
Pd max
Ta ≤ 70°C
400
mW
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Soldering temperature (pin part only)
Input/output power
II, IO
10 s
235
°C
Per 1 input/output reference cell
±20
mA
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N3099TH (OT) No. 6237-1/10
LC895198
Allowable Operating Ranges at Ta = 0 to +70°C, VSS = 0 V
IO cell 5.0 V supply voltage
Parameter
Symbol
Ratings
Conditions
min
typ
Supply voltage
VDD
4.5
Input voltage range
VIN
0
5.0
max
Unit
5.5
V
VDD
V
Internal cell 3.3 V supply voltage
Parameter
Symbol
Ratings
Conditions
min
typ
Supply voltage
VDD
3.0
Input voltage range
VIN
0
3.3
max
Unit
3.6
V
VDD
V
Electrical Characteristics at Ta = 0 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V
Parameter
Symbol
Input high-level voltage
VIH
Input low-level voltage
VIL
Input high-level voltage
VIH
Input low-level voltage
VIL
Input high-level voltage
VIH
Input low-level voltage
VIL
Conditions
TTL levels
(1)
TTL levels
with pull-up resistor
(9)
TTL levels Schmitt
with pull-down resistor
Input high-level voltage
VIH
Input low-level voltage
VIL
TTL levels
Schmitt
Output high-level voltage
VOH
IOH = –2 mA
Output low-level voltage
VOL
IOL = 2 mA
Output high-level voltage
VOH
IOH = –8 mA
Output low-level voltage
VOL
IOL = 8 mA
Output high-level voltage
VOH
IOH = –4 mA
Output low-level voltage
VOL
IOL = 24 mA
Output low-level voltage
VOL
IOL = 24 mA
Output low-level voltage
VOL
IOL = 8 mA
IIL
VI = VSS, VDD
Output leak current
IOZ
During high-impedance output
Pull-up resistance
RUP
Pull-down resistance
RDN
Input leak current
Applicable pins
DRESP, DREQ, HDB0 to HDB7
DRESP
HDB0 to HDB7
(2), (3), (10)
(9)
(4)
Ratings
min
typ
max
Unit
2.2
—
—
V
—
—
0.8
V
2.2
—
—
V
—
—
0.8
V
2.2
—
—
V
—
—
0.8
V
2.4
—
—
V
—
—
0.8
V
VDD – 2.1
—
—
V
—
—
0.4
V
VDD – 2.1
—
—
V
—
—
0.4
V
VDD – 2.1
—
—
V
—
—
0.4
V
(8)
—
—
0.4
V
(5), (6)
—
—
0.4
V
+10
µA
(7), (10)
(1), (2), (3), (10)
–10
(5), (7), (8), (10)
–10
+10
µA
(6), (9)
40
80
160
kΩ
40
80
160
kΩ
The applicable pin sets are as follows.
INPUT
(1)
ATPINSEL, CSCTRL, SUA0 to SUA6, BCK, C2PO, LRCK, DSDATA, SBS0, SCOR, WFCK, TEST0 to TEST1, AUDIOCK
(2)
ZRESET, ZCS, ZRD, ZWR, CSEL
(3)
DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZDMACK, ZHRST
OUTPUT
(4)
EXCK, DREQ, MCK, MCK3
(5)
ZRSTCPU
(6)
ZINT, ZINT1, ZSWAIT
(7)
DMARQ, HINTRQ
(8)
IORDY, ZIOCS16
INOUT
(9)
D0 to D7
(10) DD0 to DD15, ZDASP, ZPDIAG
Note: Pins other than XTAL and XTALCK are not included in DC characteristics.
No. 6237-2/10
LC895198
Recommended Oscillator Circuit Example
LC895198
XTALCK
PN28
R1
XTAL
PN29
R2
C1
C2
A12524
R1 = 1 MΩ
R2 = 15 Ω
C1 = 0
C2 = 47 pF
When the ceramic clock oscillator frequency is 33.8688 MHz:
(The 33.8688 MHz in this recommended example is the third harmonic.)
The exact values of the components are influenced by the printed circuit board used. Consult with the manufacturer of
the oscillator element used to determine these values.
No. 6237-3/10
LC895198
Block Diagram
RAM
Data bus[0:15] Address bus[0:16]
Data bus[0:7]
*1
Sub-code I/F
10byte FIFO for Sub Q
EXCK
Address generator
LC895198
CAV-Audio contorol
*10
CD-DSP
DAC
Address generator
*2
CD-DSP I/F
& SYNC
Detector
De-scramble &
Buffering
Address generator
ECC & EDC
ZRESET
ZRSTCPU
Reset
Controller
Address generator
Each Block
Bus control
signal
1Mbit
HOST
*3
*4
*5
ZINT0
ZINT1
*6
*7
Micro
controller
IDE I/F
Based HISIDE
Each Block
Register
R0-R127
decoder
ZSWAIT
Each Block
XTALCK
Clock
generator
XTAL
DVD-ECC
dec
MCK3
MCK
*8
*9
**1
Bus
Arbiter
&
DRAM
controller
Buffer
DRAM
Data output input I/F
Address generator
Microcontroller
RAM access
Address generator
DVD-ECC I/F
Address generator
A12525
*1
*2
*3
*4
*5
*6
*7
*8
*9
*10
**1
WFCK, SBSO, SCOR
BCK, SDATA, LRCK, C2PO
DD0 to DD15, ZDASP, ZPDIAG
ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK, CSEL
DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST
ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL
D0 to D7
HDB0 to HDB7, DRESP
DREQ
DBCK, DLRCK, DSDATA
HISIDE(WD25C32) is made by WESTERN DIGITAL
No. 6237-4/10
LC895198
Pin Functions
Type
LC895198 Pin Functions 1
(When ATPINSEL (pin 113) is 0)
I
INPUT
B
BIDIRECTION
O
OUTPUT
P
POWER
NC
NOT CONNECT
Pin No.
Pin
Type
1
VDD0
P
5.0 V
2
DREQ
O
DVD ECC data request output
3
DRESP
I
DVD ECC data latch signal input
4
HDB7 (IOP0)
B
5
HDB6 (IOP1)
B
6
HDB5 (IOP2)
B
7
HDB4 (IOP3)
B
DVD ECC data I/O
8
HDB3 (IOP4)
B
These pins can be switched to function as general-purpose I/O ports by register settings.
9
HDB2 (IOP5)
B
10
HDB1 (IOP6)
B
11
HDB0 (IOP7)
B
12
MCK3
O
13
VSS0
P
14
VDD1
P
3.3 V
15
VDD0
P
5.0 V
16
DSDATA
O
17
DLRCK
O
18
DBCK
O
19
C2PO
I
20
SDATA
I
21
BCK
I
Function
XTALCLK 1/1, 1/2, and stop output
D/A converter output
CD DSP interface
22
LRCK
I
23
EXCK
O
24
WFCK
I
25
SBSO
I
26
SCOR
I
27
MCK
O
XTALCLK 1/1, 1/2, and stop output
28
XTALCK
I
Crystal oscillator circuit input
29
XTAL
O
Crystal oscillator circuit output
30
VSS0
P
31
VDD1
P
3.3 V
32
VDD0
P
5.0 V
33
VSS0
P
34
CSCTRL
I
Active low/active high selection for the microcontroller CS pin
35
ZRD
I
Microcontroller data read signal input
36
ZWR
I
Microcontroller data write signal input
37
ZCS
I
Register chip select input from the microcontroller
38
SUA0
I
39
SUA1
I
40
SUA2
I
41
SUA3
I
42
SUA4
I
43
SUA5
I
44
SUA6
I
45
VDD1
P
3.3 V
46
VDD0
P
5.0 V
47
VSS0
P
Subcode I/O
Microcontroller register selection signals
Continued on next page.
No. 6237-5/10
LC895198
Continued from preceding page.
Pin No.
Pin
Type
48
D0
B
Function
49
D1
B
50
D2
B
51
D3
B
Microcontroller data signals.
52
D4
B
These pins have built-in pull-up resistors.
53
D5
B
54
D6
B
55
D7
B
56
ZINT0
O
57
ZINT1
O
Interrupt request signal output to the microcontroller
58
ZSWAIT
O
WAIT signal output to the microcontroller
59
ZRSTCPU
O
CPU reset signal output
60
VSS0
P
61
VDD0
P
62
CSEL
I
63
ZHRST
I
64
ZDASP
B
65
ZCS3FX
I
66
ZCS1FX
I
67
VSS1
P
68
DA2
I
69
DA0
I
70
ZPDIAG
B
71
DA1
I
72
VSS1
P
73
ZIOCS16
O
74
HINTRQ
O
75
VSS1
P
76
VDD1
P
77
ZDMACK
I
78
IORDY
O
79
VSS1
P
80
ZDIOR
I
81
ZDIOW
I
82
DMARQ
O
83
DD15
B
84
DD0
B
85
VSS1
P
86
DD14
B
87
DD1
B
88
DD13
B
89
DD2
B
90
VSS1
P
91
VDD0
P
92
DD12
B
93
DD3
B
94
DD11
B
95
DD4
B
96
VSS1
P
97
DD10
B
98
DD5
B
99
DD9
B
100
VSS1
P
5.0 V
ATAPI control signals
ATAPI control signals
ATAPI control signals
3.3 V
ATAPI control signals
ATAPI control signals
ATAPI data bus
ATAPI data bus
5.0 V
ATAPI data bus
ATAPI data bus
Continued on next page.
No. 6237-6/10
LC895198
Continued from preceding page.
Pin No.
Pin
Type
101
DD6
B
Function
102
DD8
B
103
DD7
B
104
VDD1
P
3.3 V
105
VDD1
P
3.3 V
106
VDD0
P
5.0 V
107
VDD1
P
3.3 V
108
ZRESET
I
IC reset input
109
VDD1
P
3.3 V
110
VSS0
P
111
TEST1
I
112
VSS0
P
113
ATPINSEL
I
114
VSS0
P
115
TEST0
I
Test pin. This pin must be connected to VSS in normal operation.
116
VDD0
I
5.0 V
117
AUDIOCK
I
Clock input for the CAV audio block
118
VDD0
P
5.0 V
119
VDD0
P
5.0 V
120
VSS0
P
ATAPI data bus
Test pin. This pin must be connected to VSS in normal operation.
ATAPI pin layout selection. This pin must be connected to VSS0.
• Unused ("NC") pins must be left open.
• Pins whose name begin with a Z operate with inverted (negative) logic.
• VSS0 is the logic system ground and VSS1 is the IDE interface driver ground.
• Applications must supply 5.0 V to VDD0 and 3.3 V to VDD1.
No. 6237-7/10
LC895198
Pin Functions
Type
LC895198 Pin Functions 2
(When ATPINSEL (pin 113) is 1)
I
INPUT
B
BIDIRECTION
O
OUTPUT
P
POWER
NC
NOT CONNECT
Pin No.
Pin
Type
1
VDD0
P
5.0 V
2
DREQ
O
DVD ECC data request output
3
DRESP
I
DVD ECC data latch signal input
4
HDB7 (IOP0)
B
5
HDB6 (IOP1)
B
6
HDB5 (IOP2)
B
7
HDB4 (IOP3)
B
DVD ECC data I/O
8
HDB3 (IOP4)
B
These pins can be switched to function as general-purpose I/O ports by register settings.
9
HDB2 (IOP5)
B
10
HDB1 (IOP6)
B
11
HDB0 (IOP7)
B
12
MCK3
O
13
VSS0
P
14
VDD1
P
3.3 V
15
VDD0
P
5.0 V
16
DSDATA
O
17
DLRCK
O
18
DBCK
O
19
C2PO
I
20
SDATA
I
21
BCK
I
Function
XTALCLK 1/1, 2/5, 1/5, 1/512, and stop output
DAC converter output
CD DSP interface
22
LRCK
I
23
EXCK
O
24
WFCK
I
25
SBSO
I
26
SCOR
I
27
MCK
O
XTALCLK 1/1, 1/2, and stop output
28
XTALCK
I
Crystal oscillator circuit input
29
XTAL
O
Crystal oscillator circuit output
30
VSS0
P
31
VDD1
P
3.3 V
32
VDD0
P
5.0 V
33
VSS0
P
34
CSCTRL
I
Active low/active high selection for the microcontroller CS pin
35
ZRD
I
Microcontroller data read signal input
36
ZWR
I
Microcontroller data write signal input
37
ZCS
I
Register chip select input from the microcontroller
38
SUA0
I
39
SUA1
I
40
SUA2
I
41
SUA3
I
42
SUA4
I
43
SUA5
I
44
SUA6
I
45
VDD1
P
3.3 V
46
VDD0
P
5.0 V
47
VSS0
P
Subcode I/O
Microcontroller register selection signals
Continued on next page.
No. 6237-8/10
LC895198
Continued from preceding page.
Pin No.
Pin
Type
48
D0
B
Function
49
D1
B
50
D2
B
51
D3
B
Microcontroller data signals.
52
D4
B
These pins have built-in pull-up resistors.
53
D5
B
54
D6
B
55
D7
B
56
ZINT0
O
57
ZINT1
O
Interrupt request signal output to the microcontroller
58
ZSWAIT
O
WAIT signal output to the microcontroller
59
ZRSTCPU
O
CPU reset signal output
60
VSS0
P
61
VDD0
P
62
CSEL
I
63
DD7
B
64
DD8
B
65
DD6
B
66
DD9
B
67
VSS1
P
68
DD5
B
69
DD10
B
70
DD4
B
71
DD11
B
72
VSS1
P
73
DD3
B
74
DD12
B
75
VSS1
P
76
VDD1
P
77
DD2
B
78
DD13
B
79
VSS1
P
80
DD1
B
81
DD14
B
82
DD0
B
83
DD15
B
84
DMARQ
O
85
VSS1
P
86
ZDIOW
I
87
ZDIOR
I
88
IORDY
O
89
ZDMACK
I
90
VSS1
P
91
VDD0
P
92
HINTRQ
O
93
ZIOCS16
O
94
DA1
I
95
ZPDIAG
B
96
VSS1
P
97
DA0
I
98
DA2
I
99
ZCS1FX
I
100
VSS1
P
5.0 V
ATAPI control signals
ATAPI data bus
ATAPI data bus
ATAPI data bus
3.3 V
ATAPI data bus
ATAPI data bus
ATAPI control signal
ATAPI control signal
5.0 V
ATAPI control signal
ATAPI control signal
Continued on next page.
No. 6237-9/10
LC895198
Continued from preceding page.
Pin No.
Pin
Type
101
ZCS3FX
I
Function
102
ZDASP
B
103
ZHRST
I
104
VDD1
P
3.3 V
105
VDD1
P
3.3 V
106
VDD0
P
5.0 V
107
VDD1
P
3.3 V
108
ZRESET
I
IC reset input
109
VDD1
P
3.3 V
110
VSS0
P
111
TEST1
I
112
VSS0
P
113
ATPINSEL
I
114
VSS0
P
115
TEST0
I
Test pin. This pin must be connected to VSS in normal operation.
116
VDD0
I
5.0 V
117
AUDIOCK
I
Clock input for the CAV audio block
118
VDD0
P
5.0 V
119
VDD0
P
5.0 V
120
VSS0
P
ATAPI control signal
Test pin. This pin must be connected to VSS in normal operation.
ATAPI pin layout selection. This pin must be connected to VDD0.
• Unused ("NC") pins must be left open.
• Pins whose name begin with a Z operate with inverted (negative) logic.
• VSS0 is the logic system ground and VSS1 is the IDE interface driver ground.
• Applications must supply 5.0 V to VDD0 and 3.3 V to VDD1.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of November, 1999. Specifications and information herein are
subject to change without notice.
PS No. 6237-10/10