Revised January 1999 74ABT16652 16-Bit Transceivers and Registers with 3-STATE Outputs General Description Features The ABT16652 consists of sixteen bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. ■ Independent registers for A and B buses ■ Multiplexed real-time and stored data ■ Separate control logic for each byte ■ A and B output sink capability of 64 mA, source capability of 32 mA ■ Guaranteed output skew ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Nondestructive hot insertion capability Ordering Code: Order Number Package Number 74ABT16652CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Description 74ABT16652CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Pin Names A0–A16 Connection Diagram Descriptions Data Register A Inputs/ 3-STATE Outputs B0–B16 Data Register B Inputs/ 3-STATE Outputs CPABn, CPBAn Clock Pulse Inputs SABn, SBAn Select Inputs OEABn, OEBAn Output Enable Inputs © 1999 Fairchild Semiconductor Corporation DS011599.prf www.fairchildsemi.com 74ABT16652 16-Bit Transceivers and Registers with 3-STATE Outputs April 1993 74ABT16652 Functional Description In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SABn, SBAn) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the ABT16652. Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropriate Clock Inputs (CPABn, CPBAn) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEABn and OEBAn. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. Note A: Real-Time Transfer Bus B to Bus A Note C: Storage OEAB OEBA CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA 1 1 X H 1 1 1 1 1 1 L L X X X L Note B: Real-Time Transfer Bus A to Bus B OEAB OEBA CPAB CPBA SAB X H 1 1 1 1 X X X X X X X X Note D: Transfer Storage Data to A or B SBA 1 1 1 1 1 1 H H X X L X OEAB OEBA CPAB1 CPBA SAB SBA FIGURE 1. www.fairchildsemi.com L L 2 1 1 H L 1 H or L H or L 1 1 H H Inputs OEAB1 OEBA1 L H L H X H H H L X L L L L L L Inputs/Outputs (Note 1) CPAB1 CPBA1 SAB1 SBA1 H or L H or L H or L H or L A0 thru A7 Input B0 thru B7 X X Input X X X X Input Not Specified Store A, Hold B X X Input Output X X Not Specified Input Hold A, Store B Store B in Both Registers X X Output Input X L Output Input X H or L X H H H X X L X H H H or L X H X H L H or L H or L H H Isolation Store A and B Data X X Operating Mode Store A in Both Registers Real-Time B Data to A Bus Store B Data to A Bus Input Output Output Output Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW to HIGH Clock Transition Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs. This also applies to data I/O (A and B: 8–15) and #2 control pins. Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74ABT16652 Function Table 74ABT16652 Absolute Maximum Ratings(Note 2) Over Voltage Latchup (I/O) Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C 10V Recommended Operating Conditions −40°C to +85°C Free Air Ambient Temperature VCC Pin Potential to +4.5V to +5.5V −0.5V to +7.0V Supply Voltage Input Voltage (Note 3) −0.5V to +7.0V Minimum Input Edge Rate (∆V/∆t) Input Current (Note 3) −30 mA to +5.0 mA Ground Pin Voltage Applied to Any Output −0.5V to +5.5V in the Disable or Power-Off State 20 mV/ns 100 mV/ns Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output Note 3: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) in LOW State (Max) 50 mV/ns Enable Input Clock Input −0.5V to VCC in the HIGH State Data Input −500 mA DC Latchup Source Current DC Electrical Characteristics Symbol Parameter Min Typ Max Units VCC Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins) VOH Output HIGH 2.5 V Min IOH = −3 mA, (An, Bn) Voltage 2.0 V Min IOL = 64 mA, (A n, Bn) V 0.0 IID = 1.9 µA, (Non-I/O Pins) µA Max 7 µA Max VIN = 7.0V (Non-I/O Pins) 100 µA Max VIN = 5.5V (An, Bn) −1 µA Max VOL Output LOW Voltage VID Input Leakage Test IIH Input HIGH Current V Conditions VIH Recognized HIGH Signal Recognized LOW Signal IOH = −32 mA, (A n, Bn) 0.55 All Other Pins Grounded 1 IBVI Input HIGH Current VIN = 2.7V (Non-I/O Pins) (Note 4) VIN = VCC (Non-I/O Pins) 1 Breakdown Test IBVIT Input HIGH Current Breakdown Test (I/O) IIL Input LOW Current −1 VIN = 0.5V (Non-I/O Pins) (Note 4) VIN = 0.0V (Non-I/O Pins) IIH + IOZH Output Leakage Current 10 µA 0V–5.5V IIL + IOZL Output Leakage Current −10 µA 0V–5.5V VOUT = 2.7V (An, Bn); OEABn = GND and OEBAn = 2.0V VOUT = 0.5V (An, Bn); OEABn = GND and OEBAn = 2.0V IOS Output Short-Circuit Current −275 mA Max ICEX Output HIGH Leakage Current 50 µA Max VOUT = 0V (An, Bn) VOUT = VCC (An, Bn) IZZ Bus Drainage Test 100 µA 0.0V VOUT = 5.5V (An, Bn); All Others GND ICCH Power Supply Current 1.0 mA Max All Outputs HIGH ICCL Power Supply Current 60 mA Max All Outputs LOW ICCZ Power Supply Current 1.0 mA Max Outputs 3-STATE; ICCT Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V ICCD Dynamic ICC 0.23 mA/MHz Max All Others at VCC or GND All Others at VCC or GND No Load Outputs Open OEABn, OEBAn and SEL = GND (Note 4) Non-I/O = GND or VCC One bit toggling, 50% duty cycle Note 4: Guaranteed but not tested. www.fairchildsemi.com 4 (SSOP Package) Symbol Parameter Min Typ Max 0.7 1.2 −1.4 −1.0 Units Conditions VCC CL = 50 pF, RL = 500Ω V 5.0 TA = 25°C (Note 5) V 5.0 TA = 25°C (Note 5) VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VOHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25° (Note 6) VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.6 V 5.0 TA = 25°C (Note 7) VILD Maximum LOW Level Dynamic Input Voltage V 5.0 TA = 25°C (Note 7) 1.2 0.8 Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. AC Electrical Characteristics (SSOP Package) Symbol Parameter TA = +25°C TA = −40°C to +85°C V CC = +5.0V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Typ Max Min Max tPLH Propagation Delay 1.5 3.0 4.9 1.5 4.9 tPHL Clock to Bus 1.5 3.4 4.9 1.5 4.9 tPLH Propagation Delay 1.5 2.6 4.5 1.5 4.5 tPHL Bus to Bus 1.5 3.0 4.5 1.5 4.5 tPLH Propagation Delay 1.5 2.9 5.0 1.5 5.0 tPHL SBAn or SABn 1.5 3.2 5.0 1.5 5.0 tPZH Enable Time 1.5 2.8 5.5 1.5 5.5 tPZL OEBAn or OEABn 1.5 3.0 5.5 1.5 5.5 tPHZ Disable Time 1.5 3.9 5.9 1.5 5.9 tPLZ OEBAn or OEABn 1.5 3.3 5.9 1.5 5.9 Units ns ns ns to An to Bn ns to An or Bn ns to An or Bn AC Operating Requirements Symbol Parameter Min fmax Max Clock Frequency tS(H) Setup Time, HIGH tS(L) or LOW Bus to Clock tH(H) Hold Time, HIGH tH(L) or LOW Bus to Clock tW(H) Pulse Width, tW(L) HIGH or LOW TA = +25°C TA = −40°C to +85°C V CC = +5.0V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Typ Max Min 200 Units Max MHz 2.0 2.0 ns 1.0 1.0 ns 3.0 3.0 ns 5 www.fairchildsemi.com 74ABT16652 DC Electrical Characteristics 74ABT16652 Extended AC Electrical Characteristics (SSOP Package) Symbol Parameter TA = −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF CL = 250 pF 16 Outputs Switching 1 Output Switching 16 Outputs Switching (Note 8) (Note 9) Units (Note 10) Min Max Min Max Min Max tPLH Progagation Delay 1.5 5.8 2.0 7.5 2.5 10.0 tPHL Clock to Bus 1.5 5.8 2.0 7.5 2.5 10.0 tPLH Progagation Delay 1.5 6.5 2.0 7.0 2.5 9.5 tPHL Bus to Bus 1.5 6.5 2.0 7.0 2.5 9.5 tPLH Progagation Delay 1.5 6.0 2.0 7.5 2.5 10.0 tPHL SBA or SAB to 1.5 6.0 2.0 7.5 2.5 10.0 ns ns ns An or Bn tPZH Output Enable Time 1.5 6.0 2.0 8.0 2.5 10.5 tPZL OEBAn or OEABn to 1.5 6.0 2.0 8.0 2.5 10.5 ns An or Bn tPHZ Output Disable Time 1.5 6.0 tPLZ OEBA or OEAB to 1.5 6.0 (Note 11) (Note 11) ns An or Bn Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 11: The 3-STATE delay times are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Skew (Note 12) (SSOP Package) Symbol Parameter tOSHL Pin to Pin Skew (Note 14) HL Transitions tOSLH Pin to Pin Skew (Note 14) LH Transitions tPS Duty Cycle (Note 15) LH–HL Skew tOST Pin to Pin Skew (Note 14) LH/HL Transitions tPV Device to Device Skew (Note 16) LH/HL Transitions TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF 16 Outputs Switching 16 Outputs Switching (Note 12) (Note 13) Max Max 2.0 2.5 ns 2.0 2.5 ns 2.0 2.5 2.8 3.0 ns 3.5 4.0 ns Units Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW to HIGH and/or HIGH to LOW (tOST). This specification is guaranteed but not tested. Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. www.fairchildsemi.com 6 Symbol Parameter Typ Units Conditions (TA = 25°C) CIN Input Capacitance 5.0 pF V CC = 0V (non I/O pins) CI/O (Note 17) I/O Capacitance 11.0 pF V CC = 5.0V (An, Bn) Note 17: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883, Method 3012. AC Loading *Includes jig and probe capacitance FIGURE 3. Test Input Signal Levels FIGURE 2. Standard AC Test Load Input Pulse Requirement Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 4. Test input Signal Requirements AC Waveforms FIGURE 5. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 7. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 6. Propagation Delay, Pulse Width Waveforms FIGURE 8. Setup Time, Hold Time and Recovery Time Waveforms 7 www.fairchildsemi.com 74ABT16652 Capacitance 74ABT16652 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A www.fairchildsemi.com 8 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74ABT16652 16-Bit Transceivers and Registers with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)