Edge693
500 MHz Monolithic
Dual Pin Electronics Driver
EDGE HIGH-PERFORMANCE PRODUCTS
Description
Applications
The Edge693 is a dual pin electronics driver solution
manufactured in a high-performance, complementary
bipolar process. In Automatic Test Equipment (ATE)
applications, the Edge693 offers two pin drivers suitable
for drive-only channels in memory testers, as well as for
bidirectional channels in memory, VLSI, and mixed- signal
test systems.
•
•
Memory Test Equipment
Instrumentation
Each driver is completely isolated from the other. There
are separate data, enable, slew rate adjust, high and
low levels; as well as power supply inputs for each driver.
The driver output slew rate is adjustable from 3 V/ns to
1 V/ns, allowing the matching of edges from channel-tochannel, as well as slowing down edges for noise
sensitive applications.
Each driver is capable of driving 9 V signals over a 12 V
range, in addition to going into a high impedance state.
The Edge693 can generate ECL signals up to 500 MHz
and 3V signals in excess of 300 MHz.
Functional Block Diagram
SLEWADJA
Combining two independent drivers into a 28-pin PLCC
package offers a highly integrated solution appropriate
where speed and density are at a premium.
VCCA GNDA VEEA
DRVENA
DRVENA*
DRIVER A
DHIA
DOUTA
EN
Features
DHIA*
DVHA
•
•
•
•
•
•
>2.5 V/ns Driver Slew Rates
Adjustable Driver Slew Rates
HiZ Capability
12 V Output Range
9 V Output Swings
28-Pin PLCC with an Internal
Heat Spreader
DVLA
BIAS
DRVENB
DRVENB*
DRIVER B
DHIB
DOUTB
EN
DHIB*
DVHB
DVLB
SLEWADJB
Revision 1 / August 4, 2000
1
VCCB GNDB VEEB
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
PIN Description
Pin Name
Pin #
Description
Driver
DRVENA, DRVENA*
DRVENB, DRVENB*
25, 24
5, 6
Wide voltage differential input pins that determine whether the driver (A and B
respectively) is forcing a voltage or placed in a high impedance state.
DHIA, DHIA*
DHIB, DHIB*
27, 28
3, 2
Wide voltage differential input pins that force one of two programmable levels
(DVH or DVL) at the driver (A and B respectively) output.
DOUTA
DOUTB
18
12
DVLA, DVHA
DVLB, DVHB
22, 23
8, 7
Buffereed analog inputs that program the low and high output levels for driver A
and driver B.
DVLCAPA, DVHCAPA
DVLCAPB, DVHCAPB
16, 21
14, 9
Analog pins. 0.01 µF capacitor to ground should be connected to each pin.
SLEWADJA
SLEWADJB
20
10
Analog current inputs that adjust the rise and fall slew rates of driver A and
driver B.
BIAS
1
Analog input. A positive current into this node sets the internal bias level for
driver A and driver B.
VEEA, VEEB
17, 13
Negative power supply for driver A and driver B.
VCCA, VCCB
19, 11
Positive power supply for driver A and driver B.
GNDA, GNDB
26, 4
Device ground for driver A and driver B.
Driver A and driver B outputs.
Power
Test Pins
THERMAL DIODE
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Thermal monitor output used to track the die junction temperature.
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
PIN Description (continued)
2000 Semtech Corp.
DRVENA
DRVENA*
DVHA
DVLA
DVHCAPA
SLEWADJA
VCCA
25
24
23
22
21
20
19
28-Pin PLCC
15
THERMAL DIODE
DHIB*
2
14
DVLCAPB
DHIB
3
13
VEEB
GNDB
4
12
DOUTB
3
11
1
VCCB
BIAS
10
DVLCAPA
SLEWADJB
16
9
28
DVHCAPB
DHIA*
8
VEEA
DVLB
17
7
27
DVHB
DHIA
6
DOUTA
DRVENB*
18
5
26
DRVENB
GNDA
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description
Introduction
Driver Levels
The driver circuit will force the DOUT output to one of
three states:
DVH and DVL are high-input impedance voltage controlled
inputs that establish the driver logical high and low levels
respectively.
1.
2.
3.
DVH (driver high voltage level)
DVL (driver low voltage level)
High Impedance (Hi Z).
Slew Rate Adjustment
Both driver digital control inputs (DHI/DHI*, DRVEN/
DRVEN*) are wide-voltage differential inputs capable of
receiving ECL, TTL, and CMOS signals. Single-ended
operation is achievable by generating the proper
threshold levels for the inverting inputs.
The driver rising and falling slew rates are adjustable
from 3.0 V/ns to 1 V/ns. The SLEWADJ signals are
current controlled inputs that vary the rising and falling
edge slew rates. An input current of 2.0 mA translates
to a slew rate of 3.0 V/ns. An input current of 0.8 mA
forces a 1 V/ns edge (see Figure 1).
The drive enable (DRVEN/DRVEN*) inputs control
whether the driver is forcing a voltage or is placed in a
high-impedance state. If DRVEN is more positive than
DRVEN*, the output will force either DVL or DVH,
depending on the driver data inputs. When DRVEN is
more negative than DRVEN*, the output is set to highimpedance, independent of the driver data inputs.
Driver Data
Slew Rate (V/ns)
Drive Enable
2.5
1.0
0.8
The driver data inputs (DHI/DHI*) determine whether
the driver output is high or low. If DHI is more positive
than DHI*, the output will force DVH when the driver is
enabled. If DHI is more negative than DHI*, the output
will force DVL when the driver is enabled.
Table 1 summarizes the functionality of the driver enable
and driver data pins.
DRVEN, DRVEN*
DHI, DHI*
DOUT
DRVEN > DRVEN*
DHI > DHI*
DVH
DRVEN > DRVEN*
DHI < DHI*
DVL
DRVEN < DRVEN*
X
HiZ
2.0
SLEWADJ (mA)
(BIAS = 1.5 mA)
Figure 1. Slew Rate Control
Notice that the driver A slew rate and driver B slew rate
are independent. However, the rising and falling edge
slew rates on each driver track each other and are not
independent (see Figure 2).
a
b
a. SLEWADJ = 2.0 mA, Rising SR = Falling SR = 2.5V/ns.
b. SLEWADJ = 0.8 mA, Rising SR = Falling SR = 1.0V/ns.
Figure 2. Output Slew Rate Adjustability
Table 1. DRVEN and DHI Pin Functionality
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description (continued)
For system level flexibility, the SLEWADJ input is designed
to allow a voltage DAC, a current DAC, or a resistor to a
fixed voltage as possible slew rate control mechanisms
(see Figure 3).
SLEWADJ
1.5KΩ
DVLCAP / DVHCAP
These two analog nodes are brought out to better
stabilize the high and low driver levels. Much like placing
decoupling capacitors on the DVL and DVH input pins,
the DVLCAP and DVHCAP pins require a fixed .01 µF
chip capacitor (with good high frequency characteristics)
to ground (see Figure 5). A tight layout with minimum
etch is recommended.
Edge693
DVLCAP
Rise/Fall
Adjust Current
DVHCAP
.01 µF
.01 µF
Figure 3. SLEWADJ Inputs
Figure 5. DVLCAP and DVHCAP
Driver Bias
Thermal Monitor
The BIAS pin is an analog current input that requires a
1.2 mA fixed reference current for the driver. Several
circuit configurations are usable to satisfy this
requirement, the most simple being a fixed resistor to a
fixed power supply, typically VCC (see Figure 4). Looking
into the BIAS node shows a .7 V voltage source with a
1.5 KW impedance, so the equation to select the fixed
resistor is:
The Edge693 includes an on-chip thermal monitor
accessible through the THERMAL DIODE pin. This node
connects to 5 diodes in series to VEE (see Figure 6) and
may be used to accurately measure the junction
temperature at any time.
Thermal Diode
Bias Current
(VCC – .7) / (R + 1.5) = 1.2 mA
Alternatively, a current DAC could be used to either
program the BIAS current or to perform subtle
adjustments in the fixed value.
VCC
Temperature coefficient = –10 mV/ C
˚
Edge693
VEE
Figure 6. Thermal Diode String
1.2 mA
R
Bias
Figure 4. Bias Current Generation
2000 Semtech Corp.
A bias current of 100 µA is injected into this node, and
the measured voltage corresponds to a specific junction
temperature with the following equation:
TJ(˚C) = {(VTHERMAL DIODE – VEE) / 5 – .7} / (–.00208).
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
Application Information
Thermal Information
Parameter
Symbol
Min
Typ
Max
Units
Thermal Resistance
Junction to Case
θJC
13
oC/W
Junction to Air
Still Air
50 LFPM
400 LFPM
θJA
θJA
θJA
49
36
26
oC/W
oC/W
oC/W
Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse
air flow of 400 linear feet per minute over the device mounted either in the test socket or on the printed
circuit board. Thermal resistance measurements are taken with device soldered to PCB.
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
Package Information
28 Pin PLCC Package
θJA = 75 to 80˚C / W
PIN Descriptions
Pin #1
Pin #1
Pin #1 Ident
0.045 x 45o
[1.143]
0.485 – 0.495
[12.32 – 12.57]
SQ
0.300 REF
[7.62]
0.450 – 0.456
[11.43 – 11.58]
SQ
0.050
[1.27]
TYP
.045 x 45
[1.14]
o
0.165 – 0.180
[4.19 – 4.57]
0.390 – 0430
[9.91 – 10.92]
0.026 – 0.032
[0.661 – 0.812]
0.026 – 0.032
[0.661 – 0.812]
0.090 – 0.120
[2.29 – 3.04]
Notes: (unless otherwise specified)
1. Dimensions are in inches [millimeters].
2. Tolerances are: .XXX ± 0.005 [0.127].
3. PLCC packages are intended for surface mounting on solder lands on 0.050 [1.27] centers.
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
Recommended Operating Conditions
Parameter
Symbol
Min
Positive Power Supply
VCC
Negative Power Supply
Typ
Max
Units
10.5
12.5
V
VEE
-8.0
-4.2
V
Total Analog Supply
VCC - VEE
14.7
19.0
V
Analog Inputs
Driver High Level
Driver Low Level
Driver Bias
Driver A Slew Rate Adjust
Driver B Slew Rate Adjust
DVH
DVL
BIAS
SLEWADJA
SLEWADJB
VEE + 3.5
VEE + 2.9
VCC - 2.9
VCC - 3.5
0.8
0.8
2.5
2.5
V
V
mA
mA
mA
Ambient Operating
Temperature
TA
0
+70
oC
Junction Temperature
TJ
+25
+125
oC
1.5
Absolute Maximum Ratings
Parameter
Symbol
Min
VCC (Relative to GND)
VCC
VEE (Relative to GND
VEE
Total Power Supply
Max
Units
0
+14.0
V
-10.0
0
V
+19.0
V
VCC - VEE
Typ
Digital Input Voltages
DRVEN, DRVEN*
DHI, DHI*
VEE
+7.0
V
Differential Digital Input Voltages
DRVEN - DRVEN*
DHI - DHI*
-5.5
+5.5
V
Analog Voltages
DOUT, DVL, DVH
VEE
VCC
V
BIAS
SLEWADJA
SLEWADJB
0
0
0
2.5
3.0
3.0
mA
mA
mA
DOUT
-50
+50
mA
Ambient Operating Temperature
TA
-55
+125
oC
Storage Temperature
TS
-65
+150
oC
Junction Temperature
TJ
+150
oC
TSOL
260
oC
Analog Input Currents
Driver Bias
Slew Rate Adjust
Driver Output Current (Static)
Soldering Temperature
(5 seconds, 1/4" from pin)
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only, and functional operation of the device at these or any other conditions above those listed in the
operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
DC Characteristics
Parameter
Analog Input Current
DVH, DVL
Bias Input
Symbol
Min
IIN
BIAS
-50
Adjustment Inputs
SLEWADJ Input Resistance
SLEWADJ Current Range
Typ
Max
Units
+50
µA
mA
1.5
0.9
2.0
KΩ
mA
VDOUT
Vswing
VEE + 3.5
0.25
VCC - 3.5
9.0
V
V
IDOUT
IDOUT
-35
-20
-100
+35
+35
+100
mA
mA
mA
ILEAK
ILEAK
-1
-3
1
3
µA
µA
Driver High Accuracy
Offset (Note 1)
Gain (Note 2)
Linearity (Note 3)
DVH - DOUT
∆DVH / ∆DOUT
DVL - DOUT
-90
-95
-15
-65
.99
1
-40
1.0
+15
mV
V/V
mV
Driver Low Accuracy
Offset (Note 1)
Gain (Note 2)
Linearity (Note 3)
DVH - DOUT
∆DVH / ∆DOUT
DVL - DOUT
-75
-95
-15
-50
.99
1
-25
1.0
+15
mV
V/V
mV
Driver Circuit
Output Voltage Range
Output Voltage Swing
Max Static Output Current:
DOUT >= -2V
DOUT < -2V
Max Dynamic Output Current
DOUT Leakage Current (Note 1)
DOUT >= -2V
DOUT < -2V
Offset Voltage Temperature
Coefficient
1.5
DOUT TC
Driver Output Impedance
ZOUT
1.0
Driver PSRR
PSRR
20
Digital Inputs
DRVEN, DRVEN*, DHI, DHI*
Input Current
Input Voltage Range
Differential Input Swing
IIN
VRNG
VDIFF
-900
-2.0
0.25
Power Supply Current
Positive Supply
Negative Supply
Note 1:
Note 2:
Note 3:
ICC
IEE
mV/oC
±1
-160
3.0
4.5
Ω
dB
+900
+5.5
+4.0
140
-140
160
µA
V
V
mA
mA
The offset voltage is defined as the difference between the measured driver output at DOUT under no
load conditions versus the programmed voltage (DVH or DVL) when forced to –1.0 V.
The driver gain is defined as the change in driver output voltage (DOUT) divided by the change in
programmed input voltage (DVH or DVL). Measurements are taken at –1.0 V and +4.0 V programmed
inputs with the output under no-load conditions.
Linearity error is defined as the maximum deviation between the theoretical driver output voltage
(predicted by the straight line determined by the offset and gain) and the actual measured output
voltage under no load conditions.
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EDGE HIGH-PERFORMANCE PRODUCTS
AC Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Driver Circuit
Tpd from DHI to DOUT (Note 1)
1.5
ns
Tpd from DRVEN to DOUT HiZ (Note 2)
1.5
ns
Tpd from DRVEN to DOUT Active (Note 2)
1.5
ns
Tr/Tf
Tr/Tf
Tr/Tf
Tr/Tf
0.6
1.2
1.8
2.75
ns
ns
ns
ns
SR/IADJ
.938
V/ns/mA
Toggle Rate (Note 4)
Fmax
500
MHz
Output Capacitance in HiZ
Cout
2.0
pF
1.0
2.0
2.7
3.5
ns
ns
ns
ns
DOUT Rise/Fall Times (Note 3)
ECL, 20% - 80%
3V, 10% - 90%
5V, 10% - 90%
8V, 10% - 90%
Slew Rate Sensitivity to RADJ or FADJ
Tpd
Minimum Pulse Width (Note 5)
ECL
3V
5V
7V
The specified limits shown can be met only after thermal equilibrium has been established. Thermal
equilibrium is established by applying power for at least two minutes while maintaining the normal operating
environment. (IBIAS = 1.2 mA, SLEWADJ = 2.5 mA)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Tpd is measured from crossover point of DHI and DHI* to the 50% point in the output. DVL
equals 0 V and DVH equals +3 V.
Specification condition: DVL equals -1 V and DVH equals +1 V. Output is terminated to GND by
100 Ω. Tpd is measured from the crossover point of DRVEN and DRVEN* to the point where a
10-percent change in output voltage occurs.
The driver load is an 18 cm 50Ω transmission line terminated with 1KΩ in parallel with 3 pF.
ECL output conditions. Signal reaches 100% of programmed value.
The output pulse width is measured at the 50-percent points. Output reaches 100% of programmed
value.
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Edge693
EDGE HIGH-PERFORMANCE PRODUCTS
Ordering Information
Model Number
Package
E693AHJ
28-Pin PLCC
(with Internal Heat Spreader)
EVM693AHJ
Edge693 Evaluation Module
Contact Information
Semtech Corporation
Edge High-Performance Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
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