PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER PRELIMINARY - December 2, 1999 TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION FEATURES The SC1186 combines a synchronous voltage mode controller with two low-dropout linear regulators providing most of the circuitry necessary to implement three DC/DC converters for powering ® advanced microprocessors such as Pentium II & III. • • • • • • The SC1186 switching section features an integrated 5 bit D/A converter, latched drive output for enhanced noise immunity, pulse by pulse current limiting and logic compatible shutdown. The SC1186 switching section operates at a fixed frequency of 140kHz, providing an optimum compromise between size, efficiency and cost in the intended application areas. The integrated D/A converter provides programmability of output voltage from 2.0V to 3.5V in 100mV increments and 1.30V to 2.05V in 50mV increments with no external components. Synchronous design, enables no heatsink solution 95% efficiency (switching section) 5 bit DAC for output programmability ® Designed for Intel Pentium ll & III requirements 1.5V, 2.5V short circuit protected linear controllers 1.265V ± 1.5% Reference available APPLICATIONS • • • • ® Pentium ll & III microprocessor supplies Flexible motherboards 1.3V to 3.5V microprocessor supplies Programmable triple power supplies ORDERING INFORMATION (1) Part Number The SC1186 linear sections are low dropout regulators with short circuit protection, supplying 1.5V for GTL bus and 2.5V for non-GTL I/O. The Reference voltage is made available for external linear regulators. PIN CONFIGURATION SC1186 Linear Voltage Package SC1186CSW SO-24 Temp. Range (T J) 1.5V/2.5V 0° to 125°C Note: (1) Add suffix ‘TR’ for tape and reel. BLOCK DIAGRAM VCC Top View CS- CS+ EN CURRENT LIMIT AGND GATE1 LDOS1 LDOS2 VCC REF LDOEN CSCS+ PGNDH DH PGNDL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GATE2 LDOV VID0 VID1 VID2 VID3 VID4 VOSENSE EN BSTH BSTL DL REF BSTH + 70mV - VID4 VID3 VID2 VID1 VID0 LEVEL SHIFT AND HIGH SIDE DRIVE + ERROR AMP PGNDH VOSENSE R Q OSCILLATOR AGND SHOOT-THRU CONTROL S BSTL LDOEN LDOS1 GATE1 2.5V FET CONTROLLER SYNCHRONOUS MOSFET DRIVE 1.5V FET CONTROLLER 1.265V REF (24 Pin SOIC) DL PGNDL LDOV REF GATE2 LDOS2 Pentium is a registered trademark of Intel Corporation © 1999 SEMTECH CORP. DH + D/A 1 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER SC1186 PRELIMINARY - December 2, 1999 ABSOLUTE MAXIMUM RATINGS Parameter VCC to GND PGND to GND BST to GND Operating Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 seconds Thermal Impedance Junction to Ambient Symbol VIN Thermal Impedance Junction to Case TA TJ TSTG TL θJA Maximum -0.3 to +7 ±1 -0.3 to +15 0 to +70 0 to +125 -65 to +150 300 80 Units V V V °C °C °C °C °C/W θJC 25 °C/W ELECTRICAL CHARACTERISTICS Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70°C PARAMETER Switching Section Output Voltage Supply Voltage Supply Current Load Regulation Line Regulation Current Limit Voltage Oscillator Frequency Oscillator Max Duty Cycle Peak DH Sink/Source Current Peak DL Sink/Source Current Gain (AOL) VID Source Current VID Leakage Power Good Threshold Voltage Dead Time Linear Sections Quiescent Current Output Voltage LDO1 Output Voltage LDO2 Reference Voltage Gain (AOL) Load Regulation Line Regulation Output Impedance CONDITIONS MIN IO = 2A in Application Circuit VCC VCC = 5.0V IO = 0.8A to 15A See Output Voltage Table 4.5 7 V 8 15 mA 1 % ±0.15 % 60 70 85 mV 120 140 160 kHz 90 95 % 1 A 100 mA 1 A 100 mA BSTH-DH = 4.5V, DH-PGNDH = 3.3V DH-PGNDH = 1.5V BSTL-DL = 4.5V, DL-PGNDL = 3.3V DL-PGNDL = 1.5V VOSENSE to VO VIDx ≤ 2.4V VIDx = 5V 1 88 40 LDOV = 12V Iref ≤ 100µA LDOS (1,2) to GATE (1,2) IO = 0 to 8A VGATE = 6.5V TYP MAX 35 10 10 112 100 5 2.493 2.525 2.556 1.496 1.515 1.534 1.246 1.265 1.284 90 0.3 0.3 1 1.5 UNITS dB µA µA % ns mA V V V dB % % kΩ 2 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER SC1186 PRELIMINARY - December 2, 1999 ELECTRICAL CHARACTERISTICS (Cont.) Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70°C PARAMETER LDOV Undervoltage Lockout CONDITIONS MIN 6.5 LDOEN Threshold TYP 8.0 1.3 LDOEN Sink Current Overcurrent Trip Voltage LDOEN = 3.3V LDOEN = 0V % of Vo set point 1.9 V 20 0.01 -200 40 1.0 -300 60 µA µA % 1 5 60 ms 0.5 4 6 ms 80 300 750 kΩ Power-up Output Short Circuit Immunity Output Short Circuit Glitch Immunity Gate Pulldown Impedance GATE(1,2)-AGND;VCC=BST=0V VOSENSE Impedance MAX UNITS 10 V 10 kΩ PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name AGND GATE1 LDOS1 LDOS2 VCC REF LDOEN CSCS+ PGNDH DH PGNDL DL BSTL BSTH (1) EN 17 18 19 20 21 22 23 24 VOSENSE (1) VID4 (1) VID3 (1) VID2 (1) VID1 (1) VID0 LDOV GATE2 Pin Function Small Signal Analog and Digital Ground Gate Drive Output LDO1 Sense Input for LDO1 Sense Input for LDO2 Input Voltage Buffered Reference Voltage output LDO Supply Monitor. Current Sense Input (negative) Current Sense Input (positive) Power Ground for High Side Switch High Side Driver Output Power Ground for Low Side Switch Low Side Driver Output Supply for Low Side Driver Supply for High Side Driver Logic low shuts down the converter; High or open for normal operation. Top end of internal feedback chain Programming Input (MSB) Programming Input Programming Input Programming Input Programming Input (LSB) +12V for LDO section Gate Drive Output LDO2 Top View AGND GATE1 LDOS1 LDOS2 VCC REF LDOEN CSCS+ PGNDH DH PGNDL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GATE2 LDOV VID0 VID1 VID2 VID3 VID4 VOSENSE EN BSTH BSTL DL (24 Pin SOIC) Note: (1) All logic level inputs and outputs are open collector TTL compatible. 3 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER SC1186 PRELIMINARY - December 2, 1999 OUTPUT VOLTAGE Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; = 0°C < Tj < 85°C PARAMETER Output Voltage VID 43210 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 MIN Standard TYP MAX UNITS 1.277 1.326 1.375 1.424 1.478 1.527 1.576 1.625 1.675 1.724 1.782 1.832 1.881 1.931 1.980 2.030 1.970 2.069 2.167 2.266 2.364 2.463 2.561 2.660 2.758 2.842 2.940 3.038 3.136 3.234 3.332 3.430 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000 2.050 2.000 2.100 2.200 2.300 2.400 2.500 2.600 2.700 2.800 2.900 3.000 3.100 3.200 3.300 3.400 3.500 1.323 1.374 1.425 1.476 1.523 1.573 1.624 1.675 1.726 1.776 1.818 1.869 1.919 1.970 2.020 2.071 2.030 2.132 2.233 2.335 2.436 2.538 2.639 2.741 2.842 2.958 3.060 3.162 3.264 3.366 3.468 3.570 V 4 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 © 1999 SEMTECH CORP. VID4 VID3 VID2 VID1 VID0 3.3V + 330uF C21 C5 0.1uF 19 20 21 22 6 5 4 2 24 12 1 10 R1 16 C3 1500uF + EN C2 1500uF + REF C1 0.1uF 5V 12V Q4 IRFZ14S SC1186CSW LDOS2 GATE1 GATE2 PGNDL AGND EN VID3 VID2 VID1 VID0 REF VCC U1 + 3 23 14 13 10 11 15 18 7 17 8 9 C9 1000uF LDOS1 LDOV BSTL DL PGNDH DH BSTH VID4 LDOEN VOSENSE CS- CS+ Q2 IRL34025 4uH L1 Q1 IRL34025 0.1uF C13 IRLML2803 Q3 R4 5mOhm 1.00k R6 C14 1500uF + + C15 1500uF 2.32k R5 1500uF C16 + + + C17 1500uF C11 330uF C18 0.1uF 1.5V 2.5V GND VCC_CORE PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER SC1186 PRELIMINARY - December 2, 1999 APPLICATION CIRCUIT 5 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER SC1186 PRELIMINARY - December 2, 1999 MATERIALS LIST Qty. Reference Part/Description Vendor Notes 4 C1,C5,C13,C18 0.1µF Ceramic Various 6 C2,C3,C14-C17 1500µF/6.3V SANYO 1 C9 1000µF 2 C11,C21 330µF/6.3V 1 L1 4µH 2 Q1,Q2 See notes See notes FET selection requires trade-off between efficiency and cost. Absolute maximum RDS(ON) = 22 mΩ for Q1,Q2 1 Q3 IRLML2803 IR .25Ω 30V SOT23 (or equivalent) 1 Q4 IRFZ14S IR Or equivalent 1 R4 5mΩ IRC OAR-1 Series 1 R5 2.32kΩ, 1%, 1/8W Various 1 R6 1kΩ, 1%, 1/8W Various 1 R1 10Ω, 5%, 1/8W Various 1 U1 SC1186CSW SEMTECH MV-GX or equiv. Low ESR Various 8 Turns 16AWG on MICROMETALS T50-52D core 6 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER SC1186 PRELIMINARY - December 2, 1999 96% Efficiency (%) 92% 88% 84% Vo=2.8V Vo=2.0V Vo=2.5V 80% 76% 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 Io (Amps) Typical Efficiency (Switching section) Typical Ripple, Vo=2.0V, Io=10A Output Voltage Output Current 5A/div Transient Response Vo=2.4V, Io=300mA to 15A 2.5V Linear Short circuit output response 7 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER SC1186 PRELIMINARY - December 2, 1999 as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. LAYOUT GUIDELINES Careful attention to layout requirements are necessary for successful implementation of the SC1186 PWM controller. High currents switching at 140kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom FET ground. 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. The connection between the output inductor and the sense resistor should be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length is not so important, however adding unnecessary impedance will reduce efficiency. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept 12V IN 5V 10 1 2 3 4 0.1uF 5 6 0.1uF 7 8 9 10 11 12 AGND GATE2 GATE1 LDOV LDOS1 VID0 LDOS2 VID1 VCC VID2 REF VID3 LDOEN VID4 CS- VOSENSE CS+ EN PGNDH BSTH DH BSTL PGNDL DL 24 23 2.32k 22 Cin 21 Q1 + 1.00k 20 5mOhm Vout 19 4uH 18 + Q2 Cout 17 16 15 14 13 SC1186 Heavy lines indicate 3.3V Vo Lin1 Q3 high current paths. + + Cout Lin1 Cin Lin Vo Lin2 Q4 + Cout Lin2 Layout diagram for the SC1186 8 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER SC1186 PRELIMINARY - December 2, 1999 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC1186 is best placed over a quiet ground plane area, avoid pulse currents in the Cin, Q1, Q2 loop flowing in this area. PGNDH and PGNDL should be returned to the ground plane close to the package. The AGND pin should be connected to the ground side of (one of) the output capacitor(s). If this is not possible, the AGND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should AGND be returned to a ground inside the Cin, Q1, Q2 loop. 5V supply through a 10Ω resistor, the Vcc pin should be decoupled directly to AGND by a 0.1µF ceramic capacitor, trace lengths should be as short as possible. 7) The Current Sense resistor and the divider across it should form as small a loop as possible, the traces running back to CS+ and CS- on the SC1186 should run parallel and close to each other. The 0.1µF capacitor should be mounted as close to the CS+ and CS- pins as possible. 8) Ideally, the grounds for the two LDO sections should be returned to the ground side of (one of) the output capacitor(s). 6) Vcc for the SC1186 should be supplied from the 5V + Vout + Currents in various parts of the power section 9 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER SC1186 PRELIMINARY - December 2, 1999 fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence enSWITCHING SECTION suring a good recovery from transient with no additional OUTPUT CAPACITORS - Selection begins with the excursions. most critical component. Because of fast transient load We must also be concerned with ripple current in the current requirements in modern microprocessor core output inductor and a general rule of thumb has been to supplies, the output capacitors must supply all transient allow 10% of maximum output current as ripple current. load current requirements until the current in the output Note that most of the output voltage ripple is produced inductor ramps up to the new level. Output capacitor by the inductor ripple current flowing in the output caESR is therefore one of the most important criteria. The pacitor ESR. Ripple current can be calculated from: maximum ESR can be simply calculated from: VIN ILRIPPLE= Vt 4 L ⋅ ⋅ fOSC R ESR ≤ COMPONENT SELECTION It Ripple current allowance will define the minimum permitted inductor value. Where Vt = Maximum transient voltage excursion I t = Transient current step For example, to meet a 100mV transient limit with a 10A load step, the output capacitor ESR must be less than 10mΩ. To meet this kind of ESR level, there are three available capacitor technologies. Each Capacitor Technology C (µF) ESR (mΩ) PCOND = I2O ⋅ R DS( on ) ⋅ δ Total Qty. Rqd. C (µF) ESR (mΩ) Low ESR Tantalum 330 60 6 2000 10 OS-CON 330 25 3 990 8.3 1500 44 5 7500 8.8 Low ESR Aluminum The choice of which to use is simply a cost/performance issue, with Low ESR Aluminum being the cheapest, but taking up the most space. INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above. The maximum inductor value may be calculated from: L≤ POWER FETS - The FETs are chosen based on several criteria with probably the most important being power dissipation and power handling capability. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses. a) Conduction losses are simply calculated as: R ESR C (VIN − VO ) It The calculated maximum inductor value assumes 100% duty cycle, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp where δ = duty cycle ≈ VO VIN b) Switching losses can be estimated by assuming a switching time, if we assume 100ns then: PSW = IO ⋅ VIN ⋅ 10 − 2 or more generally, PSW = IO ⋅ VIN ⋅ ( t r + t f ) ⋅ fOSC 4 c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be: PRR = Q RR ⋅ VIN ⋅ f OSC To a first order approximation, it is convenient to only consider conduction losses to determine FET suitability. For a 5V in; 2.8V out at 14.2A requirement, typical FET losses would be: 10 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER SC1186 PRELIMINARY - December 2, 1999 Using 1.5X Room temp RDS(ON) to allow for temperature rise. FET type RDS(on) (mΩ) PD (W) Package IRL34025 15 1.69 D PAK IRL2203 10.5 1.19 D PAK Si4410 20 2.26 SO-8 2 2 BOTTOM FET - Bottom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it, resulting in low switching losses. Conduction losses for the FET can be determined by: PCOND = I2O ⋅ RDS( on) ⋅ (1− δ) For the example above: FET type RDS(on) (mΩ) PD (W) Package IRL34025 15 1.33 D PAK IRL2203 10.5 0.93 D PAK Si4410 20 1.77 SO-8 2 2 Each of the package types has a characteristic thermal impedance, for the TO-220 package, thermal impedance is mostly determined by the heatsink used. For the surface mount packages on double sided FR4, 2 oz printed circuit board material, thermal impedances of o 2 o 40 C/W for the D PAK and 80 C/W for the SO-8 are readily achievable. The corresponding temperature rise is detailed below: o Temperature rise ( C) FET type Top FET Bottom FET IRL34025 67.6 53.2 IRL2203 47.6 37.2 Si4410 180.8 141.6 INPUT CAPACITORS - since the RMS ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size. SHORT CIRCUIT PROTECTION - LINEARS The Short circuit feature on the linear controllers is implemented by using the Rds(on) of the FETs. As output current increases, the regulation loop maintains the output voltage by turning the FET on more and more. Eventually, as the Rds(on) limit is reached, the FET will be unably to turn on more fully, and output voltage will start to fall. When the output voltage falls to approximately 50% of nominal, the LDO controller is latched off, setting output voltage to 0. Power must be cycled to reset the latch. To prevent false latching due to capacitor inrush currents or low supply rails, the current limit latch is initially disabled. It is enabled at a preset time (nominally 2mS) after both the LDOV and LDOEN rails rise above their lockout points. To be most effective, the linear FET Rds(on) should not be selected artificially low, the FET should be chosen so that, at maximum required current, it is almost fully turned on If, for example, a linear supply of 1.5V at 4A is required from a 3.3V ± 5% rail, max allowable Rds(on) would be. Rds(on)max = (0.95*3.3-1.5)/4 ≈ 400mΩ To allow for temperature effects 200mΩ would be a suitable room temperature maximum, allowing a peak short circuit current of approximately 15A for a short time before shutdown. It is apparent that single SO-8 Si4410 are not adequate for this application, but by using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4. 11 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER SC1186 PRELIMINARY - December 2, 1999 OUTLINE DRAWING JEDEC MS-013AD B17104B ECN99-600 9-22-99 ECN99-719 12-2-99 12 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320