TM 500mA SmartLDO With Power Up Signal Sequencing PRELIMINARY - January 17, 2000 SC1545 TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION FEATURES The SC1545 was designed for instantly available motherboard applications. As part of the Semtech family of SmartLDO’s it provides additional control functions not available in a standard LDO. • • The device provides the capability to control three separate supplies. There is an on-board 500mA, 2.5V LDO with current limit protection, and drive pins for an N-channel MOSFET and a P-channel MOSFET. Internal logic circuitry ensures that the system starts up in a controlled manner, and that the correct outputs are enabled during specific sequences of BF_CUT and SLP. The LDO draws its power from the 5V standby supply, and the N-channel MOSFET drive is derived from the 12V supply. 500mA LDO with Over Current Protection (OCP) ±2.5% LDO regulation over line, load and temperature Power sequencing for three supplies • APPLICATIONS • • • Instantly available motherboards Embedded systems Desktop computers ORDERING INFORMATION The SC1545 is available in the surface mount SO-8 package. (1) Part Number Package SC1545CS SO-8 Note: (1) Add suffix ‘TR’ for tape and reel packaging. TYPICAL APPLICATION CIRCUIT 2.5V IN 3.3V IN Q1 Q2 3.3V OUT 2.5V OUT Si4410 C1 2 x 100uF IRLMS6802 C2 100uF C3 2 x 100uF C4 100uF U1 1 2.5V OUT 2 3 4 C5 10uF VO 5VSTBY GND 12VIN PDR BF_CUT NDR SC1545 SLP 8 5V STANDBY 7 12V IN 6 BF_CUT 5 SLP C6 1uF C7 0.1uF 1 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 TM 500mA SmartLDO With Power Up Signal Sequencing SC1545 PRELIMINARY - January 17, 2000 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Maximum Units 12V Input Voltage Range 12VIN -0.3 to +15 V 5V Input Voltage Range 5VSTBY -0.3 to +7 V P-channel MOSFET Gate Drive PDR -0.3 to 5VSTBY V N-channel MOSFET Gate Drive NDR -0.3 to 12VIN V -0.3 to +7 V Input Pins Operating Ambient Temperature Range TA 0 to +70 °C Operating Junction Temperature Range TJ 0 to +125 °C Storage Temperature Range TSTG -65 to +150 °C Lead Temperature (Soldering) 10 Sec TLEAD 300 °C θJC 47 °C/W θJA 65 °C/W ESD 2 kV Thermal Impedance Junction to Case Thermal Impedance Junction to Ambient (1) ESD Rating Note: (1) 2 inch square of 1/16” FR-4, double sided, 1 oz. minimum copper weight. ELECTRICAL CHARACTERISTICS Unless specified, 12VIN = 12V, 5VSTBY = 5V, CO = 100µF min., TA = 25°C. Values in bold apply over full operating temperature range. Parameter Symbol Test Conditions MIN TYP MAX Units 12VIN Supply Voltage Quiescent Current 12VIN 11.28 12.00 12.72 V IQ12 800 µA 1000 1200 5VSTBY Supply Voltage Quiescent Current 5VSTBY IQ5 4.7 LDO ON 5.0 5.3 9.5 11 12 LDO OFF 3.0 V mA 4.0 5.0 Undervoltage Lockout (5V) UVLO Threshold Hysteresis Logic Reset Threshold UVLO 5VSTBY rising 4.1 4.3 4.5 V 5VSTBY falling 3.9 4.1 4.3 V HYST RST 200 1.5 2.0 mV 2.5 V 2 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 TM 500mA SmartLDO With Power Up Signal Sequencing SC1545 PRELIMINARY - January 17, 2000 ELECTRICAL CHARACTERISTICS (Cont.) Unless specified, 12VIN = 12V, 5VSTBY = 5V, CO = 100µF min., TA = 25°C. Values in bold apply over full operating temperature range. Parameter Symbol Test Conditions VO 4.7V ≤ 5VSTBY ≤ 5.3V, MIN TYP MAX Units VO LDO Output Voltage 1mA ≤ IO ≤ 500mA LDO Output Voltage During (1) Load Transients (2) Time To Regulation VO(T) Load step between 0mA and 500mA at 8A/µs max. -1.5% 2.525 +1.5% -2.5% V +2.5% -3.0% 2.525 +3.0% tREG 5 V µs Inputs (BF_CUT & SLP) Input Resistance RIN High Level Input Voltage VIH Low Level Input Voltage VIL BF_CUT = SLP = 5V 1.0 10.0 MΩ V 2.0 0.8 V NDR Peak Drive Current INDR(PK) Sinking: NDR = 0.5V Sourcing: NDR = 10V 30 Output Voltage VNDR Full ON, INDR = 100µA 10 Drive Low Delay tDL(N) Measured from BF_CUT threshold to 90% of NDR 150 ns Fall Time tf(N) Measured from 90% to 10% 1.0 µs tDH(N) Measured from BF_CUT/SLP threshold to 10% of NDR 300 ns tr(N) Measured from 10% to 90% 1.0 µs IPDR(PK) Sinking: PDR = 0.5V Sourcing: PDR = 3.5V 30 Output Voltage VPDR Full ON, IPDR = 100µA 3.5 Drive Low Delay tDL(P) Measured from BF_CUT threshold to 90% of PDR 150 ns Fall Time tf(P) Measured from 90% to 10% 1.0 µs tDH(P) Measured from BF_CUT/SLP threshold to 10% of PDR 300 ns tr(P) Measured from 10% to 90% 1.0 µs ICL VO = 0V Drive High Delay Rise Time mA 12 V PDR Peak Drive Current Drive High Delay Rise Time mA 5 V Overcurrent Protection Current Limit Threshold 550 mA NOTES: (1) The LDO will bring the output back to within the regular VO limits in less than 10µs. (2) External 2.5V ± 2.5% applied at output, turning off when NDR goes low. CO = 100µF to 400µF, IO = 50mA to 200mA. 3 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 TM 500mA SmartLDO With Power Up Signal Sequencing SC1545 PRELIMINARY - January 17, 2000 BLOCK DIAGRAM PIN CONFIGURATION PIN DESCRIPTION Pin Top View Pin Name Pin Function 1 VO 2 GND Logic and power ground. 3 PDR Gate drive signal for P-channel MOSFETs. 4 NDR Gate drive signal for N-channel MOSFETs. 5 SLP Control input #1. 6 7 8 LDO 2.5V output. BF_CUT Control input #2. 12VIN +12V input supply. Used for generating NDR only. 5VSTBY +5V input supply. SOIC-8 4 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 TM 500mA SmartLDO With Power Up Signal Sequencing SC1545 PRELIMINARY - January 17, 2000 TYPICAL CHARACTERISTICS 12VIN Quiescent Current vs. Junction Temperature 5VSTBY Quiescent Current (ON) vs. Junction Temperature 1000 10.0 5VSTBY = 5V 9.5 800 9.0 700 8.5 IQ5(ON) (mA) IQ12 (µA) 12VIN = 12V 900 600 500 400 8.0 7.5 7.0 300 6.5 200 6.0 100 5.5 0 5.0 0 25 50 75 100 125 0 25 50 75 100 TJ (°C) TJ (°C) 5VSTBY Quiescent Current (OFF) vs. Junction Temperature 5VSTBY Under Voltage Lockout vs. Junction Temperature 5.0 125 4.5 4.5 4.0 4.4 3.5 4.4 3.0 4.3 UVLO (V) IQ5(OFF) (mA) 5VSTBY = 5V 4.5 2.5 2.0 4.3 4.2 1.5 4.2 1.0 4.1 0.5 4.1 0.0 5VSTBY RISING 5VSTBY FALLING 4.0 0 25 50 75 100 125 0 25 50 TJ (°C) LDO Output Voltage vs. Junction Temperature 100 125 LDO Line Regulation vs. Junction Temperature 2.550 10 5VSTBY = 4.7V to 5.3V 5VSTBY = 5V 2.545 9 2.540 8 2.535 7 REGLINE (mV) IO = 1mA 2.530 VO (V) 75 TJ (°C) 2.525 2.520 2.515 IO = 500mA 6 5 4 3 2.510 2 2.505 1 2.500 0 0 25 50 75 TJ (°C) 100 125 0 25 50 75 100 125 TJ (°C) 5 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 TM 500mA SmartLDO With Power Up Signal Sequencing SC1545 PRELIMINARY - January 17, 2000 TYPICAL CHARACTERISTICS (Cont.) VDO Current Limit vs. Junction Temperature 1000 VO = 0V 900 800 ICL (mA) 700 600 500 400 300 200 100 0 0 25 50 75 100 125 TJ (°C) TIMING DIAGRAMS Power up signal sequencing is shown in Figure 1. BF_CUT, PDR and NDR follow the power rails up to their final values. SLP goes to its high value when the power rails have stabilized, ~25msec after power on. BF_CUT is pulled low a period T1 after SLP goes high. T1 can be as short as 1msec. Typical measured values are ~200msec. The 2.5V LDO output stays OFF through this sequence. Figure 1: Power Up Signal Sequencing 6 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 TM 500mA SmartLDO With Power Up Signal Sequencing SC1545 PRELIMINARY - January 17, 2000 TIMING DIAGRAMS (Cont.) After power up, there are two possible signal sequences that the device will see. The first sequence is with SLP staying HIGH and BF_CUT transitioning from LOW to HIGH, remaining HIGH for an undetermined period and then going back to LOW. At this point, the system state is back to where it was at the end of the power up sequence. The sequence is shown in Figure 2 (below). During these BF_CUT transitions, the propagation delays, rise and fall times and going into regulation times for PDR, NDR and VO are described in Electrical Characteristics on page 3. The first sequence can start at any time after the end of the power up sequence. Figure 2: 1st Sequence Timing Signal sequencing for the second possible sequence is shown in Figure 3. BF_CUT goes from LOW to HIGH and SLP goes from HIGH to LOW, 30µsec to 65µsec (T3) later. When BF_CUT goes HIGH, PDR and NDR go LOW and the 2.5V LDO turns ON. When SLP goes LOW, PDR and NDR return to HIGH and the 2.5V LDO turns OFF. BF_CUT will stay HIGH and SLP will stay low for an undetermined time, after which SLP will go HIGH. A minimum of 1msec (T4) later, BF_CUT will go LOW and the system is back at the end of the power up sequence. Typical measured values of T4 are ~250msec. During all transitions, the propagation delays, rise and fall times, and going into regulation times for PDR, NDR and 2.5V LDO are described in Electrical Characteristics on page 3. The second sequence can start at any time after the end of the power up sequence. Figure 3: 2nd Sequence Timing 7 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 TM 500mA SmartLDO With Power Up Signal Sequencing SC1545 PRELIMINARY - January 17, 2000 OUTLINE DRAWING JEDEC REF: MS-012AA MINIMUM LAND PATTERN - SO-8 ECN99-694 ECN00-831 8 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320