SK10/100E016 8-Bit Synchronous Binary Up Counter HIGH-PERFORMANCE PRODUCTS Description Features • • • • • • • • • • • The SK10/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. The counter features internal feedback of TC*, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC* feedback is disabled, and counting proceeds continuously, with TC* going LOW to indicate an all-one state. When TCLD is HIGH, the TC* feedback causes the counter to automatically reload upon TC* = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated. 700 MHz Min Count Frequency 1000 ps CLK to Q, TC* Internal TC* Feedback (Gated) 8-Bit Fully Synchronous Counting and TC* Generation Asynchronous Master Reset Internal 75 kΩ Input Pulldown Resistors Extended 100E VEE Range of –4.2V to –5.46V Fully Compatible with MC10/100E016 Available in 28-Pin PLCC Package ESD Protection of >4000V Functional Block Diagram 8 Bit Binary Counter - Logic Counter Q0 Q1 Q7 PE TCLD QOM CE* SLAVE MASTER BIT 0 QOM* PO CE* CE* Q0* Q1* Q2* Q3* Q4* Q5* Q6* BIT 1 Q0* P1 BIT 7 P7 MR CLK BITS 2-6 TC* 5 Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay. Revision 1/February 13, 2001 1 www.semtech.com SK10/100E016 HIGH-PERFORMANCE PRODUCTS PIN Description Pinout PE* CE* P7 P6 P5 V CCO TC* Function Table 25 24 23 22 21 20 19 CE* PE* TCLD MR CLK Function X L X L Z Load Parallel (Pn to Qn) L H L L Z Continuous Count MR 26 18 Q7 CLK 27 17 Q6 L H H L Z Count; Load Parallel on TC* = LOW TCLD 28 16 V CC H H X L Z Hold 15 Q5 X X X L ZZ Masters Respond, Slaves Hold X X X H X Reset (Qn: = LOW, TC*: = HIGH) 28 Lead PLCC V EE 1 (Top View) NC 2 14 V CCO P0 3 13 Q4 P1 4 12 Q3 11 Q2 10 Q1 9 Q0 8 V CCO 7 P4 6 P3 P2 5 Pin Names Pin Function P0 - P7 Parallel Data (Preset) Inputs Q0 - Q7 Data Outputs CE* Count Enable Control Input PE* Parallel Load Enable Control Input MR Master Reset CLK Clock TC* Terminal Count Output TCLD TC-Load Control Input Revision 1/February 13, 2001 2 www.semtech.com SK10/100E016 HIGH-PERFORMANCE PRODUCTS Application Information Function Table Funct i on PE * CE * MR T CL D CL K P7- P4 P3 P2 P1 P0 Q7 - Q4 Q3 Q2 Q1 Q0 TC Load L X L X Z H H H L L H H H L L H Count H L L L Z X X X X X H H H L H H H L L L Z X X X X X H H H H L H H L L L Z X X X X X H H H H H L H L L L Z H H H L L H H H L L H Load L X L X Z H H H L L H H H L L H Ho l d H H L X Z X X X X X H H H L L H H H L X Z X X X X X H H H L L H L o a d On H L L H Z H L H H L H H H L H H Ter minal H L L H Z H L H H L H H H H L H Count H L L H Z H L H H L H H H H H L H L L H Z H L H H L H L H H L H H L L H Z H L H H L H L H H H H H L L H Z H L H H L H H L L L H X X H X X X X X X X L L L L L G Reset Cascading Multiple E016 Devices For applications which call for larger than 8-bit counters, multiple E016s can be tied together to achieve very wide bit width counters. The active low terminal count (TC*) output and count enable input (CE*) greatly facilitate the cascading of E016 devices. Two E016s can be cascaded without the need for external gating; however, for counters wider than 16 bits, external OR gates are necessary for cascade implementations. Figure 3 below illustrates the cascading of 4 E016s to build a 32-bit high frequency counter. Note that the E101 gates are used to OR the terminal count outputs of the lower order E016s to control the counting operation of the higher order bits. When the terminal count of the preceding device (or devices) goes low (the counter reaches an all 1s state), the more significant E016 is set in its count mode and will count one binary digit upon the next positive clock transition. In addition, the preceding devices will also count one bit, sending their terminal count outputs back to a high state, disabling the count operation of the more significant counters, and placing them back into hold modes. Therefore, for an E016 in the chain to count, Revision 1/February 13, 2001 all of the lower order terminal count outputs must be in the low state. The bit width of the counter can be increased or decreased by simply adding or subtracting E016 devices from Figure 3 and maintaining the logic pattern illustrated in the same figure. The maximum frequency of operation for the cascaded counter chain is set by the propagation delay of the TC* output, the necessary setup time of the CE* input, and the propagation delay through the OR gate controlling it (for 16-bit counters the limitation is only the TC* propagation delay and the CE* setup time). Figure 3 shows EL01 gates used to control the count enable inputs; however, if the frequency of operation is lower, a lower ECL OR gate can be used. Using the worst case guarantees for these parameters, the maximum count frequency for a greater than 16-bit counter is 500 MHz, and for a 16-bit counter is 625 MHz. Note that this assumes the trace delay between the TC* outputs and the CE* inputs are negligible. If this is not the case, estimates of these delays need to be added to the calculations. 3 www.semtech.com SK10/100E016 HIGH-PERFORMANCE PRODUCTS Application Information (continued) LOAD Q0 ® Q7 CE* Q0 PE* CE* E016 LSB CLK P0 ® Q7 Q0 PE* CE* E016 TC* CLK ® P7 P0 ® Q7 Q0 PE* CE* E016 TC* CLK ® P7 EL01 P0 ® Q7 PE* E016 MSB TC* CLK ® P7 EL01 P0 TC* ® P7 CLOCK Figure 3. 32-Bit Cascaded E016 Counter Programmable Divider The E016 has been designed with a control pin which makes it ideal for use as an 8-bit programmable divider. The TCLD pin (load on terminal count) when asserted reloads the data present at the parallel input pin (Pn’s) upon reaching terminal count (an all 1s state on the outputs). Because this feedback is built internal to the chip, the programmable division operation will run at very nearly the same frequency as the maximum counting frequency of the device. Figure 4 below illustrates the input conditions necessary for utilizing the E016 as a programmable divider set up to divide by 113. H L L L H H H H P7 P6 P5 P4 P3 P2 P1 P0 H PE* L CE* H TCLD TC* CLK Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Figure 4. Mod 2 to 256 Programmable Divider To determine what value to load into the device to accomplish the desired division, the designer simply subtracts the binary equivalent of the desired divide ratio from the binary value for 256. As an example for a divide ratio of 113: Revision 1/February 13, 2001 4 Pn’s = 256 – 113 = 8F16 = 1000 1111 where: PO = LSB and P7 = MSB Forcing this input condition as per the setup in Figure 4 will result in the waveforms of Figure 5. Note that the TC* output is used as the divide output and the pulse duration is equal to a full clock period. For even divide ratios, twice the desired divide ratio can be loaded into the E016, and the TC* output can feed the clock input of a toggle flip-flop to create a signal divided as desired with a 50% duty cycle. Preset Data Inputs Di v i d e Ra t i o P7 P6 P5 P4 P3 P2 P1 P0 2 H H H H H H H L 3 H H H H H H L H 4 H H H H H H L L 5 H H H H H L H H l l l l l l l l l l l l l l l l l l 112 H L L H L L L L 113 H L L L H H H H 114 H L L L H H H L l l l l l l l l l l l l l l l l l l 254 L L L L L L H L 255 L L L L L L L H 256 L L L L L L L L www.semtech.com SK10/100E016 HIGH-PERFORMANCE PRODUCTS Application Information (continued) A single E016 can be used to divide by any ratio from 2 to 256 inclusive. If divide ratios of greater than 256 are needed, multiple E016s can be cascaded in a manner similar to that already discussed. When E016s are cascaded to build larger dividers, the TCLD pin will no longer provide a means for loading on terminal count. Because one does not want to reload the counters until all of the devices in the chain have reached terminal count, external gating of the TC* pins must be used for multiple E016 divider chains. Figure 6 shows a typical block diagram of a 32-bit divider chain. Once again, to maximize the frequency of operation, EL01 OR gates were used. For lower frequency applications, a slower OR gate could replace the EL01. Note that for a 16-bit divider, the OR function feeding the PE* (program enable) input CANNOT be placed by a wire OR tie as the TC* output of the least significant E016 must also feed the CE* input of the most significant E016. If the two TC* outputs were OR tied, the cascaded count operation would not operate properly. Because, in the cascaded form, the PE* feedback is external and requires external gating, the maximum frequency of operation will be significantly less than the same operation in a single device. LOAD 1001 0000 1001 0001 Maximizing E016 Count Frequency The E016 device produces 9 fast transitioning singleended outputs, thus VCC noise can become significant in situations where all of the outputs switch simultaneously in the same direction. This VCC noise can negatively impact the maximum frequency of operation of the device. Since the device does not need to have the Q outputs terminated to count properly, it is recommended that if the outputs are not going to be used in the rest of the system, they should be terminated. Not terminating the unused outputs will not only cut down the VCC noise generated, but will also save in total system power dissipation. Following these guidelines will allow designers to either be more aggressive in their designs or provide them with an extra margin to the published databook specifications. 1111 1100 1111 1101 1111 1110 1111 1111 LOAD CLOCK PE* TC* DIVIDE BY 113 Figure 5. Divide by 113 E016 Programmable Divider Waveforms Revision 1/February 13, 2001 5 www.semtech.com SK10/100E016 HIGH-PERFORMANCE PRODUCTS Application Information (continued) EL01 Q0 ® Q7 CE* PE* E016 LSB CLK Q0 ® Q7 CE* Q0 ® Q7 PE* CE* E016 TC* P0 ® P7 CLK Q0 ® Q7 PE* CE* E016 TC* P0 ® P7 CLK EL01 PE* E016 MSB TC* P0 ® P7 CLK EL01 TC* P0 ® P7 CLOCK Figure 6. 32-Bit Cascaded E016 Programmable Divider Revision 1/February 13, 2001 6 www.semtech.com SK10/100E016 HIGH-PERFORMANCE PRODUCTS Package Information Y BRK –N– B D 0.007 (0.180) U M T L-M N S 0.007 (0.180) M T L - M S S N S + PIN–L–Descriptions –M– Z D W + G1 X 0.010 (0.250) S T L-M S N S V 28 1 Z C A 0.007 (0.180) M R 0.007 (0.180) M T L–M T L–M S S N 0.007(0.180) M T L – M S N S H S NS K1 + + E 0.004 (0.100) G J –T– SEATING PLANE G1 0.010 (0.250) S T L–M S N S K VIEW S 0.007 (0.180) M T L – M F NOTES: 1. Datums -L-, -M-, and -N- determined where top of lead shoulder exits plastic body at mold parting line. 2. DIM G1, true position to be measured at Datum -T-, Seating Plane. 3. DIM R and U do not include mold flash. Allowable mold flash is 0.010 (0.250) per side. 4. Dimensioning and tolerancing per ANSI Y14.5M, 1982. 5. Controlling Dimension: Inch. 6. The package top may be smaller than the package bottom by up to 0.012 (0.300). Dimensions R and U are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. Dimension H does not include Dambar protrusion or intrusion. The Dambar protrusion(s) shall not cause the H dimension to be greater than 0.037 (0.940). The Dambar intrusion(s) shall not cause the H dimension to be smaller than 0.025 (0.635). Revision 1/February 13, 2001 DI M MIN MAX MIN MAX A 0. 485 0. 495 12. 32 12. 57 B 0. 485 0. 495 12. 32 12. 57 C 0. 165 0. 180 4. 20 4. 57 E 0. 090 0. 110 2. 29 2. 79 F 0. 013 0. 019 0. 33 0. 48 7 0. 050 BSC H 0. 026 N S MILLIMETERS INCHES G S 0. 032 1. 27 BSC 0. 66 0. 81 J 0. 020 -- 0. 51 -- K 0. 025 -- 0. 64 -- R 0. 450 0. 456 11. 43 11. 58 U 0. 450 0. 456 11. 43 11. 58 V 0. 042 0. 048 1. 07 1. 21 W 0. 042 0. 048 1. 07 1. 21 X 0. 042 0. 056 1. 07 1. 42 Y -- 0. 020 -- 0. 50 Z 2o 10o 2o 10o G1 0. 410 0. 430 10. 42 10. 92 K1 0. 040 -- 1. 02 -- www.semtech.com SK10/100E016 HIGH-PERFORMANCE PRODUCTS DC Characteristics SK10/100E016 DC Electrical Characteristics (Notes 1, 2) (VCC – VEE = 4.2V to 5.5V;VCC = VCCO; VOUT Loaded 50Ω Ω to VCC – 2.0V) TA = –40oC Symbol Ch a r a c t e r i s t i c IIH I n p u t HI GH Cu r r e n t I EE Power Supply Cur rent 10E 100E Min Typ TA = 0oC Max Min Typ 150 151 151 TA = +25oC Max Min Typ Max 150 174 185 151 151 TA = +85oC Min Typ Max Un i t 150 µA 174 185 mA mA 150 174 185 151 151 174 185 151 151 AC Characteristics SK10/100E016 AC Electrical Characteristics Ω to VCC – 2.0V) (VCC – VEE = 4.2V to 5.5V;VCC = VCCO; VOUT Loaded 50Ω TA = –40oC Symbol Ch a r a c t e r i s t i c Min Typ f COUNT Maximum Count Frequency 700 900 t PLH t P HL Propagation Delay to Output CLK t o Q MR t o Q CLK t o TC* MR t o T C * 726 666 743 656 855 775 775 738 ts S e t u p T i me Pn CE* PE* TCLD 150 600 600 500 th H o l d T i me Pn CE* PE* TCLD t RR TA = 0oC Max Min Typ 700 900 726 666 743 656 855 775 775 738 - 30 400 400 300 150 600 600 500 350 0 0 100 100 - 400 - 400 - 300 Reset Recover y Time 900 700 t PW Mi n i mu m P u l s e Wi d t h C L K , MR 400 tr, tf Rise/Fall Times (20 - 80%) 231 948 876 926 820 TA = +25oC Max Min Typ 700 900 726 666 743 656 855 775 775 738 - 30 400 400 300 150 600 600 500 350 0 0 100 100 - 400 - 400 - 300 900 700 948 876 926 820 400 306 559 231 TA = +85oC Max Min Typ 700 900 726 666 743 656 855 775 775 738 - 30 400 400 300 150 600 600 500 - 30 400 400 300 ps ps ps ps 350 0 0 100 100 - 400 - 400 - 300 350 0 0 100 100 - 400 - 400 - 300 ps ps ps ps 900 700 900 700 ps 948 876 926 820 400 306 559 235 Max MH z 948 876 926 820 400 318 526 244 Un i t ps ps ps ps ps 330 460 ps Notes: 1. 10E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 2. The same DC parameter values apply across the full VEE range of –4.2 to –5.5V. 100E circuits are designed to meet the DC specifications shown in the table where transverse airflow greater than 500 lfpm is maintained. 3. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data Sheet. 4. For part ordering descriptions, see HPP Part Ordering Information Data Sheet. Revision 1/February 13, 2001 8 www.semtech.com SK10/100E016 HIGH-PERFORMANCE PRODUCTS Ordering Information Or d e r i n g Co d e Package ID Temperature Range SK10E016PJ 28- PLCC I ndust r i al SK10E016PJ T 28- PLCC I ndust r i al SK100E016PJ 28- PLCC I ndust r i al SK100E016PJ T 28- PLCC I ndust r i al Contact Information Division Headquarters 10021 Willow Creek Road San Diego, CA 92131 Phone: (858) 695-1808 FAX: (858) 695-2633 Revision 1/February 13, 2001 Semtech Corporation High-Performance Products Division 9 Marketing Group 1111 Comstock Street Santa Clara, CA 95054 Phone: (408) 566-8776 FAX: (408) 727-8994 www.semtech.com