SEMTECH SK10LVE111E

SEMTECH
Today's Results ...Tomorrow's Vision
Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input
Preliminary Information
SK10LVE111E
SK100LVE111E
October 6, 1999
This document contains information on a new product. The parametric
information, although not fully characterized, is the result of testing
initial devices.
Features
•
•
•
•
•
•
•
•
•
•
•
•
200 ps Part-to-Part Skew
50 ps Output-to-Output Skew
Differential Design
VBB Output
Enable Input
Voltage and Temperature Compensated Outputs
Low Voltage VEE Range of –3,0 to –3.8V
75KΩ Internal Pulldown Resistors
Fully Compatible with Motorola MC100LVE111
Specified Over Industrial Temperature Range:
–40˚C to 85˚C
ESD Protection of >2000V
Available in 28-pin PLCC Package
Low Voltage 1:9 Differential
ECL / PECL Clock Driver
28 Pin
PLCC Package
Description
The SK10/1000LVE111E is a low skew 1-to-9 differential driver
designed with clock distribution in mind. The SK10/
100LVE111E’s function and performance are similar to the
SK100E111, with the added feature of low voltage operation.
It accepts one signal input which can be either differential or
single-ended if the VBB output is used. The signal is fanned
out to 9 identical differential outputs. An enable input is also
provided. A High disables the device by focing all Q outputs
Low and all Q* outputs High.
The device is specifically designed, modeled, and produced
with low skew as the key goal. Optimal design and layout serve
to minimize gate-to-gate skew within a device, and
characterization is used to determine process control limits that
ensure consistent tpd distributions from lot to lot. The net result
is a dependable, guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary
that both sides of the differential output are terminated into 50Ω,
even if only one side is being used. In most applications, all
nine differential pairs will be used and therefore terminated. In
the case where fewer than nine pairs are used, it is necessary
to terminate at least the output pairs on the same package
side as the pair(s) being used on that side in order to maintain
minimum skew. Failure to do this will result in small
degradations of propagation delay (on the order of 10–20ps)
of the output(s) being used which, while not being
catastrophic to most designs, will mean a loss of
skew margin.
The SK10/100LVE111E, as with most other ECL
devices, can be operated from a positive VCC
supply in PECL mode. This allows the LVE111E
to be used for high performance clock distribution
in +3.3V systems. Designers can take advantage
of the LVE111E’s performance to distribute low
skew clocks across the backplane or the board.
In a PECL environment, series or Thevenin line
terminations are typically used as they require no
additional power supplies. For systems
incorporating GTL, parallel termination offers the
lowest power by taking advantage of the 1.2V
supply as a terminating voltage.
SEMTECH
Today's Results ...Tomorrow's Vision
SK10LVE111E
SK100LVE111E
Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input
Q0
Q0*
Q1
Q1*
Pin
Function
IN, IN*
EN*
Q0, Q0* − Q8, Q8*
VBB
Differential Input Pair
Enable
Differential Outputs
VBB Output
Q2
Q2*
Q5
Q5*
Q0*
Q1
VCC0
Q1*
Q2
Q2*
Q4
Q4*
IN
IN*
Q0
Q3
Q3*
25
24
23
22
21
20
19
VEE
26
18
Q3
EN*
27
17
Q3*
IN
28
16
Q4
VCC
1
15
VCC0
IN*
2
14
Q4*
VBB
3
13
Q5
N/C
4
12
Q5*
EN*
Q6
Q6*
28 Lead PLCC
(Top View)
9
10
11
Q6*
8
Q6
7
Q7*
6
VCC0
5
Q8
VBB
Q7
Q8
Q8*
Q8*
Q7
Q7*
Absolute Maximum Ratings (Note 3)
Symbol
Parameter
Rating
Unit
VEE
Power Supply (VCC = 0V)
-4.5 to 0
V
VI
Input Voltage (VCC = 0V)
0 to -4.0
V
IOUT
Output Current:
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
-40 to +85
oC
VEE (note 4)
Operating Range
-3.8 to -3.0
V
Tstore
Storage Temperature Range
-65 to +150
oC
SK10LVE111E
SK100LVE111E
Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input
SEMTECH
Today's Results ...Tomorrow's Vision
SK10LVE111E ECL DC Electrical Characteristics
(VEE = VEE (min) to VEE (max); VCC = GND) (Notes 1 and 4)
TA = –40˚C
Symbol
Characteristic
VOH
Output HIGH Voltage
VOL
Min
Typ
TA = 0˚C
Max
Min
-1135
-890
Output LOW Voltage
-1950
VIH
Input HIGH Voltage
VIL
Typ
TA = +25˚C
Max
Min
-1080
-840
-1650
-1950
-1230
-890
Input LOW Voltage
-1950
VBB
Output Reference Voltage
-1.43
IIH
Input HIGH Current
IIL
Input LOW Current
0.5
IEE
Power Supply Current
35
TA = +85˚C
Max
Min
-1020
-810
-1630
-1950
-1170
-840
-1500
-1950
-1.30
-1.38
150
Max
Unit
-910
-720
mV
-1630
-1950
-1595
mV
-1130
-810
-1060
-720
mV
-1480
-1950
-1480
-1950
-1445
mV
-1.27
-1.35
-1.25
-1.31
-1.19
V
15 0
µA
150
0.5
65
Typ
150
0.5
35
65
Typ
0.3
35
65
µA
35
65
mA
Max
Unit
SK10LVE111E PECL DC Electrical Characteristics
(VCC = VCC (min) to VCC (max); VEE = GND) (Notes 1 and 4)
TA = –40˚C
Symbol
Characteristic
Min
VOH
Output HIGH Voltage7
VOL
Typ
TA = 0˚C
Max
Min
2165
3210
Output LOW Voltage7
1350
VIH
Input HIGH Voltage7
VIL
Max
Min
2220
2420
1650
1350
2070
2410
Input LOW Voltage7
1350
VBB
Output Reference Voltage7
1.87
IIH
Input HIGH Current
Min
2280
2490
2390
2580
mV
1670
1350
1670
1350
1705
mV
2130
2460
2170
2410
2240
2580
mV
1800
1350
1820
1350
1820
1350
1855
mV
2.00
1.92
2.03
1.95
2.05
1.99
2.11
V
150
µV
IIL
Input LOW Current
IEE
Power Supply Current
0.5
150
0.5
66
Typ
TA = +85˚C
Max
150
Typ
TA = +25˚C
150
0.5
66
Typ
0.3
66
µA
66
mA
SK10LVE111E
SK100LVE111E
Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input
SEMTECH
Today's Results ...Tomorrow's Vision
SK100LVE111E ECL DC Electrical Characteristics
(VEE = VEE (min) to VEE (max); VCC = GND) (Notes 2 and 4)
TA = –40˚C
Symbol
Characteristic
VOH
TA = 0˚C
TA = +85˚C
TA = +25˚C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Output HIGH Voltage
-1.14
-1.005
-0.880
-1.08
-0.955
-0.880
-1.08
-0.955
-0.880
-1.08
-0.955
-0.880
V
VOL
Output LOW Voltage
-1.83
-1.695
-1.555
-1.810
-1.705
-1.620
-1.810
-1.705
-1.620
-1.810
-1.705
-1.620
V
VIH
Input HIGH Voltage
-1.165
-0.880
-1.165
-0.880
-1.165
-0.880
-1.165
-0.880
V
VIL
Input LOW Voltage
-1.810
-1.475
-1.810
-1.475
-1.810
-1.475
-1.810
-1.475
V
VBB
Output Reference Voltage
-1.38
-1.26
-1.38
-1.26
-1.38
-1.26
-1.38
-1.26
V
VEE
Power Supply Voltage
-3.0
-3.8
-3.0
-3.8
-3.0
-3.8
-3.0
-3.8
V
IIH
Input HIGH Current
15 0
µA
IEE
Power Supply Current
78
mA
150
55
150
66
55
150
66
55
66
65
SK100LVE111E PECL DC Electrical Characteristics
(VCC = VCC (min) to VCC (max); VEE = GND) (Notes 2 and 4)
TA = –40˚C
TA = 0˚C
TA = +25˚C
TA = +85˚C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
Output HIGH Voltage7
2.16
2.295
2.420
2.22
2.345
2.420
2.22
2.345
2.420
2.22
2.345
2.420
V
VOL
Output LOW Voltage7
1.470
1.610
1.750
1.490
1.595
1.680
1.490
1.595
1.680
1.490
1.595
1.680
V
VIH
Input HIGH Voltage7
2.135
2.420
2.135
2.420
2.135
2.420
2.135
2.420
V
VIL
Input LOW Voltage7
1.490
1.825
1.490
1.825
1.490
1.825
1.490
1.825
V
VBB
Output Reference Voltage7
1.92
2.04
1.92
2.04
1.92
2.04
1.92
2.04
V
VCC
Power Supply Voltage
3.0
3.8
3.0
3.8
3.0
3.8
3.0
3.8
V
IIH
Input HIGH Current
150
µA
I EE
Power Supply Current
78
mA
150
55
66
150
55
66
150
55
66
65
SEMTECH
Today's Results ...Tomorrow's Vision
Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input
SK10LVE111E
SK100LVE111E
AC Characteristics
(VEE = VEE (min) to VEE (max); VCC = VCCO = GND) (Note 4)
-40oC
Symbol
Characteristic
Min
tPLH
tPHL
Propagation Delay to
Output
IN (Differential)
IN (Single-Ended)
400
350
Typ
0oC
Max
Min
650
700
435
385
Typ
25oC
Max
Min
625
675
440
390
Typ
85oC
Max
Min
630
680
445
395
Typ
Max
Unit
Cond
ps
tskew
Within-Device Skew
Part-to-Part Skew (Diff)
VPP
Minimum Input Swing
500
VCMR
Common Mode Range
-1.5
-0.4
-1.5
-0.4
-1.5
-0.4
-1.5
tr , tf
Rise/Fall Time
20% to 80%
200
600
200
600
20 0
600
200
50
250
50
250
500
50
250
500
635
685
50
250
500
8.
9.
ps
10.
mV
11.
-0.4
V
12.
600
ps
20%-80%
Notes:
1. 10LVE111E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been
established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
Outputs are termionated through a 50Ω resistor to –2.0V.
2. The same DC parameter values apply across the full VEE range of –3.0 to –3.8V. Outputs are terminated through a 50Ω
resistor to –2.0V. 100LVE111E circuits are designed to meet the DC specifications shown in the table where transverse airflow
greater than 500 lfpm is maintained.
3. Absolute maximum rating, beyond which device life may be impaired unless otherwise specificed on an individual data sheet.
4. Parametric values specified at:
10LVE111E Series: –3.0 to –3.8V
100 LVE111E Series: –3.0 to –3.8V; PECL Power Supply: +3.0V to +3.8V
5. Guaranteed HIGH signal for all inputs.
6. Guaranteed LOW signal for all inputs.
7. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing
point of the differential output signals.
9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of theoutput
signal.
10. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
11. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The
VPP(min) is AC limited for the E111 as a differential input as low as 50 mV will still produce full ECL levels at the output.
12. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay
specification. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to
VPP(min).
SK10LVE111E
SK100LVE111E
Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input
SEMTECH
Today's Results ...Tomorrow's Vision
Package Information
B
0.007 (0.180)
M
T L–MS N
S
Y BRK
–N–
U
0.007 (0.180)
M
T L–MS N
S
+
D
Z
–L–
–M–
VIEW D-D
W
D
+
X
G1
0.010 (0.250)
H
0.007 (0.180)
T L–MS N
S
S
V
28
1
Z
A
0.007 (0.180)
M
T L–MS N
S
R
0.007 (0.180)
M
T L–MS N
S
K1
C
T L–MS N
M
VIEW S
+
+
E
G
J
0.004 (0.100)
–T– SEATING PLANE
K
G1
0.010 (0.250)
S
T L–MS N
S
F
VIEW S
0.007 (0.180)
T L–MS N
MILLIMETERS
INCHES
NOTES:
1. Datums -L-, -M-, and -N- determined where top of lead
shoulder exits plastic body at mold parting line.
2. DIM G1, true position to be measured at Datum -T-,
Seating Plane.
3. DIM R and U do not include mold flash. Allowable mold flash
is 0.010 (0.250) per side.
4. Dimensioning and tolerancing per ANSI Y14.5M, 1982.
5. Controlling Dimension: Inch.
6. The package top may be smaller than the package bottom by
up to 0.012 (0.300). Dimensions R and U are determined at
the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs and interlead flash, but including
any mismatch betweeen the top and bottom of the plastic body.
7. Dimension H does not include Dambar protrusion or intrusion.
The Dambar protrusion(s) shall not cause the H dimension
to be greater than 0.037 (0.940). The Dambar intrusion(s)
shall not cause the H dimension to be smaller than 0.025
(0.635).
M
DIM
MIN
MAX
MIN
MAX
A
0.485
0.495
12.32
12.57
B
0.485
0.495
12.32
12.57
C
0.165
0.180
4.20
4.57
E
0.090
0.110
2.29
2.79
F
0.013
0.019
0.33
0.48
G
0.050 BSC
1.27 BSC
H
0.026
0.032
0.66
0.81
J
0.020
--
0.51
--
K
0.025
--
0.64
--
R
0.450
0.456
11.43
11.58
U
0.450
0.456
11.43
11.58
V
0.042
0.048
1.07
1.21
W
0.042
0.048
1.07
1.21
X
0.042
0.056
1.07
1.42
Y
--
0.020
--
0.50
Z
2o
10o
2o
10o
G1
0.410
0.430
10.42
10.92
K1
0.040
--
1.02
--
S
S