512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 SST29SF/VF512 / 010 / 020 / 0405.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) Byte-Program, Small Erase Sector flash memories Preliminary Specifications FEATURES: • Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 • Single Voltage Read and Write Operations – 5.0V-only for SST29SF512/010/020/040 – 2.7-3.6V for SST29VF512/010/020/040 • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 10 mA (typical) – Standby Current: 30 µA (typical) for SST29SF512/010/020/040 1 µA (typical) for SST29VF512/010/020/040 • Sector-Erase Capability – Uniform 128 Byte sectors • Fast Read Access Time: – 55 ns – 70 ns • Latched Address and Data • Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 1 second (typical) for SST29SF/VF512 2 seconds (typical) for SST29SF/VF010 4 seconds (typical) for SST29SF/VF020 8 seconds (typical) for SST29SF/VF040 • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • TTL I/O Compatibility for SST29SFxxx • CMOS I/O Compatibility for SST29VFxxx • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 32-pin PLCC – 32-pin TSOP (8mm x 14mm) – 32-pin PDIP PRODUCT DESCRIPTION The SST29SF512/010/020/040 and SST29VF512/010/ 020/040 are 64K x8 / 128K x8 / 256K x8 / 512K x8 CMOS Small-Sector Flash (SSF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST29SFxxx devices write (Program or Erase) with a 4.5-5.5V power supply. The SST29VFxxx devices write (Program or Erase) with a 2.73.6V power supply. These devices conform to JEDEC standard pinouts for x8 memories. and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. They also improve flexibility while lowering the cost for program, data, and configuration storage applications. Featuring high performance Byte-Program, the SST29SFxxx and SST29VFxxx devices provide a maximum Byte-Program time of 20 µsec. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of at least 10,000 cycles. Data retention is rated at greater than 100 years. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST29SFxxx and SST29VFxxx devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505 1 To meet high density, surface mount requirements, the SST29SFxxx and SST29VFxxx devices are offered in 32pin PLCC and 32-pin TSOP packages. A 600 mil, 32-pin PDIP is also offered for SST29SFxxx devices. See Figures 1, 2, and 3 for pinouts. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SSF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications Device Operation edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands issued during the Sector-Erase operation are ignored. Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Chip-Erase Operation The SST29SFxxx and SST29VFxxx devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1s” state. This is useful when the entire device must be quickly erased. Read The Read operation of the SST29SFxxx and SST29VFxxx devices are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4). The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 19 for the flowchart. Any commands written during the ChipErase operation will be ignored. Byte-Program Operation The SST29SFxxx and SST29VFxxx devices are programmed on a byte-by-byte basis. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Write Operation Status Detection The SST29SFxxx and SST29VFxxx devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The SST29SFxxx and SST29VFxxx offer Sector-Erase mode. The sector architecture is based on uniform sector size of 128 Bytes. The Sector-Erase operation is initiated by executing a six-bytecommand sequence with Sector-Erase command (20H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (20H) is latched on the rising ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 2 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications Data# Polling (DQ7) the Program operation, providing optimal protection from inadvertent write operations, e.g., during the system powerup or power-down. Any Erase operation requires the inclusion of six byte load sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC. When the SST29SFxxx and SST29VFxxx devices are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 17 for a flowchart. Product Identification The Product Identification mode identifies the devices as SST29SF512, SST29SF010, SST29SF020, SST29SF040 and SST29VF512, SST29VF010, SST29VF020, SST29VF040 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram and Figure 18 for the Software ID Entry command sequence flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 17 for a flowchart. TABLE 1: PRODUCT IDENTIFICATION Address Data 0000H BFH SST29SF512 0001H 20H SST29VF512 0001H 21H SST29SF010 0001H 22H SST29VF010 0001H 23H SST29SF020 0001H 24H SST29VF020 0001H 25H SST29SF040 0001H 13H SST29VF040 0001H 14H Manufacturer’s ID Device ID Data Protection The SST29SFxxx and SST29VFxxx devices provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. T1.1 505 VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V for SST29SFxxx. The Write operation is inhibited when VDD is less than 1.5V. for SST29VFxxx. Product Identification Mode Exit/Reset In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform and Figure 18 for a flowchart. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST29SFxxx and SST29VFxxx provide the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 3 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications FUNCTIONAL BLOCK DIAGRAM SuperFlash Memory X-Decoder Memory Address Address Buffers & Latches Y-Decoder CE# I/O Buffers and Data Latches Control Logic OE# WE# DQ7 - DQ0 A17 WE# NC NC A17 WE# WE# WE# A18 VDD VDD VDD VDD 4 3 2 1 32 31 30 29 NC NC NC A16 A15 A16 NC A16 A15 A15 A15 A12 A12 A12 SST29SF/VF040 SST29SF/VF020 SST29SF/VF010 SST29SF/VF512 A12 SST29SF/VF512 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040 505 ILL B1.1 SST29SF/VF512 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040 A7 A7 A7 5 A14 A14 A14 A14 A6 A6 A6 A6 6 28 A13 A13 A13 A13 A5 A5 A5 A5 7 27 A8 A8 A8 A8 A4 A4 A4 A4 8 26 A9 A9 A9 A9 A3 A3 A3 A3 9 25 A11 A11 A11 A11 A2 A2 A2 A2 10 24 OE# OE# OE# OE# A1 A1 A1 A1 11 23 A10 A10 A10 A10 A0 A0 A0 A0 12 22 CE# CE# CE# CE# DQ0 DQ0 DQ0 DQ0 13 21 14 15 16 17 18 19 20 DQ7 DQ7 DQ7 DQ7 DQ3 DQ4 DQ5 DQ6 DQ3 DQ4 DQ5 DQ6 DQ3 DQ4 DQ5 DQ6 DQ5 DQ6 VSS VSS VSS VSS DQ4 DQ2 DQ2 DQ2 DQ2 DQ3 DQ1 DQ1 DQ1 32-pin PLCC Top View DQ1 SST29SF/VF040 SST29SF/VF020 SST29SF/VF010 SST29SF/VF512 A7 505 ILL F02a.3 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 4 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications SST29SF/VF040 SST29SF/VF020 SST29SF/VF010 SST29SF/VF512 A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC NC A15 A12 A7 A6 A5 A4 SST29SF/VF512 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 505 ILL F01.2 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X SST29SF040 SST29SF020 SST29SF010 SST29SF512 A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 14MM) SST29SF512 SST29SF010 SST29SF020 SST29SF040 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 505 ILL F02b.4 FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 5 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A8 address lines will select the sector. DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide power supply voltage: VSS Ground NC No Connection 4.5-5.5V for SST29SF512/010/020/040 2.7-3.6V for SST29VF512/010/020/040 Pin not connected internally T2.3 505 1. AMS = Most significant address AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# Read Program VIL VIL VIL VIH Address VIH DOUT AIN VIL DIN AIN VIL X1 Sector address, XXH for Chip-Erase Erase VIL Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit VIH DQ Product Identification Software Mode See Table 4 T3.4 505 1. X can be VIL or VIH, but no other value. ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 6 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle Addr1 Data 2nd Bus Write Cycle Addr1 Data 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data Addr1 Data Data 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data Addr1 Data Byte-Program 555H AAH 2AAH 55H 555H A0H BA2 Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX3 20H 555H AAH 2AAH 55H 555H 10H Chip-Erase 555H AAH 2AAH 55H 555H 80H Software ID Entry4,5 555H AAH 2AAH 55H 555H 90H 2AAH 55H 555H F0H Software ID Exit6 XXH F0H Software ID Exit6 555H AAH T4.4 505 1. Address format A14-A0 (Hex), Address A15 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF512. Addresses A15 - A16 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF010. Addresses A15 - A17 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF020. Addresses A15 - A18 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF040. 2. BA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A7 address lines for SST29SF/VFxxx AMS = Most significant address AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040 4. The device does not remain in Software Product ID Mode if powered down. 5. With AMS-A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0, SST29SF512 Device ID = 20H, is read with A0 = 1 SST29SF512 Device ID = 21H, is read with A0 = 1 SST29SF010 Device ID = 22H, is read with A0 = 1 SST29VF010 Device ID = 23H, is read with A0 = 1 SST29SF020 Device ID = 24H, is read with A0 = 1 SST29SF020 Device ID = 25H, is read with A0 = 1 SST29SF040 Device ID = 13H, is read with A0 = 1 SST29VF040 Device ID = 14H, is read with A0 = 1 6. Both Software ID Exit operations are equivalent ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 7 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE FOR Range Commercial Industrial AC CONDITIONS OF SST29SF512/010/020/040 OPERATING RANGE Ambient Temp VDD 0°C to +70°C 5V±10% Commercial -40°C to +85°C 5V±10% Industrial FOR Range SST29VF512/010/020/040 Ambient Temp VDD 0°C to +70°C 2.7-3.6V -40°C to +85°C 2.7-3.6V TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 55 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 70 ns See Figures 13, 14, and 15 TABLE 5: DC OPERATING CHARACTERISTICS VDD = 5.0V±10% FOR SST29SFXXX Limits Symbol Parameter IDD Power Supply Current Min Max Units Test Conditions Address input=VIL/VIH, at f=1/TRC Min VDD=VDD Max Read 20 mA CE#=OE#=VIL, WE#=VIH, all I/Os open Write 20 mA CE#=WE#=VIL, OE#=VIH ISB1 Standby VDD Current (TTL input) 3 mA CE#=VIH, VDD=VDD Max ISB2 Standby VDD Current (CMOS input) 100 µA CE#=VIHC, VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VIH Input High Voltage 2.0 V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max VOL Output Low Voltage V IOL=2.1 µA, VDD=VDD Min VOH Output High Voltage V IOH=-400 µA, VDD=VDD Min 0.4 2.4 T5.3 505 ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 8 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications TABLE 6: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V FOR SST29VFXXX Limits Symbol Parameter IDD Power Supply Current Min Max Units Test Conditions Address input=VIL/VIH, at f=1/TRC Min VDD=VDD Max Read 20 mA CE#=OE#=VIL, WE#=VIH, all I/Os open Write 20 mA CE#=WE#=VIL, OE#=VIH ISB Standby VDD Current 15 µA CE#=VIHC, VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VIH Input High Voltage 0.7VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 VOL Output Low Voltage VOH Output High Voltage 0.2 VDD-0.2 V VDD=VDD Max V IOL=100 µA, VDD=VDD Min V IOH=-100 µA, VDD=VDD Min T6.5 505 TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ Parameter 1 TPU-WRITE1 Minimum Units Power-up to Read Operation 100 µs Power-up to Program/Erase Operation 100 µs T7.1 505 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter CI/O 1 CIN1 Description Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF T8.1 505 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 9: RELIABILITY CHARACTERISTICS Symbol Parameter NEND1 Endurance TDR1 Data Retention ILTH1 Latch Up Minimum Specification Units Test Method 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA JEDEC Standard 78 T9.2 505 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 9 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications AC CHARACTERISTICS TABLE 10: READ CYCLE TIMING PARAMETERS VDD = 5V±10% FOR SST29SFXXX AND 2.7-3.6V FOR SST29VFXXX SST29SF/VFxxx-55 SST29SF/VFxxx-70 Min Min Symbol Parameter Max Max Units TRC Read Cycle Time TCE Chip Enable Access Time 55 70 ns TAA TOE Address Access Time 55 70 ns Output Enable Access Time 30 35 TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 ns CE# Low to Active Output 0 0 ns OE# Low to Active Output 0 0 ns 55 70 ns CE# High to High-Z Output 20 25 ns OE# High to High-Z Output 20 25 ns Output Hold from Address Change 0 0 ns T10.5 505 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD = 5V±10%V FOR SST29SFXXX AND 2.7-3.6V FOR SST29VFXXX Symbol Parameter TBP Byte-Program Time TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns WE# Pulse Width 40 ns TWP TWPH 1 Min Max Units 20 µs WE# Pulse Width High 30 ns TCPH1 CE# Pulse Width High 30 ns TDS Data Setup Time 40 ns Data Hold Time 0 TDH 1 ns TIDA1 Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TSCE Chip-Erase 100 ms T11.6 505 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 10 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications TAA TRC ADDRESS AMS-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# HIGH-Z DQ7-0 TCHZ TOH TCLZ HIGH-Z DATA VALID DATA VALID 505 ILL F03.1 Note: AMS = Most Significant Address AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040 FIGURE 4: READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS TBP 555 TAH ADDRESS AMS-0 2AA 555 ADDR TDH TWP WE# TAS TDS TWPH OE# TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) 505 ILL F04.1 Note: AMS = Most Significant Address AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040 FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 11 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications INTERNAL PROGRAM OPERATION STARTS TBP 555 TAH ADDRESS AMS-0 2AA 555 ADDR TDH TCP CE# TAS TDS TCPH OE# TCH WE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) 505 ILL F05.1 Note: AMS = Most Significant Address AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040 FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS AMS-0 TCE CE# TOES TOEH OE# TOE WE# DQ7 D D# D# D 505 ILL F06.1 Note: AMS = Most Significant Address AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040 FIGURE 7: DATA# POLLING TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 12 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications ADDRESS AMS-0 TCE CE# TOES TOE TOEH OE# WE# DQ6 TWO READ CYCLES WITH SAME OUTPUTS 505 ILL F07.1 Note: AMS = Most Significant Address AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040 FIGURE 8: TOGGLE BIT TIMING DIAGRAM TSE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 555 2AA 555 555 2AA SAX CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 20 SW0 SW1 SW2 SW3 SW4 SW5 505 ILL F10.2 Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 11) AMS = Most significant address AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040 FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 13 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications TSCE SIX-BYTE CODE FOR CHIP-ERASE 555 ADDRESS AMS-0 2AA 555 555 2AA 555 CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 SW0 SW1 SW2 SW3 SW4 10 SW5 505 ILL F17.2 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 11) Note: AMS = Most Significant Address AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040 FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM Three-Byte Sequence for Software ID Entry ADDRESS A14-0 555 2AA 555 0000 0001 TIDA CE# OE# TWP WE# TWPH DQ7-0 TAA AA 55 90 SW0 SW1 SW2 BF Device ID 505 ILL F08.2 Note: Device ID = 20H for SST29SF512, 22H for SST29SF010, 24H for SST29SF020, 13H for SST29SF040 21H for SST29VF512, 23H for SST29VF010, 25H for SST29VF020, 14H for SST29VF040 FIGURE 11: SOFTWARE ID ENTRY AND READ ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 14 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 DQ7-0 555 AA 2AA 555 55 F0 TIDA CE# OE# TWP WE# T WHP SW0 SW1 SW2 505 ILL F21.0 FIGURE 12: SOFTWARE ID EXIT AND RESET ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 15 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications VIHT VIT INPUT REFERENCE POINTS VOT OUTPUT VILT 505 ILL F11.0 AC test inputs are driven at VIHT (3.0 V) for a logic “1” and VILT (0 V) for a logic “0”. Measurement reference points for inputs and outputs are VIT (1.5 VDD) and VOT (1.5 VDD). Input rise and fall times (10% ↔ 90%) are <10 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS FOR SST29SFXXX VIHT VIT INPUT REFERENCE POINTS VOT OUTPUT VILT 505 ILL F11.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS FOR SST29VFXXX TEST LOAD EXAMPLE FOR SST29VF512/010/020/040 TEST LOAD EXAMPLE FOR SST29SF512/010/020/040 VDD TO TESTER TO TESTER RL HIGH TO DUT CL 505 ILL F12b.2 TO DUT CL RL LOW 505 ILL F12.2 FIGURE 15: TEST LOAD EXAMPLES ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 16 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications Start Load data: AAH Address: 555H Load data: 55H Address: 2AAH Load data: A0H Address: 555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 505 ILL F13.1 FIGURE 16: BYTE-PROGRAM ALGORITHM ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 17 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications Internal Timer Toggle Bit Data# Polling ByteProgram/Erase Initiated ByteProgram/Erase Initiated ByteProgram/Erase Initiated Read byte Read DQ7 Wait TBP, TSCE, or TSE Read same byte Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 505 ILL F14.0 FIGURE 17: WAIT OPTIONS ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 18 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications Software ID Entry Command Sequence Software ID Exit & Reset Command Sequence Load data: AAH Address: 555H Load data: AAH Address: 555H Load data: F0H Address: XXH Load data: 55H Address: 2AAH Load data: 55H Address: 2AAH Wait TIDA Load data: 90H Address: 555H Load data: F0H Address: 555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 505 ILL F15.1 FIGURE 18: SOFTWARE ID COMMAND FLOWCHARTS ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 19 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications Chip-Erase Command Sequence Sector-Erase Command Sequence Load data: AAH Address: 555H Load data: AAH Address: 555H Load data: 55H Address: 2AAH Load data: 55H Address: 2AAH Load data: 80H Address: 555H Load data: 80H Address: 555H Load data: AAH Address: 555H Load data: AAH Address: 555H Load data: 55H Address: 2AAH Load data: 55H Address: 2AAH Load data: 10H Address: 555H Load data: 20H Address: SAX Wait TSCE Wait TSE Chip erased to FFH Sector erased to FFH 505 ILL F19.2 FIGURE 19: ERASE COMMAND SEQUENCE ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 20 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications Device SST29xFxxx Speed - XXX Suffix1 - XX Suffix2 - XX Package Modifier H = 32 pins Numeric = Die modifier Package Type N = PLCC W = TSOP (die up) (8mm x 14mm) P = PDIP Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 55 = 55 ns 70 = 70 ns Device Density 512 = 512 Kilobit 010 = 1 Megabit 020 = 2 Megabit 040 = 4 Megabit Voltage S = 5V±10% V = 2.7-3.6V ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 21 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications SST29SF512 Valid combinations SST29SF512-55-4C-NH SST29SF512-70-4C-NH SST29SF512-55-4C-WH SST29SF512-70-4C-WH SST29SF512-55-4I-NH SST29SF512-70-4I-NH SST29SF512-55-4I-WH SST29SF512-70-4I-WH SST29SF512-70-4C-PH SST29VF512 Valid combinations SST29VF512-55-4C-NH SST29VF512-70-4C-NH SST29VF512-55-4C-WH SST29VF512-70-4C-WH SST29VF512-55-4I-NH SST29VF512-70-4I-NH SST29VF512-55-4I-WH SST29VF512-70-4I-WH SST29SF010 Valid combinations SST29SF010-55-4C-NH SST29SF010-70-4C-NH SST29SF010-55-4C-WH SST29SF010-70-4C-WH SST29SF010-55-4I-NH SST29SF010-70-4I-NH SST29SF010-55-4I-WH SST29SF010-70-4I-WH SST29SF010-70-4C-PH SST29VF010 Valid combinations SST29VF010-55-4C-NH SST29VF010-70-4C-NH SST29VF010-55-4C-WH SST29VF010-70-4C-WH SST29VF010-55-4I-NH SST29VF010-70-4I-NH SST29VF010-55-4I-WH SST29VF010-70-4I-WH SST29SF020 Valid combinations SST29SF020-55-4C-NH SST29SF020-70-4C-NH SST29SF020-55-4C-WH SST29SF020-70-4C-WH SST29SF020-55-4I-NH SST29SF020-70-4I-NH SST29SF020-55-4I-WH SST29SF020-70-4I-WH SST29SF020-70-4C-PH SST29VF020 Valid combinations SST29VF020-55-4C-NH SST29VF020-70-4C-NH SST29VF020-55-4C-WH SST29VF020-70-4C-WH SST29VF020-55-4I-NH SST29VF020-70-4I-NH SST29VF020-55-4I-WH SST29VF020-70-4I-WH SST29SF040 Valid combinations SST29SF040-55-4C-NH SST29SF040-70-4C-NH SST29SF040-55-4C-WH SST29SF040-70-4C-WH SST29SF040-55-4I-NH SST29SF040-70-4I-NH SST29SF040-55-4I-WH SST29SF040-70-4I-WH SST29SF040-70-4C-PH SST29VF040 Valid combinations SST29VF040-55-4C-NH SST29VF040-70-4C-NH SST29VF040-55-4C-WH SST29VF040-70-4C-WH SST29VF040-55-4I-NH SST29VF040-70-4I-NH SST29VF040-55-4I-WH SST29VF040-70-4I-WH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 22 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications PACKAGING DIAGRAMS TOP VIEW Optional Pin #1 Identifier SIDE VIEW .485 .495 .447 .453 .042 .048 2 1 .106 .112 32 .020 R. MAX. .023 x 30˚ .029 .030 R. .040 .042 .048 .585 .595 BOTTOM VIEW .547 .553 .013 .021 .400 BSC .026 .032 .490 .530 .050 BSC. .015 Min. .075 .095 .050 BSC. .026 .032 .125 .140 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32.PLCC.NH-ILL.2 4. Coplanarity: 4 mils. 32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH 1.05 0.95 Pin # 1 Identifier .50 BSC .270 .170 8.10 7.90 0.15 0.05 12.50 12.30 0.70 0.50 14.20 13.80 32.TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH X 14MM ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 23 505 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 Preliminary Specifications 32 CL .600 .625 1 Pin #1 Identifier .530 .550 1.645 1.655 .065 .075 7˚ 4 PLCS. .170 .200 Base Plane Seating Plane .015 .050 .070 .080 Note: .045 .065 .016 .022 .100 BSC .120 .150 0˚ 15˚ .008 .012 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. .600 BSC 32.pdipPH-ILL.2 32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 24 505