TDA7343 DIGITALLY CONTROLLED AUDIO PROCESSOR INPUT MULTIPLEXER - TWO STEREO AND ONE MONO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES FULLY PROGRAMMABLE LOUDNESS FUNCTION VOLUME CONTROL IN 0.3dB STEPS INCLUDING GAIN UP TO 20dB ZERO CROSSING MUTE AND DIRECT MUTE SOFT MUTE CONTROLLED BY SOFTWARE OR HARDWARE PIN BASS AND TREBLE CONTROL FOUR SPEAKER ATTENUATORS - FOUR INDEPENDENT SPEAKERS CONTROL IN 1.25dB STEPS FOR BALANCE AND FADER FACILITIES - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2 CBUS DESCRIPTION The TDA7343 is an upgrade of the TDA7313 audioprocessor. Thanks to the used BIPOLAR/CMOS technology, very low distortion, low noise and DC-stepping are obtained. Due to a highly linear signal processing, using November 1999 DIP28 SO28 ORDERING NUMBER: TDA7343 (DIP28) TDA7343D (SO28) CMOS-switching techniques instead of standard bipolar multipliers, very low distortion and very low noise are obtained Several new features like softmute, zero-crossing mute and pause detector are implemented. The Soft Mute function can be activated in two ways: 1 Via serial bus (bit D0, Mute Byte) 2 Directly on pin 22 through an I/O line of the microcontroller Very low DC stepping is obtained by use of a BICMOS technology. 1/14 2/14 RIGHT INPUTS LEFT INPUTS C5 C4 C2 C1 2x 1µF C3 2x 1µF VS R1 R2 L2 L1 C6 7 OUT(R) 1 CREF 10µF INPUT SELECTOR + GAIN 3 SUPPLY R1 R2 R3 L3 L2 L1 C7 2.2µF IN(R) 6 8 LOUD+ VOL LOUD+ VOL C9 47nF CSM 15 SOFT MUTE C11 100nF 21 18 R1 4.7K BOUT(R) 20 RB BASS BASS RB BIN(L) 19 22 12 LOUD(R) ZERO CROSS + MUTE ZERO CROSS + MUTE 16 17 AGND 2 10 9 11 13 14 IN(L) OUT(L) C14 100nF SM BOUT(L) R2 4.7K C10 100nF LOUD(L) CSM C8 2.2µF C16 2.7nF TREBLE(L) MUTE SPKR ATT MUTE SPKR ATT C12 100nF BIN(R) 5 TREBLE C13 2.7nF TREBLE(R) MUTE SPKR ATT MUTE SPKR ATT SERIAL BUS DECODER + LATCHES TREBLE 4 C15 100nF D93AU062B 23 25 27 28 24 26 BUS OUT RIGHT REAR OUT RIGHT FRONT SDA SCL OUT LEFT REAR OUT LEFT FRONT TDA7343 BLOCK DIAGRAM TDA7343 ABSOLUTE MAXIMUM RATINGS Symbol VS Parameter Operating Supply Voltage Value Unit 10.5 V Tamb Operating Ambient Temperature -40 to 85 °C Tstg Storage Temperature Range -55 to 150 °C PIN CONNECTION CREF 1 28 SCL VS 2 27 SDA GND 3 26 OUT LF TREBLE BUS INPUTS L 4 25 OUT RF R 5 24 OUT LR IN(R) 6 23 OUT RR OUT(R) 7 22 SM LOUD R 8 21 BOUT(R) IN R2 9 20 BIN(R) IN R1 10 19 BOUT(L) AM MONO 11 18 BIN(L) LOUD L 12 17 OUT(L) IN L2 13 16 IN(L) IN L1 14 15 CSM BASS D94AU061B THERMAL DATA Symbol Rth j-amb Parameter DIP28 SO28 Unit 85 65 °C/W Unit Thermal Resistance Junction-pins QUICK REFERENCE DATA Symbol Parameter VS Supply Voltage VCL Max. input signal handling Min. Typ. Max. 6 9 10.2 2.1 2.6 THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 S/N Signal to Noise Ratio 106 SC Channel Separation f = 1KHz Volume Control 0.3dB step V Vrms 0.08 % dB 100 dB -59.7 20 dB Treble Control 2dB step -14 +14 dB Bass Control 2dB step -10 +18 dB -38.75 0 dB 0 11.25 dB Fader and Balance Control 1.25dB step Input Gain 3.75dB step Mute Attenuation 100 dB 3/14 TDA7343 ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all controls flat (G - 0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. 130 Unit INPUT SELECTOR RI VCL Input Resistance Clipping Level d ≤ 0.3% 70 100 2.1 2.6 100 SI Input Separation 80 RL Output Load Resistance 2 KΩ VRMS dB KΩ GI MIN Minimum Input Gain -0.75 0 0.75 GI MAX Maximum Input Gain 10.25 11.25 12.25 dB Gstep Step Resolution 2.75 3.75 4.75 dB 10 µV mV eN Input Noise 20Hz to 20 KHz unweighted 2.3 VDC DC Steps Adiacent Gain Steps 1.5 GIMIN to GIMAX 3 dB mV VOLUME CONTROL 35 50 GMAX RI Input Resistance Maximum Gain 18.75 20 21.25 dB AMAX Maximum Attenuation 57.7 59.7 62.7 dB ASTEPC Step Resolution Coarse Attenuation 0.5 1.25 2.0 dB ASTEPF Step Resolution Fine Attenuation EA Attenuation Set Error Et Tracking Error VDC DC Steps KΩ 0.11 0.31 0.51 dB G = 20 to -20dB -1.25 0 1.25 dB G = -20 to -58dB -3 Adiacent Attenuation Steps -3 From 0dB to AMAX 2 dB 2 dB 0 3 mV 0.5 5 mV LOUDNESS CONTROL 35 50 65 KΩ AMAX RI Internal Resistor Maximum Attenuation Loud = ON 17.5 18.75 20.0 dB Astep Step Resolution 0.5 1.25 2.0 dB ZERO CROSSING MUTE VTH AMUTE VDC Zero Crossing Threshold (note 1) WIN = 11 20 mV WIN = 10 40 mV WIN = 01 80 mV WIN = 00 160 mV 100 dB Mute Attenuation DC Step 80 0dB to Mute 0 3 mV SOFT MUTE AMUTE Mute Attenuation TDON ON Delay Time TDOFF OFF Delay Time 60 CCSM = 22nF; 0 to -20dB; I = IMAX 0.7 1 1.7 ms CCSM = 22nF; 0 to -20dB; I = IMIN 20 35 55 ms VCSM = 0V; I = IMAX 25 50 75 µA VCSM = 0V; I = IMIN Soft Mute Threshold µA 1 1.5 2.5 3.5 V RINT Pullup Resistor (pin 22) (note 2) 35 50 65 KΩ VSMH (pin 22) Level High Soft Mute Active 3.5 VSML (pin 22) Level Low 1 V VTHSM 4/14 dB V TDA7343 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit dB BASS CONTROL BBOOST Max Bass Boost 15 18 20 BCUT Max Bass Cut -8.5 -10 -11.5 dB Astep Step Resolution 1 2 3 dB Internal Feedback Resistance 45 65 85 KΩ ±13 1 ±14 2 ±15 3 dB 35 37.5 40 dB 0.5 1.25 2.0 80 100 Rg TREBLE CONTROL C RANGE Astep Control Range Step Resolution dB SPEAKER ATTENUATORS C RANGE Astep AMUTE Control Range Step Resolution Output Mute Attenuation EA Attenuation Set Error VDC DC Steps Data Word = XXX11111 Adjacent Attenuation Steps 0 dB dB 1.25 dB 3 mV AUDIO OUTPUT Vclip Clipping Level RL Output Load Resistance RO Output Impedance VDC DC Voltage Level d = 0.3% 2.1 2.6 Vrms 2 3.5 KΩ 30 100 Ω 3.8 4.1 V GENERAL VCC Supply Voltage 6 9 10.2 V ICC Supply Current 5 10 15 mA PSRR e NO Et Power Supply Rejection Ratio Output Noise Total Tracking Error S/N Signal to Noise Ratio SC Channel Separation d Distortion 80 dB B = 20 to 20kHz ”A” weighted f = 1KHz 60 65 dB µV Output Muted (B = 20 to 20kHz flat) 2.5 All Gains 0dB (B = 20 to 20kHz flat) 5 15 µV AV = 0 to -20dB 0 1 dB AV = -20 to -60dB 0 2 dB All Gains = 0dB; VO = 1Vrms 106 80 Vin = 1V dB 100 0.01 dB 0.08 % 1 V 5 µA 0.8 V BUS INPUTS VIL Input Low Voltage V lN Input High Voltage IlN Input Current VIN = 0.4V VO Output Voltage SDA Acknowledge IO = 1.6mA 3 V -5 0.4 Note 1: WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold Note 2: Internal pullup resistor to Vs/2; ”LOW” = softmute active 5/14 TDA7343 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7343 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS Figure 4: Timing Diagram of I2CBUS Figure 5: Acknowledge on the I2CBUS 6/14 knowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. TDA7343 SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte,(the LSB bit determines CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 read/write transmission) A subaddress byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) MSB 0 R/W ACK X X DATA 1 to DATA n LSB X I MSB A3 A2 A1 A0 ACK LSB DATA ACK P ACK = Acknowledge S = Start P = Stop I = Auto Increment X = Not used MAX CLOCK SPEED 500kbits/s AUTO INCREMENT If bit I in the subaddress byte is set to ”1”, the autoincrement of the subaddress is enabled SUBADDRESS (receive mode) MSB LSB X X X I FUNCTION A3 A2 A1 A0 0 0 0 0 Input Selector 0 0 0 1 Loudness 0 0 1 0 Volume 0 0 1 1 Bass, Treble 0 1 0 0 Speaker Attenuator LF 0 1 0 1 Speaker Attenuator LR 0 1 1 0 Speaker Attenuator RF 0 1 1 1 Speaker Attenuator RR 1 0 0 0 Mute TRANSMITTED DATA Send Mode MSB X LSB X X X X SM ZM X ZM = Zero crossing muted (HIGH active) SM = Soft mute activated (HIGH active) X = Not used The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chip address. 7/14 TDA7343 DATA BYTE SPECIFICATION X = not relevant; set to ”1” during testing Input Selector MSB LSB D7 D6 D5 X X X X D4 D3 FUNCTION D2 D1 D0 1 0 0 0 not used X 1 0 0 1 IN 2 X 1 0 1 0 IN 1 X X 1 0 1 1 AM mono X X 1 1 0 0 not used X X 1 1 0 1 not used X X 1 1 1 0 not allowed X X 1 1 1 1 X X 1 0 0 11.25dB gain X X 1 0 1 7.5dB gain X X 1 1 0 3.75dB gain X X 1 1 1 0dB gain not allowed For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1 Loudness MSB LSB FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 X X X 0 0 0 0 0 0dB X X X 0 0 0 0 1 -1.25dB X X X 0 0 0 1 0 -2.5dB X X X 0 0 0 1 1 -3.75dB X X X 0 0 1 0 0 -5dB X X X 0 0 1 0 1 -6.25dB X X X 0 0 1 1 0 -7.5dB X X X 0 0 1 1 1 -8.75dB X X X 0 1 0 0 0 -10dB X X X 0 1 0 0 1 -11.25dB X X X 0 1 0 1 0 -12.5dB X X X 0 1 0 1 1 -13.75dB X X X 0 1 1 0 0 -15dB X X X 0 1 1 0 1 -16.25dB X X X 0 1 1 1 0 -17.5dB X X X 0 1 1 1 1 -18.75dB X X X 1 D3 D2 D1 D0 Loudness OFF (1) For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0 NOTE 1: If the loudness is switched OFF, the loudness stage is acting like a volume attenuator with flat frequency response. D0 to D3 determine the attenuation level. 8/14 TDA7343 Mute MSB D7 LSB D6 D5 D4 D3 D2 D1 FUNCTION D0 1 Soft Mute On 0 1 Soft Mute with fast slope (I = IMAX) 1 1 Soft Mute with slow slope (I = IMIN) 1 Direct Mute 0 1 Zero Crossing Mute On 0 0 Zero Crossing Mute Off (delayed until next zerocrossing) 1 Zero Crossing Mute and Pause Detector Reset 0 0 160mV ZC Window Threshold (WIN = 00) 0 1 80mV ZC Window Threshold (WIN = 01) 1 0 40mV ZC Window Threshold (WIN = 10) 1 1 20mV ZC Window Threshold (WIN = 11) 0 Nonsymmetrical Bass Cut (note 4) 1 Symmetrical Bass Cut An additional direct mute function is included in the Speaker Attenuators. Note 4: Bass cut for very low frequencies; should not be used at +16 and +18dB bass boost (DC gain) Speaker Attenuators MSB LSB D7 D6 D5 X X X D4 D3 SPEAKER ATTENUATOR LF, LR, RF, RR D2 D1 D0 X 0 0 0 0dB X X 0 0 1 -1.25dB X X X 0 1 0 -2.5dB X X X 0 1 1 -3.75dB X X X 1 0 0 -5dB X X X 1 0 1 -6.25dB X X X 1 1 0 -7.5dB X X X 1 1 1 -8.75dB X X X 0 0 0dB X X X 0 1 -10dB X X X 1 0 -20dB X X X 1 1 X X X 1 1 1.25dB step 10dB step -30dB 1 1 1 Speaker Mute For example an attenuationof 25dB on a selected output is given by: X X X1 0 1 0 0 9/14 TDA7343 Bass/Treble MSB D7 LSB D6 D5 D4 FUNCTION D3 D2 D1 D0 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB TREBLE STEP BASS STEPS 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 -0dB 1 1 1 1 -0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB 0 0 0 1 146B 0 0 0 0 18dB For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1 10/14 TDA7343 Volume MSB D7 LSB D6 D5 D4 D3 D2 FUNCTION D1 D0 0 0 0dB 0 1 -0.31dB 1 0 -0.62dB 1 1 -0.94dB 0.31dB Fine Attenuation Steps 1.25dB Coarse Attenuation Steps 0 0 0 0dB 0 0 1 -1.25dB 0 1 0 -2.5dB 0 1 1 -3.75dB 1 0 0 -5dB 1 0 1 -6.25dB 1 1 0 -7.5dB 1 1 1 -8.75dB 10dB Gain / Attenuation Steps 0 0 0 20dB 0 0 1 10dB 0 1 0 0dB 0 1 1 -10dB 1 0 0 -20dB 1 0 1 -30dB 1 1 0 -40dB 1 1 1 -50dB For example to select -47.81dB Volume the Data Byte is: 1 1 0 1 1 0 0 1 Power on RESET: All Bytes Set to 1 1 1 1 1 1 1 0 Purchase of I2C Components of STMicrolectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I 2C Standard Specifications as defined by Philips. 11/14 TDA7343 mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 2.65 MAX. 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 c1 0.020 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S 12/14 OUTLINE AND MECHANICAL DATA 8 ° (max.) SO28 TDA7343 mm DIM. MIN. TYP. inch MAX. MIN. TYP. a1 0.63 0.025 b 0.45 0.018 b1 0.23 b2 0.31 D E 0.012 0.009 1.27 0.050 37.34 15.2 16.68 1.470 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 F MAX. OUTLINE AND MECHANICAL DATA 14.1 0.555 I 4.445 0.175 L 3.3 0.130 DIP28 13/14 TDA7343 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 14/14