74ACT74 DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 250 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The ACT74 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of B M (Plastic Package) (Micro Package) ORDER CODES : 74ACT74B 74ACT74M the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS April 1997 1/11 74ACT74 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 13 1CLR, 2CLR Asyncronous Reset Direct Input NAME AND F UNCTIO N 2, 12 1D, 2D Data Inputs 3, 11 1CK, 2CK Clock Input (LOW-to-HIGH, EdgeTriggered) 4, 10 1PR, 2PR Asyncronous Set - Direct Input 5, 9 1Q, 2Q True Flip-Flop Outputs 6, 8 1Q, 2Q Complement Flip-Flop Outputs 7 GND Ground (0V) 14 VCC Positive Supply Voltage TRUTH TABLE INPUTS OUT PUT S CLR PR D CK L H X H L X X Q X L H CLEAR X H L PRESET H H L H L L X H H L H H H H L H H X Qn Qn X: Don’t Care LOGIC DIAGRAMS This logic diagram has not be used to estimate propagation delays 2/11 F UNCT IO N Q NO CHANGE 74ACT74 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ± 200 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o C 300 o C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol Valu e Unit Supply Voltage 4.5 to 5.5 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC VCC Top dt/dv Parameter Operating Temperature: Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) -40 to +85 8 V o C ns/V 1) VIN from 0.8 V to 2.0 V 3/11 74ACT74 DC SPECIFICATIONS Symbol Parameter Test Con dition s VIH High Level Input Voltage 4.5 5.5 VIL Low Level Input Voltage 4.5 5.5 VOH High Level Output Voltage 4.5 5.5 Low Level Output Voltage VO = 0.1 V or VCC - 0.1 V Min. Typ. 2.0 1.5 2.0 2.0 1.5 2.0 VO = 0.1 V or VCC - 0.1 V (*) VI = V IH or V IL Unit -40 to 85 o C Max. Min . Max. V 1.5 0.8 0.8 1.5 0.8 0.8 IO=-50 µA 4.4 4.49 4.4 IO=-50 µA 5.4 5.49 5.4 V V IO=-24 mA 3.86 5.5 IO=-24 mA 4.86 4.5 IO=50 µA 0.001 0.1 0.1 IO=50 mA 0.001 0.1 0.1 IO=24 mA 0.36 0.44 IO=24 mA 0.36 0.44 ±0.1 ±1 µA 1.5 mA 40 µA 4.5 VOL Value T A = 25 oC V CC (V) 5.5 4.5 5.5 V I (*) = V IH or V IL 3.76 4.76 Input Leakage Current 5.5 ICCT Max ICC /Input 5.5 VI = VCC -2.1 V ICC Quiescent Supply Current 5.5 VI = VCC or GND IOLD Dynamic Output Current (note 1, 2) 5.5 VOLD = 1.65 V max 75 mA VOHD = 3.85 V min -75 mA II IOHD VI = VCC or GND V 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω. (*) All outputs loaded. 4/11 0.6 4 74ACT74 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = t f =3 ns) Symbol Parameter T est Cond ition V CC (V) Value T A = 25 oC -40 to 85 o C Min. Typ. Max. Min . Max. Unit (*) 5.0 10.0 11.0 ns 5.0 (*) 5.0 10.0 11.0 ns CK Pulse Width, HIGH or LOW 5.0(*) 1.5 5.0 6.0 ns ts Setup Time Q to CK HIGH or LOW 5.0(*) 0.5 3.0 3.5 ns th Hold Time Q to CK HIGH or LOW 5.0(*) -0.5 1.0 1.0 ns trem Removal Time PR or CLR to CK 5.0 (*) -0.7 1.0 1.0 ns fMAX Maximim Clock Frequency 5.0 tPLH tPHL Propagation Delay Time CK to Q 5.0 tPLH tPHL Propagation Delay Time PR or CLR to Q or Q tw (*) 100 250 85 MHz (*) Voltage range is 5V ± 0.5V CAPACITIVE CHARACTERISTICS Symbol Parameter Test Con dition s V CC (V) CIN Input Capacitance C PD Power Dissipation Capacitance (note 1) Value T A = 25 oC Min. Typ. Max. Unit -40 to 85 o C Min . Max. 5.0 4 pF 5.0 43 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n (per circuit) 5/11 74ACT74 TEST CIRCUIT CL = 50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT =ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/11 74ACT74 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 7/11 74ACT74 WAVEFORM 3: RECOVERY TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PULSE WIDTH 8/11 74ACT74 Plastic DIP14 MECHANICAL DATA mm DIM. MIN. a1 0.51 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L Z 3.3 1.27 0.130 2.54 0.050 0.100 P001A 9/11 74ACT74 SO14 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 (typ.) D 8.55 E 5.8 8.75 0.336 6.2 0.228 0.344 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8 (max.) P013G 10/11 74ACT74 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. 1997 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A . 11/11