74LCX374 OCTAL D-TYPE FLIP FLOP NON INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED: fMAX = 150 MHz (MIN.) at VCC = 3V POWER-DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 LATCH-UP PERFORMANCE EXCEEDS 500mA ESD PERFORMANCE: HBM >2000V; MM > 200V DESCRIPTION The LCX374 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed applications; it can be interfaced to 5V signal environment for both inputs and outputs. These 8 bit D-Type flip-flops are controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q M (Micro Package) T (TSSOP Package) ORDER CODES : 74LCX374M 74LCX374T outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the 8 outputs will be in a normal state (high or low logic level) and while high level the outputs will be in a high impedance state. The output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. It has same speed performance at 3.3V than 5V, AC/ACT family, combined with a lower power consumption. It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/10 74LCX374 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE TRUTH TABLE NAME AND FUNCT ION 3 State Output Enable Input (Active LOW) 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 Data Inputs 11 CLOCK Clock Input (LOW to HIGH, edge triggered) 10 GND Ground (0V) 20 VCC Positive Supply Voltage LOGIC DIAGRAM 2/10 3 State Outputs INPUT S OUT PUT S OE CK D H X X Z X NO CHANGE L Q L L L L H H X:”H” or ”L” Z: High Impedance 74LCX374 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to + 7.0 V VI DC Input Voltage -0.5 to + 7.0 V VO DC Output Voltage (OFF state) -0.5 to + 7.0 V VO DC Output Voltage (High or Low State) (note1) -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 50 mA IOK DC Output Diode Current (note2) ± 50 mA IO DC Output Source/Sink Current ± 50 mA ICC DC Supply Current per Supply Pin ± 100 mA IGND DC Ground Current per Supply Pin ± 100 mA Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) IO absolute maximum rating must be observed 2) VO < GND, VO > VCC RECOMMENDED OPERATING CONDITIONS Symbol Parameter Unit 2.0 to 3.6 V VI Input Voltage 0 to 5.5 V VO Output Voltage (OFF state) 0 to 5.5 V VO Output Voltage (High or Low State) 0 to VCC V ± 24 mA ± 12 mA VCC Supply Voltage (note 1) Value IOH, IOL High or Low Level Output Current (VCC = 3.0 to 3.6V) IOH, IOL High or Low Level Output Current (VCC = 2.7 to 3.0V) Top dt/dv Operating Temperature: Input Transition Rise or Fall Rate (V CC = 3.0V) (note 2) -40 to +85 0 to 10 o C ns/V 1) Truth Table guaranteed: 1.5V to3.6V 2) VIN from0.8V to 2.0V 3/10 74LCX374 DC SPECIFICATIONS Symb ol Parameter Test Co nditi ons Value VIH High Level Input Voltage VIL Low Level Input Voltage VOH High Level Output Voltage 2.7 3.0 VOL Low Level Output Voltage 2.7 to 3.6 2.7 3.0 3.0 II Input Leakage Current IOZ 3 State Output Leakage Current Ioff Power Off Leakage Current ICC Quiescent Supply Current ∆ICC ICC incr. per input Min. Max. 2.0 2.7 to 3.6 2.7 to 3.6 Un it -40 to 85 o C V CC (V) V 0.8 VI = VI H or V IL VI = VI H or V IL V IO=-100 µA V CC -0.2 IO=-12 mA 2.2 IO=-18 mA 2.4 IO=-24 mA 2.2 V IO=100 µA 0.2 IO=12 mA 0.4 IO=16 mA 0.4 IO=24 mA 0.55 V VI = 0 to 5.5 V ±5 µA 2.7 to 3.6 VI = VIH or VIL VO = 0 to 5.5V ±5 µA 0 VI or VO = 5.5V 100 µA 2.7 to 3.6 VI = VCC or GND 10 VI or VO = 3.6 to 5.5V ±10 µA VIH = VCC -0.6V 500 µA 2.7 to 3.6 2.7 to 3.6 DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter Test Con dition s VOLP VOLV Dynamic Low Voltage Quiet Output (note 1) 3.3 Value Un it T A = 25 o C V CC (V) Min . C L = 50 pF V IL = 0 V V IH = 3.3V T yp. Max. 0.8 -0.8 V 1) Number ofoutputs defined as ”n”. Measured with”n-1” outputs switching from HIGH to LOW or LOW t o HIGH. The remaining output is measured in the LOW state. 4/10 74LCX374 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 2.5 ns) Symb ol Parameter V CC (V) Test Con dition Waveform tPLH tPHL Propagation Delay Time tPZL tPZH Output Enable Time to HIGH and LOW level 3.0 to 3.6 2.7 3.0 to 3.6 tPLZ tPHZ Output Disable Time from HIGh and LOW level 2.7 3.0 to 3.6 ts Setup Time, HIGh or LOW level Dn to CK 2.7 3.0 to 3.6 th Hold Time, HIGh or LOW level Dn to CK 2.7 fMAX Clock Pulse Frequency tOSLH tOSHL Output to Output Skew Time (note 1, 2) 3.0 to 3.6 tw CK Pulse Width, HIGH or LOW 1 1.5 1.5 1.5 8.5 9.5 8.5 2 1.5 1.5 8.5 7.5 1 2.5 2.5 2 2.7 3.0 to 3.6 2.7 3.0 to 3.6 3.0 to 3.6 Value -40 to 85 o C Min. Max. 1.5 9.5 1 ns ns ns 1.5 3.3 3.3 150 3 ns ns 1.5 1 Un it ns MHz 1.0 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|) 2) Parameter guaranteed by design CAPACITIVE CHARACTERISTICS Symb ol Parameter Test Co nditi ons Valu e Un it T A = 25 oC V CC (V) Min. T yp. Max. Input Capacitance 3.3 VIN = 0 to VCC 6 pF COUT Output Capacitance 3.3 VIN = 0 to VCC 12 pF CPD Power Dissipation Capacitance (note 1) 3.3 fIN = 10MHz VIN = 0 or VCC 32 pF C IN 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. Average operting current can be obtained by the following equation. I CC(opr) = CPD • VCC • fIN + ICC/8 (per Flip-Flop) 5/10 74LCX374 TEST CIRCUIT T EST tPLH , tPHL SW IT CH Open tPZL , tPLZ 6V tPZH , tPHZ GND CL = 50 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500Ω orequivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cicle) 6/10 74LCX374 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cicle) WAVEFORM 3: PULSE WIDTH 7/10 74LCX374 SO-20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8 (max.) P013L 8/10 74LCX374 TSSOP20 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 9/10 74LCX374 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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