74LVQ4066 QUAD BILATERAL SWITCH ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 0.4 ns (TYP.) at VCC = 3.3V tPD = 0.1 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW ”ON” RESISTANCE: RON = 20Ω at VCC = 3.3V, II/O ≤ 1mA RON = 12Ω at VCC = 5V, II/O ≤ 1mA SINE WAVE DISTORTION: 0.04% at VCC = 3.3V, f = 1KHz OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4066 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The LVQ4066 is a low voltage CMOS QUAD BILATERAL SWITCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVQ4066M 74LVQ4066T technology. It is ideal for low power and low noise 3.3V applications. It has an ON-resistance which is greatly reduced in comparison with 74HC4066. The C input is provided to control the switch; the switch is ON when the C input is held high and OFF when C is held low. PIN CONNECTION AND IEC LOGIC SYMBOLS October 1999 1/9 74LVQ4066 LOGIC DIAGRAM PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCT ION 1, 4, 8, 11 1 to 4 I/O Independent Input/Output 2, 3, 9, 10 1 to 4 O/I Independent Output/Input 13, 5, 6, 12 1C to 4C Enable Input (Active HIGH) 7 GND Ground (0V) 14 VCC Positive Supply Voltage TRUTH TABLE CONTROL SWITCH F UNCTIO N H ON L OFF ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ± 200 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage (note 1) Unit V V VI Input Voltage 0 to VCC VO Output Voltage 0 to VCC Top Operating Temperature: dt/dv Input Rise and Fall Time (note 2) 1) Truth Table guaranteed: 1.2V to 5.5V 2) VIN from 30% to70%VCC 2/9 Valu e 2 to 5.5 -40 to +85 0 to 10 V o C ns/V 74LVQ4066 DC SPECIFICATIONS Symb ol Parameter T est Cond ition s VIH High Level Input Voltage VIL Low Level Input Voltage R ON ON Resistance 3.3 5.0 (*) 3.3(**) 5.0 (*) ∆RON Difference of ON Resistance Between Switches Min. Input/Output Leakage Current (SWITCH OFF) 5.5 IIZ Switch Input Leakage Current (SWITCH ON, OUTPUT OPEN) 5.5 IIN Control Input Leakage Current 5.5 ICC Quiescent Supply Current 5.5 Max. V I = VI H V I/O = V CC to G ND II/ O ≤ 1mA V I = VI H V I/ O = VCC or GND II/ O ≤ 1mA V OS = V CC to GND V IS = V CC to G ND V I = V IL V OS = V CC to GND V I = VI H V I = VCC or GND V I = VCC or GND Min . Max. 0.7VCC 0.3VCC V I = VI H 3.0 V I/O = V CC to G ND to 5.5 II/ O ≤ 1mA IOFF Typ . Un it -40 to 85 o C 0.7VCC 2.7 to 5.5 (**) Value T A = 25 o C V CC (V) V 0.3VCC 20 30 40 12 18 24 10 15 20 9.5 14 19 V Ω 2 Ω ±0.1 ±1.0 ±0.1 ±1.0 ±0.1 ±1.0 µA 2 20 µA µA µA (*) Voltage range is 5V ± 0.5V (**) Voltagerange is 3.3V ± 0.3V 3/9 74LVQ4066 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input t r = tf =3 ns) Symb ol Parameter Test Co ndition V CC (V) tPD Delay Time 3.3(*) 5.0(**) tPZL tPZH Output Enable Time tPLZ tPHZ Output Disable Time 3.3(*) 5.0(**) 3.3(*) 5.0(**) C IN Input Capacitance CI/O Switch Terminal Capacitance CPD Power Dissipation Capacitance (note 1) Value T A = 25 o C Min. Typ . Max. 0.4 0.8 0.1 0.2 2.5 2.0 5.0 5.0 5 R L = 1kΩ R L = 1kΩ Un it -40 to 85 o C Min . Max. 1.2 1.0 4.0 4.0 7.5 7.5 5.0 5.0 9.0 9.0 ns ns pF 10 3.3 5.0 ns pF 2.5 3 pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/4 (switch). (*) Voltage range is 3.3V ± 0.3V (**) Voltagerange is 5V ± 0.5V ANALOG SWITCH CHARACTERISTICS (GND = 0 V, TA = 25oC) Symb ol fMAX Parameter Value Un it 0.04 0.04 % Adjust fI N voltage to Obtain 0dBm at V OS . Increase fIN Frequency until dB Meter reads -3dB R L = 50Ω, C L = 10pF 150 180 MHz 3.3 5.0(*) VIN is centered at VCC/2. Adjust input for 0dBm RL = 600Ω, CL = 50pF, fIN = 1MHz sine wave -60 -60 dB Crosstalk (Control Input to Signal Output) 3.3 5.0(*) R L = 600Ω, CL = 50pF, fIN = 1MHz square wave 60 60 mV Crosstalk (Between Any Switches) 3.3 5.0(*) RL = 600Ω, CL = 50pF, fIN = 1MHz sine wave -60 -60 dB Sine Wave Distortion (THD) V IN (Vp-p) 2.75 Frequency Response (Switch ON) 3.3 5.0(*) Feedthrough Attenuation (Switch OFF) (*) Voltage range is 5V ± 0.5V 4/9 Test Co nditi on V CC (V) 3.3 5.0(*) fIN = 1 KHz RL = 10KΩ CL = 50 pF 4 74LVQ4066 SWITCHING CHARACTERISTICS TEST CIRCUIT tPLZ, tPHZ, tPZL, tPZH. CROSSTALK (control to output) BANDWIDTH AND FEEDTHROUGH ATTENUATION GND (VSS) CI–O CI/O MAXIMUM CONTROL FREQUENCY GND (VSS) 5/9 74LVQ4066 CHANNEL RESISTANCE (RON) 6/9 ICC (Opr.) 74LVQ4066 SO-14 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 e3 0.050 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8 (max.) P013G 7/9 74LVQ4066 TSSOP14 MECHANICAL DATA mm DIM. MIN. inch TYP. A MAX. MIN. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b e K c E1 PIN 1 IDENTIFICATION 1 L E D 8/9 TYP. 74LVQ4066 Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com . 9/9