74LVQ74 DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 250 MHz (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.2 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The LVQ74 is a low voltage CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVQ74M 74LVQ74T 3.3V applications. A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/10 74LVQ74 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 13 1CLR, 2CLR Asyncronous Reset Direct Input NAME AND FUNCT ION 2, 12 1D, 2D Data Inputs 3, 11 1CK, 2CK Clock Input (LOW-to-HIGH, EdgeTriggered) 4, 10 1PR, 2PR Asyncronous Set - Direct Input 5, 9 1Q, 2Q True Flip-Flop Outputs 6, 8 1Q, 2Q Complement Flip-Flop Outputs 7 GND Ground (0V) 14 VCC Positive Supply Voltage TRUTH TABLE INPUTS OUT PUT S CLR PR D CK L H X H L X Q X L H CLEAR X H L PRESET X H H L H L L X H H L H H H H L H H X Qn Qn X:Don’t Care LOGIC DIAGRAM Thislogic diagram has notbe used to esimate propagation delays 2/10 F UNCTION Q NO CHANGE 74LVQ74 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ± 400 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage (note 1) Valu e Unit 2 to 3.6 V V VI Input Voltage 0 to VCC VO Output Voltage 0 to VCC Top dt/dv Operating Temperature: Input Rise and Fall Time (VCC = 3V) (note 2) -40 to +85 0 to 10 V o C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V 3/10 74LVQ74 DC SPECIFICATIONS Symb ol Parameter Test Co nditions VIH High Level Input Voltage VIL Low Level Input Voltage VOH VOL High Level Output Voltage Low Level Output Voltage Min. 3.0 T yp. Un it -40 to 85 o C Max. 2.0 3.0 to 3.6 3.0 Valu e T A = 25 oC V CC (V) Min. 0.8 (* ) VI = V IH or V IL VI(*) = VIH or VIL Max. 2.0 I O =-50 µA 2.9 IO=-12 mA 2.58 2.99 V 0.8 V 2.9 V 2.48 IO=-24 mA 2.2 IO=50 µA 0.002 0.1 0.1 IO=12 mA 0 0.36 0.44 IO=24 mA V 0.55 Input Leakage Current 3.6 VI = VCC or GND ±0.1 ±1 µA ICC Quiescent Supply Current 3.6 VI = VCC or GND 2 20 µA IOLD Dynamic Output Current (note 1, 2) 3.6 VOLD = 0.8 V max 36 mA VOHD = 2 V min -25 mA II IOHD 1) Maximum test duration 2ms, one output loaded attime 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω. (*) All outputs loaded. DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter Test Co nditions Dynamic Low Voltage Quiet Output (note 1, 2) 3.3 VIHD Dynamic High Voltage Input (note 1, 3) 3.3 VILD Dynamic Low Voltage Input (note 1, 3) 3.3 VOLP VOLV Valu e T A = 25 oC V CC (V) Min. T yp. Max. 0.2 0.8 -0.8 -0.2 2 C L = 50 pF Un it -40 to 85 o C Min. Max. V 0.8 1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz 4/10 74LVQ74 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns) Symb ol Parameter T est Con ditio n V CC (V) tPLH tPHL Propagation Delay Time CK to Q 2.7 3.3(*) tPLH tPHL Propagation Delay Time PR or CLR to Q 2.7 3.3(*) Pulse Width CK, HIGH or LOW 3.3 (*) Pulse Width PR or CLR, LOW 2.7 3.3(*) ts Setup Time D to CK HIGH or LOW th Valu e T A = 25 oC -40 to Min. T yp. Max. Min. 8.0 19.0 6.5 13.0 ns 16.0 12.0 19.0 13.0 1.5 7.0 10.0 1.5 5.0 7.0 1.5 1.5 7.0 5.0 10.0 7.0 ns 2.7 3.3(*) -0.2 -0.2 5.0 4.0 6.0 5.0 ns Hold Time Q to CK HIGH or LOW 2.7 3.3(*) 0.2 0.2 2.0 2.0 2.0 2.0 ns Recovery Time PR or CLR to Q 3.3 fMAX Maximum Clock Frequency 2.7 3.3(*) tOSLZ tOSHL Output to Output Skew Time (note 1, 2) 2.7 3.3(*) tw tw(L) tREM 7.0 6.0 Un it 85 o C Max. 21.0 14.0 2.7 2.7 (*) 60 100 -1.0 1.0 1.0 -1.0 1.0 1.0 200 250 40 100 0.5 0.5 1.0 1.0 ns ns ns MHz 1.5 1.5 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design CAPACITIVE CHARACTERISTICS Symb ol Parameter Test Co nditions C IN Input Capacitance 3.3 CPD Power Dissipation Capacitance (note 1) 3.3 Valu e o T A = 25 C V CC (V) Min. fIN = 10 MHz T yp. 4 33 Max. Un it o -40 to 85 C Min. Max. pF pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n(per circuit) 5/10 74LVQ74 TEST CIRCUIT CL = 50 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500Ω orequivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/10 74LVQ74 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 7/10 74LVQ74 WAVEFORM 3: RECOVERY TIMES (f=1MHz; 50% duty cycle) WAVEFORM 4: PULSE WIDTH 8/10 74LVQ74 SO-14 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 e3 0.050 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8 (max.) P013G 9/10 74LVQ74 TSSOP14 MECHANICAL DATA mm DIM. MIN. inch TYP. A MAX. MIN. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b e K c E1 PIN 1 IDENTIFICATION 1 L E D 10/10 TYP. 74LVQ74 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com . 11/10