74V1T125 SINGLE BUS BUFFER (3-STATE) ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 1 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUT SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74V1T125 is an advanced high-speed CMOS SINGLE BUS BUFFER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. S (SOT23-5L) C (SC-70) ORDER CODE: 74V1T125S 3-STATE control input G has to be set high to place the output into the high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. PIN CONNECTION AND IEC LOGIC SYMBOLS October 1999 1/8 74V1T125 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 1G Output Enable Input NAME AND FUNCT ION 2 1A Data Input 4 1Y Data Output 3 GND Ground (0V) 5 VCC Positive Supply Voltage TRUTH TABLE A G Y X H Z L L L H L H X:”H” or ”L” Z:High Impedance ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (see note 1) -0.5 to +7.0 V VO DC Output Voltage (see note 2) -0.5 to VCC + 0.5 V VCC IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 50 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 260 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) Output in OFF state 2) High or Low State RECOMMENDED OPERATING CONDITIONS Symbol Parameter 4.5 to 5.5 V Input Voltage 0 to 5.5 V VO Output Voltage (see note 1) 0 to 5.5 V VO Output Voltage (see note 2) Top Operating Temperature dt/dv Input Rise and Fall Time (see note 3) (V CC = 5.0 ± 0.5V) 1) Output in OFF state 2) High or Low State 3)VIN from0.8V to 2 V 2/8 Unit VI VCC Supply Voltage Valu e 0 to VCC -40 to +85 0 to 20 V o C ns/V 74V1T125 DC SPECIFICATIONS Symb ol Parameter T est Cond ition s Min. 2 VIH High Level Input Voltage 4.5 to 5.5 VIL Low Level Input Voltage 4.5 to 5.5 VOH High Level Output Voltage VOL IOZ II Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Value o Typ . Un it o T A = 25 C V CC (V) -40 to 85 C Max. Min . Max. 2 0.8 V 0.8 V 4.5 I O =-50 µA 4.4 4.5 IO=-8 mA 3.94 4.5 I O=50 µA 0.1 0.1 4.5 IO=8 mA 0.36 0.44 VI = VIH or VIL VO = VCC or GND ±0.25 ±2.5 µA 5.5 0 to 5.5 VI = 5.5V or GND ±0.1 ±1.0 µA 4.5 4.4 V 3.8 0.0 V ICC Quiescent Supply Current 5.5 VI = VCC or GND 1 10 µA ∆ICC Additional Worst Case Supply Current 5.5 One Input at 3.4V, other input at VCC or GND 1.35 1.5 mA IOPD Output Leakage Current 0 VOUT = 5.5V 0.5 5.0 µA 0 AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns) Symb ol Parameter Test Co ndition V CC (*) CL (pF ) (V) Value T A = 25 o C Min. Un it -40 to 85 o C tPLH tPHL Propagation Delay Time 5.0 15 Typ . 3.8 Max. 5.5 Min . 1.0 Max. 6.5 5.0 50 5.3 7.5 1.0 8.5 tPLZ tPHZ Output Disable Time 5.0 5.0 15 50 3.6 5.1 5.1 7.1 1.0 1.0 6.0 8.0 ns tPZH tPZL Output Enable Time 5.0 50 6.1 8.8 1.0 10.0 ns ns (*) Voltage range is 5V ± 0.5V CAPACITIVE CHARACTERISTICS Symb ol Parameter T est Cond ition s Value o T A = 25 C Min. C IN Input Capacitance Un it o -40 to 85 C Typ . Max. 4 10 Min . Max. 10 pF COUT Output Capacitance 10 pF CPD Power Dissipation Capacitance (note 1) 14 pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC •fIN + ICC 3/8 74V1T125 TEST CIRCUIT T EST tPLH , tPHL SW IT CH Open tPZL , tPLZ VCC tPZH , tPHZ GND CL = 15/50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 1KΩ orequivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 4/8 74V1T125 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 5/8 74V1T125 SOT23-5L MECHANICAL DATA mm DIM. MIN. 6/8 TYP. mils MAX. MIN. TYP. MAX. A 0.90 1.45 35.4 57.1 A1 0.00 0.15 0.0 5.9 A2 0.90 1.30 35.4 51.2 b 0.35 0.50 13.7 19.7 C 0.09 0.20 3.5 7.8 D 2.80 3.00 110.2 118.1 E 2.60 3.00 102.3 118.1 E1 1.50 1.75 59.0 68.8 L 0.35 0.55 13.7 21.6 e 0.95 37.4 e1 1.9 74.8 74V1T125 SC-70 MECHANICAL DATA mm DIM. MIN. TYP. mils MAX. MIN. TYP. MAX. A 0.80 1.10 31.5 43.3 A1 0.00 0.10 0.0 3.9 A2 0.80 1.00 31.5 39.4 b 0.15 0.30 5.9 11.8 C 0.10 0.18 3.9 7.1 D 1.80 2.20 70.9 86.6 E 1.80 2.40 70.9 94.5 E1 1.15 1.35 45.3 53.1 L 0.10 0.30 3.9 11.8 e 0.65 25.6 e1 1.3 51.2 7/8 74V1T125 Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com . 8/8