STMICROELECTRONICS ACST4-7SFP

®
ASD™
AC Switch Family
MAIN APPLICATIONS
AC static switching in appliance control systems
Drive of low power high inductive or resistive
loads like
- spray pump in dishwashers
- fan in air-conditioners
■
ACST4 Series
AC POWER SWITCH
OUT
■
FEATURES
■
■
■
■
■
■
■
G
COM
DPAK
ACST4-7SB/CB
Blocking voltage : VDRM / VRRM = +/-700V
Avalanche controlled : VCL typ = 1100 V
Nominal conducting current : IT(RMS) = 4A
High surge current capability: 30A for 20ms full
wave
Gate triggering current : IGT < 10 mA or 25mA
Switch integrated driver
High noise immunity : static dV/dt >500V/µs
BENEFITS
Enables equipment to meet IEC 61000-4-5
High off-state reliability with planar technology
No external overvoltage protection needed
Reduces the power component factor
Interfaces directly with the microcontroller
Direct interface with the microcontroller for the
ACST4-7S (IGT < 10mA)
G
OUT
COM
TO-220FPAB
ACST4-7SFP/CFP
■
■
■
■
■
■
FUNCTIONAL DIAGRAM
OUT
DESCRIPTION
The ACST4 belongs to the AC power switch family
built around the ASD™ technology. This high performance device is adapted to home appliances or
inductrial systems and drives loads up to 4 A.
The ACS™ switch embeds a Triac structure with a
high voltage clamping device to absorb the inductive turn-off energy and withstand line transients
such as those described in the IEC61000-4-5 standards.
COM
January 2003 - Ed: 3A
G
1/9
ACST4 Series
ABSOLUTE RATINGS (limiting values)
For either positive or negative polarity of pin OUT voltage in respect to pin COM voltage
Symbol
VDRM / VRRM
IT(RMS)
ITSM
I2t
Parameter
Value
Unit
Tj = -10 °C
700
V
DPAK
Tc = 110 °C
4
A
TO-220FPAB
Tc = 100 °C
30
A
Repetitive peak off-state voltage
RMS on-state current full cycle sine
wave 50 to 60 Hz
Non repetitive surge peak on-state current
Tj initial = 25°C, full cycle sine wave
F =50 Hz
F =60 Hz
33
A
Fusing capability
tp = 10ms
6.4
A²s
F = 120 Hz
50
A/µs
dI/dt
Repetitive on-state current critical rate
of rise IG = 10mA (tr < 100ns)
VPP
Non repetitive line peak pulse voltage
Tstg
Tj = 125°C
note 1
2
kV
Storage temperature range
- 40 to + 150
°C
Tj
Operating junction temperature range
- 30 to + 125
°C
Tl
Maximum lead soldering temperature during 10s
260
°C
Value
Unit
Note 1: according to test described by IEC61000-4-5 standard & Figure B.
GATE CHARACTERISTICS (maximum values)
Symbol
PG (AV)
Parameter
Average gate power dissipation
0.1
W
PGM
Peak gate power dissipation (tp = 20µs)
10
A
IGM
Peak gate current (tp = 20µs)
1
V
THERMAL RESISTANCES
Symbol
Rth (j-a)
Rth (j-l)
Parameter
Junction to ambient
Junction to case for full cycle sine wave
conduction
S = Copper surface under Tab
2/9
Value
Unit
70
°C/W
TO-220FPAB
60
°C/W
DPAK
2.6
°C/W
TO-220FPAB
4.6
°C/W
S = 0.5cm²
DPAK
ACST4 Series
PARAMETER DESCRIPTION
Parameter Symbol
Parameter description
IGT
Triggering gate current
VGT
Triggering gate voltage
VGD
Non-triggering gate voltage
IH
Holding current
IL
Latching current
VTM
Peak on-state voltage drop
VTO
On state threshold voltage
Rd
On state dynamic resistance
IDRM / IRRM
Maximum forward or reverse leakage current
dV/dt
Critical rate of rise of off-state voltage
(dV/dt)c
Critical rate of rise of commutating off-state voltage
(dI/dt)c
Critical rate of decrease of commutating on-state current
VCL
Clamping voltage
ICL
Clamping current
ELECTRICAL CHARACTERISTICS
For either positive or negative polarity of pin OUT voltage in respect to pin COM voltage.
Symbol
Test Conditions
ACST4-7S
ACST4-7C
Unit
IGT
VOUT=12V (DC)
RL=33Ω
QI - QII - QIII
Tj=25°C
MAX
10
25
mA
VGT
VOUT=12V (DC)
RL=33Ω
QI - QII - QIII
Tj=25°C
MAX
1
1.1
V
VGD
VOUT=VDRM RL=3.3kΩ
Tj=125°C
MIN
0.2
V
IH
IOUT= 100mA gate open
Tj=25°C
MAX
20
35
mA
IL
IG= 2 x IGtmax
Tj=25°C
MAX
40
60
mA
IOUT = 5.6A
Tj=25°C
MAX
1.5
V
VTO
Tj=125°C
MAX
0.90
V
Rd
Tj=125°C
MAX
100
mΩ
Tj=25°C
MAX
10
µA
VTM
tp=380µs
IDRM /
IRRM
VOUT = 700V
Tj=125°C
MAX
dV/dt
VOUT=460V gate open
Tj=110°C
MIN
200
500
V/µs
(dV/dt)c = 15V/µs
Tj=125°C
MIN
2.0
2.5
A/ms
ICL = 1mA
Tj=25°C
TYP
(dI/dt)c
VCL
tp=1ms
500
1100
V
3/9
ACST4 Series
AC LINE SWITCH BASIC APPLICATION
The ACST4 device has been designed to switch on & off low power, but highly inductive or resistive loads
such as dishwashers spray pumps, and air-conditioners fan.
Pin COM: Common drive reference to connect to the power line neutral
Pin G: Switch Gate input to connect to the digital controller
Pin OUT: Switch Output to connect to the load
ACST4-7S triggering current has to be sunk from the gate pin G. The switch can then be driven directly by
logic level circuits through a resistor as shown on the typical application diagram ( Fig A ).
Thanks to its thermal and turn off commutation performances, the ACST4 switch is able to drive with no
turn off additional snubber an inductive load up to 4 A.
TYPICAL APPLICATION DIAGRAM (Fig. A)
LOAD
L
L
AC
MAINS
M
R
N
OUT
OUT
ACST4
COM
G
ST72 MCU
- Vcc
AC LINE TRANSIENT VOLTAGE RUGGEDNESS
The ACST4 switch is able to sustain safely the AC line transient voltages either by clamping the low energy
spikes or by breaking over under high energy shocks, even with high turn-on current rises.
The test circuit of the figure 2 is representative of the final ACST application and is also used to stress the
ACST switch according to the IEC 61000-4-5 standard conditions. Thanks to the load, the ACST switch
sustains the voltage spikes up to 2 kV above the peak line voltage. It will break over safely even on resistive
load where the turn on current rate of rise, is as high as shown on figure 3. Such non-repetitive test can be
done 10 times on each AC line voltage polarity.
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ACST4 Series
Fig. B: Overvoltage ruggedness test circuit for resistive and inductive loads according to
IEC61000-4-5 standards.
R = 150Ω, L = 10µH, VPP = 2kV.
Fig. C: Current and Voltage of the ACST4 during IEC61000-4-5 standard test with R, L & VPP .
L
R
OUT
ACST4
SURGE VOLTAGE
AC LINE & GENERATOR
VAC + V PP
G
COM
RG = 220Ω
Fig. 1: Maximum power dissipation versus RMS
on-state current.
Fig. 2-1: RMS on-state current versus case
temperature.
P(W)
IT(RMS)(A)
5.0
4.5
DPAK
α=180°
4.5
4.0
4.0
3.5
3.5
3.0
TO-220FPAB
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
180°
1.0
α
α
0.5
0.5
IT(RMS)(A)
0.0
0.5
1.0
1.5
2.0
Tc(°C)
α=180°
0.0
0.0
2.5
3.0
3.5
4.0
0
25
50
75
100
125
5/9
ACST4 Series
Fig. 2-2: RMS on-state current versus ambient
temperature.
Fig. 3: Relative variation of thermal impedance
versus pulse duration.
IT(RMS)(A)
K = [Zth/Rth]
2.0
1.00
α=180°
Printed circuit board FR4
Natural convection
S=0.5cm²
1.8
1.6
DPAK
Zth(j-c)
TO-220FPAB
1.4
1.2
DPAK
Zth(j-a)
1.0
0.10
TO-220FPAB
0.8
0.6
0.4
0.2
Tamb(°C)
tp(s)
0.0
0
25
50
75
100
125
0.01
1.E-02
Fig. 4: Relative variation of gate trigger current,
holding current and latching versus junction
temperature (typical values).
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
Fig. 5: Relative variation of static dV/dt versus
junction temperature.
dV/dt [Tj] / dV/dt [Tj = 125°C]
IGT, IH, IL [Tj] / IGT, IH, IL [Tj = 25°C]
8
3.0
Vout=460V
7
2.5
IGT
6
2.0
5
4
1.5
3
1.0
IL & I H
2
0.5
1
Tj(°C)
Tj(°C)
0
0.0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
Fig. 6-1: Relative variation of critical rate of decrease of main current versus reapplied dV/dt
(typical values).
25
50
75
100
125
Fig. 6-2: Relative variation of critical rate of decrease of main current versus reapplied dV/dt
(typical values).
(dI/dt)c [(dV/dt)c] / Specified (dI/dt)c
(dI/dt)c [(dV/dt)c] / Specified (dI/dt)c
1.2
1.2
Vout=300V
Vout=300V
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
ACST4-7C
ACST4-7S
(dV/dt)c(V/µs)
(dV/dt)c(V/µs)
0.0
0.0
0
6/9
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
25
30
35
40
45
50
ACST4 Series
Fig. 7: Relative variation of critical rate of decrease
of main current versus junction temperature.
Fig. 8: Surge peak on-state current versus number
of cycles.
(dI/dt)c [Tj] / (dI/dt)c [Tj = 125°C]
ITSM(A)
6
35
Vout=300V
30
5
t=20ms
Non repetitive
Tj initial=25°C
25
4
20
3
15
2
Repetitive
TC=100°C
10
1
5
Tj(°C)
Number of cycles
0
0
25
50
75
100
125
Fig. 9: Non repetitive surge peak on-state current
for a sinusoidal pulse with width tp < 10ms, and
corresponding value of I²t.
1
10
Fig. 10:
values).
On-state
100
1000
characteristics
(maximum
ITM(A)
ITSM(A), I²t (A²s)
100.00
1000
Tj max. :
Vto= 0.90 V
Rd= 100 mΩ
Tj initial=25°C
dI/dt limitation:
50A/µs
10.00
100
ITSM
Tj=125°C
10
1.00
I²t
Tj=25°C
VTM(V)
tp(ms)
0.10
1
0.01
0.10
1.00
10.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Fig. 11: Thermal resistance junction to ambient
versus copper surface under tab (printed circuit
board FR4, copper thickness: 35µm)
Rth(j-a)(°C/W)
100
DPAK
90
80
70
60
50
40
30
20
10
S(cm²)
0
0
5
10
15
20
25
30
35
40
7/9
ACST4 Series
ORDERING INFORMATION
ACST
4
-
7
X
X
AC Switch
IT(RMS)
4 = 4A
Package
B = DPAK
FP = TO-220FPAB
Gate Sensitivity
S= 10mA
C = 25mA
VDRM
7 = 700V
PACKAGE OUTLINE MECHANICAL DATA
DPAK
DIMENSIONS
REF.
Millimeters
Min.
Max
Min.
Max.
A
2.20
2.40
0.086
0.094
A1
0.90
1.10
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.90
0.025
0.035
B2
5.20
5.40
0.204
0.212
C
0.45
0.60
0.017
0.023
C2
0.48
0.60
0.018
0.023
D
6.00
6.20
0.236
0.244
E
6.40
6.60
0.251
0.259
G
4.40
4.60
0.173
0.181
H
9.35
10.10
0.368
0.397
L2
FOOT PRINT
DPAK
6.7
6.7
3
3
1.6
1.6
2.3
8/9
2.3
Inches
0.80 typ.
0.031 typ.
L4
0.60
1.00
0.023
0.039
V2
0°
8°
0°
8°
ACST4 Series
PACKAGE OUTLINE MECHANICAL DATA
TO-220FPAB
DIMENSIONS
REF.
B
Dia
L6
L2
Inches
Min.
Max.
Min.
Max.
A
4.4
4.6
0.173
0.181
A
H
Millimeters
B
2.5
2.7
0.098
0.106
D
2.5
2.75
0.098
0.108
E
0.45
0.70
0.018
0.027
F
0.75
1
0.030
0.039
F1
1.15
1.70
0.045
0.067
F2
1.15
1.70
0.045
0.067
G
4.95
5.20
0.195
0.205
G1
2.4
2.7
0.094
0.106
H
10
10.4
0.393
0.409
L7
L3
L5
D
F1
L4
L2
F2
F
E
G1
G
16 Typ.
0.63 Typ.
L3
28.6
30.6
1.126
1.205
L4
9.8
10.6
0.386
0.417
L5
2.9
3.6
0.114
0.142
L6
15.9
16.4
0.626
0.646
L7
9.00
9.30
0.354
0.366
OTHER INFORMATION
■
Ordering type
Marking
Package
Weight
Base qty
Delivery mode
ACST4-7SB
ACST47S
DPAK
0.3 g
75
Tube
ACST4-7SB-TR
ACST47S
DPAK
0.3 g
2500
Tape & reel
ACST4-7SFP
ACST47S
TO-220FPAB
2.4 g
50
Tube
ACST4-7CB
ACST47C
DPAK
0.3 g
75
Tube
ACST4-7CB-TR
ACST47C
DPAK
0.3 g
2500
Tape & reel
ACST4-7CFP
ACST47C
TO-220FPAB
2.4 g
50
Tube
Epoxy meets UL94,V0
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implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied.
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