ETL9444/ETL9445 ETL9344/ETL9345 4-BIT NMOS MICROCONTROLLERS .. .. . .. .. . . . .. . . . . LOW COST POWERFUL INSTRUCTION SET 2k x 8 ROM, 128 x 4 RAM 23 I/O LINES (ETL9444) TRUE VECTORED INTERRUPT, PLUS RESTART THREE-LEVEL SUBROUTINE STACK 16µs INSTRUCTION TIME SINGLE SUPPLY OPERATION (4.5-6.3V) LOW CURRENT DRAIN (13mA max.) INTERNAL TIME-BASE COUNTER FOR REALTIME PROCESSING INTERNAL BINARY COUNTER REGISTER WITH MICROWIRE SERIAL I/O CAPABILITY GENERAL PURPOSE AND TRI-STATE OUTPUTS LSTTL/CMOS COMPATIBLE IN AND OUT DIRECT DRIVE OF LED DIGIT AND SEGMENT LINES SOFTWARE/HARDWARE COMPATIBLE WITH OTHER MEMBERS OF ET9400 FAMILY EXTENDED TEMPERATURE RANGE DEVICES ETL9344/L9345 (– 40°C to + 85°C) WIDER SUPPLY RANGE (4.5 – 9.5V) OPTIONALLY AVAILABLE SOIC 24/28 AND PLCC 28 PACKAGES AVAILABLE ETL9444/ETL9344 N (Plastic Package) ETL9345/ETL9345 N (Plastic Package) PIN CONNECTION DESCRIPTION The ETL9444/L9445 and ETL9344/L9345 SingleChip N-Channel Microcontrollers are fully compatible with the COPS family, fabricated using N-channel, silicon gate XMOS technology. They are complete microcomputers containing all system timing, internal logic, ROM, RAM and I/O necessary to implement dedicated control functions in a variety of applications. Features include single supply operation, a variety of output configuration options, with an instruction set, internal architecture and I/O scheme designed to facilitate keyboard input, display output and BCD data manipulation. The ETL9445 is identical to the ETL9444, except with 19 I/O lines instead of 23 : They are an appropriate choice for use in numerous human interface control environments. Standard test procedures and reliable high-density fabrication techniques provide the medium to large volume customers with a customiMay 1989 1/27 ETL9444/9445–ETL9344/9345 zed controller oriented processor at a low end-product cost. Figure 1 : Block Diagram (28-pin version). 2/27 The ETL9344/L9345 are exact functional equivalents, but extended temperature range versions of the ETL9444/L9445 respectively. ETL9444/9445–ETL9344/9345 ETL9444/L9445 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Voltage at any Pin Relative to GND – 0.5 to + 10 V 0 to + 70 °C – 65 to + 150 °C 300 °C Ambient Operating Temperature Ambient Storage Temperature Lead Temperature (soldering, 10 seconds) Power Dissipation Unit 0.75W at 25°C 0.4W at 70°C Total Source Current 120 mA Total Sink Current 120 mA Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. DC ELECTRICAL CHARACTERISTICS 0°C ≤ T A ≤ + 70°C, 4.5V ≤ V C C ≤ 9.5V (unless otherwise specified) Parameter Standard Operating Voltage (V CC ) Optional Operating Voltage (V CC ) Power Supply Ripple Operating Supply Current Input Voltage Levels CKI Input Levels Crystal Input (÷ 32, ÷ 16, ÷ 8) Logic High (V IH) Logic Low (V IL ) Schmitt Trigger Input (÷ 4) Logic High (V IH) Logic Low (V IL ) RESET Input Levels Logic High Logic Low SO Input Level (test mode) All Other Inputs Logic High Logic High Logic Low Logic High Logic Low Input Capacitance Hi-Z Input Leakage Test Conditions Min. Max. Unit 4.5 4.5 6.3 9.5 0.5 13 V V V mA 2.0 – 0.3 0.4 V V 0.7 V CC – 0.3 0.6 V V 0.7 V CC – 0.3 2.0 0.6 2.5 V V V Note 1 Peak to Peak All Inputs and Outputs Open Schmitt Trigger Input V CC = Max. With TTL trip level options selected, V CC = 5V ± 5%. With high trip level options selected. 3.0 2.0 – 0.3 3.6 – 0.3 –1 Output Voltage Levels LSTTL Operation Logic High (V OH ) Logic Low (V OL ) V CC = 5V ± 5% I OH = – 25µA I OL = 0.36mA CMOS Operation Logic High Logic Low I OH = – 10µA I OL = + 10µA 1.2 7 +1 V V V V V pF µA 0.4 V V 0.2 V V 0.8 2.7 V CC – 1 Note : 1. VCC voltage change must be less than 0.5V in a 1ms period to maintain proper operation. 3/27 ETL9444/9445–ETL9344/9345 ETL9444/L9445 DC ELECTRICAL CHARACTERISTICS (continued) Parameter Output Current Levels Output Sink Current SO and SK Outputs (I OL ) L 0 -L 7 Outputs and Standard G 0 -G 3 , D 0 -D 3 Outputs (I OL ) G 0 -G 3 and D 0 -D 3 Outputs with High Current Options (I OL ) G 0 -G 3 and D 0 -D 3 Outputs with Very High Current Options (I OL ) CKI (single-pin RC oscillator) CKO Output Source Current Standard Configuration, All Outputs (I OH ) Push-pull Configuration SO and SK Outputs (I OH ) LED Configuration, L 0 -L 7 Outputs, Low Current Driver Option (I OH ) LED Configuration, L 0 -L 7 Outputs, High Current Driver Option (I OH ) TRI-STATE Configuration, L 0 -L 7 Outputs, Low Current Driver Option (I OH ) TRI-STATE Configuration, L 0 -L 7 Outputs, High Current Driver Option (I OH ) Input Load Source Current CKO Output RAM Power Supply Option Power Requirement TRI-STATE Output Leakage Current Total Sink Current Allowed All Outputs Combined D, G Ports L 7 -L 4 L 3 -L 0 All Other Pins Total Source Current Allowed All I/O Combined L 7 -L 4 L 3 -L 0 Each L Pin All Other Pins 4/27 Test Conditions V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC = 9.5V, V OL = 0.4V = 6.3V, V OL = 0.4V = 4.5V, V OL = 0.4V = 9.5V, V OL = 0.4V = 6.3V, V OL = 0.4V = 4.5V, V OL = 0.4V = 9.5V, V OL = 1.0V = 6.3V, V OL = 1.0V = 4.5V, V OL = 1.0V = 9.5V, V OL = 1.0V = 6.3V, V OL = 1.0V = 4.5V, V OL = 1.0V = 4.5V, V IH = 3.5V = 4.5V, V OL = 0.4V V CC V CC V CC V CC V CC V CC = 9.5V, V OH = 6.3V, V OH = 4.5V, V OH = 9.5V, V OH = 6.3V, V OH = 4.5V, V OH Min. Max. Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1.8 1.2 0.9 0.8 0.5 0.4 15 11 7.5 30 22 15 2 0.2 – 140 – 75 – 30 – 1.4 – 1.4 – 1.2 – 800 – 480 – 250 µA µA µA mA mA mA V CC = 9.5V, V OH = 2.0V V CC = 6.0V, V OH = 2.0V – 1.5 – 1.5 – 18 – 13 mA mA V CC V CC V CC V CC V CC V CC V CC V CC V CC – 3.0 – 3.0 – 0.75 – 0.8 – 0.9 – 1.5 – 1.6 – 1.8 – 10 – 35 – 25 mA mA mA mA mA mA mA mA µA = 2.0V = 2.0V = 2.0V = 4.75V = 2.4V = 1.0V = 9.5V, V OH = 2.0V = 6.0V, V OH = 2.0V = 9.5V, V OH = 5.5V = 6.3V, V OH = 3.2V = 4.5V, V OH = 1.5V = 9.5V, V OH = 5.5V = 6.3V, V OH = 3.2V = 4.5V, V OH = 1.5V = 5.0V, V IL = 0V – 140 mA V R = 3.3V 6.0 µA – 2.5 + 2.5 120 120 4 4 1.5 mA mA mA mA mA 120 60 60 30 1.5 mA mA mA mA mA ETL9444/9445–ETL9344/9345 ETL9344/L9345 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit – 0.5 to + 10 V Ambient Operating Temperature – 40 to + 85 °C Ambient Storage Temperature – 65 to + 150 °C 300 °C Voltage at any Pin Relative to GND Lead Temperature (soldering, 10 seconds) Power Dissipation 0.75W at 25°C 0.25W at 85°C Total Source Current 120 mA Total Sink Current 120 mA Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. DC ELECTRICAL CHARACTERISTICS – 40°C ≤ T A ≤ + 85°C, 4.5V ≤ V C C ≤ 7.5V (unless otherwise specified) Parameter Standard Operating Voltage (V CC ) Optional Operating Voltage (V CC ) Power Supply Ripple Operating Supply Current Input Voltage Levels CKI Input Levels Crystal Input Logic High (V IH) Logic Low (V IL ) Schmitt Trigger Input Logic High (V IH) Logic Low (V IL ) RESET Input Levels Logic High Logic Low SO Input Level (test mode) All Other Inputs Logic High Logic High Logic Low Logic High Logic Low Input Capacitance Hi-Z Input Leakage Test Conditions Min. Max. Unit 4.5 4.5 5.5 7.5 0.5 15 V V V mA 2.2 – 0.3 0.3 V V 0.7 V CC – 0.3 0.4 V V 0.7 V CC – 0.3 2.2 0.4 2.5 V V V Note 1 Peak to Peak All Inputs and Outputs Open Schmitt Trigger Input V CC = Max. With TTL trip level options selected, V CC = 5V ± 5% With high trip level options selected 3.0 2.2 – 0.3 3.6 – 0.3 –2 Output Voltage Levels LSTTL Operation Logic High (V OH ) Logic Low (V OL ) V CC = 5V ± 5% I OH = – 20µA I OL = 0.36mA CMOS Operation Logic High Logic Low I OH = – 10µA I OL = + 10µA 1.2 7 +2 V V V V V pF µA 0.4 V V 0.2 V V 0.6 2.7 V CC – 1 Note : 1. VCC voltage change must be less than 0.5V in a 1ms period to maintain proper operation. 5/27 ETL9444/9445–ETL9344/9345 ETL9344/L9345 DC ELECTRICAL CHARACTERISTICS (continued) Parameter Output Current Levels Output Sink Current SO and SK Outputs (I OL ) L 0 -L 7 Outputs and Standard G 0 -G 3 , D 0 -D 3 Outputs (I OL ) G 0 -G 3 and D 0 -D 3 Outputs with High Current Options (I OL ) G 0 -G 3 and D 0 -D 3 Outputs with Very High Current Options (I OL ) CKI (single-pin RC oscillator) CKO Output Source Current Standard Configuration, All Outputs (I OH ) Push-pull Configuration SO and SK Outputs (I OH ) LED Configuration, L 0 -L 7 Outputs, Low Current Driver Option (I OH ) LED Configuration, L 0 -L 7 Outputs, High Current Driver Option (I OH ) TRI-STATE Configuration, L 0 -L 7 Outputs, Low Current Driver Option (I OH ) TRI-STATE Configuration, L 0 -L 7 Outputs, High Current Driver Option (I OH ) Input Load Source Current CKO Output RAM Power Supply Option Power Requirement TRI-STATE Output Leakage Current Total Sink Current Allowed All Outputs Combined D. G Ports L 7 -L 4 L 3 -L 0 All Other Pins Total Source Current Allowed All I/O Combined L 7 -L 4 L 3 -L 0 Each L Pin All Other Pins 6/27 Test Conditions V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC = 7.5V, V OL = 0.4V = 5.5V, V OL = 0.4V = 4.5V, V OL = 0.4V = 7.5V, V OL = 0.4V = 5.5V, V OL = 0.4V = 4.5V, V OL = 0.4V = 7.5V, V OL = 1.0V = 5.5V, V OL = 1.0V = 4.5V, V OL = 1.0V = 7.5V, V OL = 1.0V = 5.5V, V OL = 1.0V = 4.5V, V OL = 1.0V = 4.5V, V IH = 3.5V = 4.5V, V OL = 0.4V V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC = 7.5V, V OH = 2.0V = 5.5V, V OH = 2.0V = 4.5V, V OH = 2.0V = 7.5V, V OH = 3.75V = 5.5V, V OH = 2.0V = 4.5V, V OH = 1.0V = 7.5V, V OH = 2.0V = 6.0V, V OH = 2.0V = 5.5V, V OH = 2.0V = 7.5V, V OH = 2.0V = 6.0V, V OH = 2.0V = 5.5V, V OH = 2.0V = 7.5V, V OH = 4.0V = 5.5V, V OH = 2.7V = 4.5V, V OH = 1.5V = 7.5V, V OH = 4.0V = 5.5V, V OH = 2.7V = 4.5V, V OH = 1.5V = 5.0V, V IL = 0V Min. Max. mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1.4 1.0 0.8 0.6 0.5 0.4 12 9 7 24 18 14 2 0.2 – 100 – 55 – 28 – 0.85 – 1.1 – 1.2 – 1.4 – 1.4 – 0.7 – 2.7 – 2.7 – 1.4 – 0.7 – 0.6 – 0.9 – 1.4 – 1.2 – 1.8 – 10 Unit – 900 – 600 – 350 – – – – – – 27 17 15 54 34 30 – 200 µA µA µA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA µA mA V R = 3.3V 8.0 µA –5 +5 120 120 4 4 1.5 mA mA mA mA mA 120 60 60 30 1.5 mA mA mA mA mA ETL9444/9445–ETL9344/9345 AC ELECTRICAL CHARACTERISTICS ETL9444/L9445 : 0°C ≤ T A ≤ + 70°C, 4.5V ≤ V C C ≤ 9.5V (unless otherwise specified) ETL9344/L9345 : – 40°C ≤ T A ≤ + 85°C, 4.5V ≤ V C C ≤ 7.5V (unless otherwise specified) Parameter Instruction Cycle Time – t c CKI Input Frequency – f I Duty Cycle Rise Time Fall Time CKI Using RC (÷ 4) Test Conditions ÷ ÷ ÷ ÷ 32 Mode 16 Mode 8 Mode 4 Mode Unit 16 40 µs 0.8 0.4 0.2 0.1 30 2.0 1.0 0.5 0.25 60 120 80 MHz MHz MHz MHz % ns ns 16 28 µs R = 56kΩ ± 5% C = 100pF ± 10% ns 400 INPUTS : IN 3 -IN 0 , G 3 -G 0 , L 7 -L 0 t SET UP t HOL D SI t SET UP t HOL D SO, SK Outputs tpd1, tpd 0 All Other Outputs tpd1, tpd 0 Max. f I = 2MHz Instruction Cycle Time CKO as SYNC Input t SYNC OUTPUT PROPAGATION DELAY Min. 8.0 1.3 µs µs 2.0 1.0 µs µs 4.0 µs 5.6 µs Test Condition : C L = 50pF, R L = 20kΩ, V O UT = 1.5V 7/27 ETL9444/9445–ETL9344/9345 Figure 2 : Connection Diagrams. Pin Description L 7 -L 0 8 Bidirectional I/O Ports with TRI-STATE G 3 -G 0 4 Bidirectional I/O Ports D 3 -D 0 4 General Purpose Outputs IN 3 -IN 0 4 General Purpose Inputs (COP444L only) SI Serial Input (or counter input) SO Serial Output (or general purpose output) SK Logic-controlled Clock (or general purpose output) CKI System Oscillator Input CKO System Oscillator Output (or general purpose input, RAM power supply, or SYNC input) RESET System Reset Input V CC Power Supply GND Ground Figure 3 : Input/output Timing Diagrams (crystal divide-by-16 mode). 8/27 ETL9444/9445–ETL9344/9345 Figure 3a : Synchronization Timing. FUNCTIONAL DESCRIPTION A block diagram of the ETL9444 is given in figure 1. Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is used. When a bit is set, it is a logic ”1” (greater than 2 volts). When a bit is reset, it is a logic ”0” (less than 0.8 volts). All functional references to the ETL9444/L9445 also apply to the ETL9344/L9345. PROGRAM MEMORY Program Memory consists of a 2048 byte ROM. As can be seen by an examination of the ETL9444/L9445 instruction set, these words may be program instructions, program data or ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID, and LQID instructions, ROM must often be thought of as being organized into 32 pages of 64 words each. ROM addressing is accomplished by a 11-bit PC register. Its binary value selects one of the 2048 8-bit words contained in ROM. A new address is loaded into the PC register during each instruction cycle. Unless the instruction is a transfer of control instruction, the PC register is loaded with the next sequential 11-bit binary count value. Three levels of subroutine nesting are implemented by the 11-bit subroutine save registers, SA, SB, and SC ; providing a last-in, first-out (LIFO) hardware subroutine stack. ROM instruction words are fetched, decoded and executed by the Instruction Decode, Control and Skip Logic circuitry. DATA MEMORY Data memory consists of a 512-bit RAM, organized as 8 data registers of 16 4-bit digits. RAM addressing is implemented by a 7-bit B register whose upper 3 bits (Br) select 1 of 8 data registers and lower 4 bits (Bd) select 1 of 16 4-bit digits in the selected data register. While the 4-bit contents of the selected RAM digit (M) is usually loaded into or from, or exchanged with, the A register (accumulator), it may also be loaded into or from the Q latches or loaded from the L ports. RAM addressing may also be performed directly by the LDD and XAD instructions based upon the 7-bit contents of the operand field of these instructions. The Bd register also serves as a source register for 4-bit data sent directly to the D outputs. INTERNAL LOGIC The 4-bit A register (accumulator) is the source and destination register for most I/O, arithmetic, logic and data memory access operations. It can also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch data, to input 4 bits of the 8-bit L I/O port data and to perform data exchanges with the SIO register. A 4-bit adder performs the arithmetic and logic functions, storing its results in A. It also outputs a carry bit to the 1-bit C register, most often employed to indicate arithmetic overflow. The C register, in conjunction with the XAS instruction and the EN register, also serves to control the SK output. C can be outputted directly to SK or can enable SK to be a sync clock each instruction cycle time. (See XAS instruction and EN register description, below). Four general-purpose inputs, IN3-IN0, are provided. The D register provides 4 general-purpose outputs and is used as the destination register for the 4-bit contents of Bd. The D outputs can be directly connected to the digits of a multiplexed LED display. The G register contents are outputs to 4 generalpurpose bidirectional I/O ports. G I/O ports can be directly connected to the digits of a multiplexed LED display. The Q register is an internal, latched, 8-bit register, used to hold data loaded to or from M and A, as well as 8-bit data from ROM. Its contents are output to the L I/O ports when the L drivers are enabled under program control (See LEI instruction). 9/27 ETL9444/9445–ETL9344/9345 pulse (”1” to ”0”) ocurring on the SI input. Each pulse must be at least two instruction cycles wide. SK outputs the value of SKL. The SO output is equal to the value of EN3. With EN 0 reset, SIO is a serial shift register shifting left each instruction cycle time. The data present at SI goes into the least significant bit of SIO. SO can be enabled to output the most significant bit of SIO each cycle time. (See 4 below). The SK output becomes a logic-controlled clock. The 8 L drivers, when enabled, output the contents of latched Q data to the L I/O ports. Also, the contents of L may be read directly into A and M. L I/O ports can be directly connected to the segments of a multiplexed LED display (using the LED Direct Drive output configuration option) with Q data being outputted to the Sa - Sg and decimal point segments of the display. The SIO register functions as a 4-bit serial-in/serialout shift register or as a binary counter depending on the contents of the EN register. (See EN register description, below). Its contents can be exchanged with A, allowing it to input or output a continuous serial data stream, SIO may also be used to provide additional parallel I/O by connecting SO to external serial-in/parallel-out shift registers. The XAS instruction copies C into the SKL latch. In the counter mode, SK is the output of SKL ; in the shift register mode, SK outputs SKL ANDed with the clock. The EN register is an internal 4-bit register loaded under program control by the LEI instruction. The state of each bit of this register selects or deselects the particular feature associated with each bit of the EN register (EN3-EN0). 1. The least significant bit of the enable register, EN0, selects the SIO register as either a4-bit shift register or a 4-bit binary counter. With EN0 set, SIO is an asynchronous binary counter, decrementing its value by one upon each low-going 2. With EN1 set the IN1 input is enabled as an interrupt input. Immediately following an interrupt, EN1 is reset to disable further interrupts. 3. With EN2 set, the L drivers are enabled to output the data in Q to the L I/O ports. Resetting EN2 disables the L drivers, placing the L I/O ports in a high-impedance input state. 4. EN3, in conjunction with EN0, affects the SO output. With EN0 set (binary counter option selected) SO will output the value loaded into EN 3. With EN0 reset (serial shift register option selected), setting EN3 enables SO as the output of the SIO shift register, outputting serial shifted data each instruction time. Resetting EN3 with the serial shift register option selected disables SO as the shift register output ; data continues to be shifted through SIO and can be exchanged with A via an XAS instruction but SO remains reset to ”0”. The table below provides a summary of the modes associated with EN 3 and EN0. Enable Register Modes - Bits EN 3 and EN 0 EN 3 EN0 0 0 Shift Register SI O Input to Shift Register SI 0 1 0 Shift Register Input to Shift Register Serial Out 0 1 Binary Counter Input to Binary Counter 0 1 1 Binary Counter Input to Binary Counter 1 INTERRUPT The following features are associated with the IN1 interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts. a. The interrupt, once acknowledged as explained below, pushes the next sequential program counter address (PC + 1) onto the stack, pushing in turn the contents of the other subroutine-save registers to the next lower level (PC + 1 → SA → SB → SC). Any previous contents of SC are lost. The program counter is 10/27 SO SK If If If If If If If If SKL SKL SKL SKL SKL SKL SKL SKL = 1, = 0, = 1, = 0, = 1, = 0, = 1, = 0, SK = SK = SK = SK = SK = SK = SK = SK = Clock 0 Clock 0 1 0 1 0 set to hex address 0FF (the last word of page 3) and EN1 is reset. b. An interrupt will be acknowledged only after the following conditions are met : 1. EN1 has been set. 2. A low-going pulse (”1” to ”0”) at least two instruction cycles wide occurs on the IN1 input. 3. A currently executing instruction has been completed. ETL9444/9445–ETL9344/9345 4. All successive transfer of control instructions and successive LBIs have been completed (e.g., if the main program is executing a JP instruction which transfers program control to another JP instruction, the interrupt will not be acknowledged until the second JP instruction has been executed. c. Upon acknowledgement of an interrupt, the skip logic status is saved and later restored upon popping of the stack. For example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry) instruction which results in carry, the skip logic status is saved and program control is transferred to the interrupt servicing routine at hex address 0FF. At the end of the interrupt routine, a RET instruction is executed to ”pop” the stack and return program control to the instruction following the original ASC. At this time, the skip logic is enabled and skips this instruction because of the previous ASC carry. Subroutines and LQIDinstructions should not be nested within the interrupt service routine, since their popping the stack will enable any previously saved main program skips, interfering with the orderly execution of the interrupt routine. d. The first instruction of the interrupt routine at hex address 0FF must be a NOP. e. A LEI instruction can be put immediately before the RET to re-enable interrupts. INITIALIZATION The Reset Logic will initialize (clear) the device upon power-up if the power supply rise time is less than 1ms and greater than 1µs. If the power supply rise time is greater than 1ms, the user use provide an external RC network and diode to the RESET pin as shown below. If the RC network is not used, the RESET pin must be pulled up to VCC either by the internal load or by an external resistor (≥40kΩ) to VCC. The RESET pin is configured as a Schmitt trigger input. Initialization will occur whenever a logic ”0” is applied to the RESET input, provided it stays low for at least three instruction cycle times. Power-up Clear Circuit. Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, and G registers are cleared. The SK output is enabled as a SYNC output, providing a pulse each instruction cycle time. Data Memory (RAM) is not cleared upon initialization. The first instruction at address 0 must be a CLRA. OSCILLATOR There are three basic clock oscillator configurations available as shown by figure 4. a. Crystal Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time equals the crystal frequency divided by 32 (optional by 16 or 8). b. External Oscillator. CKI is an external clock input signal. The external frequency is divided by 32 (optional by 16 or 8) to give the instruction cycle time. CKO is now available to be used as the RAM power supply (VR), as a general purpose input, or as a SYNC input. c. RC Controlled Oscillator. CKI is configured as a single pin RC controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation frequency divided by 4. CKO is available as the RAM power supply (VR) or as a general purpose input. 11/27 ETL9444/9445–ETL9344/9345 Figure 4 : ETL9444/L9445 Oscillator. CRYSTAL OSCILLATOR Crystal RC CONTROLLED OSCILLATOR Component Values Valu e R 1 (Ω) R 2 (Ω) C 1 (pF) C 2 (pF) 455kHz 2.097MHz 4.7k 1k 1M 1M 220 30 220 6-36 R (kΩ) C (pF) Instruction Cycle Time (µ s) 51 82 100 56 19 ± 15% 19 ± 13% Note : 200kΩ ≥ R ≥ 25kΩ 360pF ≥ C ≥ 50pF CKO PIN OPTIONS In a crystal controlled oscillator system, CKO is used as an output to the crystal network. As an option CKO can be a SYNC input as described above. As another option CKO can be a general purpose input, read into bit 2 of A (accumulator) upon execution of an INIL instruction. As another option, CKO can be a RAM power supply pin (VR), allowing its connection to a standby/backup power supply to maintain the integrity of RAM data with minimum power drain when the main supply is inoperative or shut down to conserve power. Using either option is appropriate in applications where the ETL9444/L9445 system timing configuration does not require use of the CKO pin. b. Open-Drain - an enhancement-mode device to ground only, allowing external pull-up as required by the user’s application. Available on SO, SK, and all D and G outputs. I/O OPTIONS f. LED Direct Drive - an enhancement-mode device to ground and to VCC, meeting the typical current sourcing requirements of the segments of an LED display. The sourcing device is clamped to limit current flow. These devices may be turned off under program control (See Functional Description, EN Register), placing the outputs in a high-impedance state to provide required LED ETL9444/L9445 outputs have the following optional configurations, illustrated in figure 5. a. Standard - an enhancement mode device to ground in con junction with a depletion-mode device to VCC, compatible with LSTTL and CMOS input requirements. Available on SO, SK, and all D and G outputs. 12/27 c. Push-Pull - An enhancement-mode device to ground in conjunction with a depletion-mode device paralleled by an enhancement-mode device to VCC. This configuration has been provided to allow for fast rise and fall times when driving capacitive loads. Available on SO and SK outputs only. d. Standard L - same as a., but may be disabled. Available on L outputs only. e. Open Drain L - same as b., but may be disabled. Available on L outputs only. ETL9444/9445–ETL9344/9345 segment blanking for a multiplexed display. Available on L outputs only. g. TRI-STATE Push-Pull - an enhancementmode device to ground and VCC. These outputs are TRI-STATE outputs, allowing for connection of these outputs to a data bus shared by other bus drivers. Available on L outputs only. ETL9444, L9445 inputs have the following optional configurations : h. An on-chip depletion load device to VCC. i. A Hi-Z input which must be driven to a ”1” or ”0” by external components. The above input and output configurations share common enhancement-mode and depletion-mode devices. Specifically, all configurations use one or more of six devices (numbered 1-6, respectively). Minimum and maximum current (IOUT and VOUT curves are given in figure 6 for each of these devices to allow the designer to effectively use these I/O configurations in designing a system. The SO, SK outputs can be configured as shown in a., b., or c. The D and G outputs can be configured as shown in a. or b. Note that when inputting data to the G ports, the G outputs should be set to ”1”. The L outputs can be configured as in d., e., f. or g. An important point to remember if using configuration d. or f. with the L drivers is that even when the L drivers are disabled, the depletion load device will source a small amount of current (see figure 6, device 2) ; however, when the L-lines are used as inputs, the disabled depletion device can not be relied on to source sufficient current to pull an input to logic ”1”. RAM KEEP-ALIVE OPTION Selecting CKO as the RAM power supply (VR) allows the user to shut off the chip power supply (VCC) and maintain data in the RAM. To insure that RAM data integrity is maintained, the following conditions must be met : 1. RESET must go low before VCC goes low during power off ; VCC must go high before RESET goes high on power-up. 2. VR must be within the operating range of the chip, and equal to VCC ± 1V during normal operation. 3. VR must be ≥ 3.3V with VCC off. ETL9445 If the ETL9444 ls bonded as a 24-pin device, it becomes the ETL9445, illustrated in figure 2, ETL9444 Connection Diagrams. Note that the ETL9445 does not contain the four general purpose IN inputs (IN3IN0). Use of this option precludes, of course, use of the IN options and the interrupt feature, which uses IN1. All other options are available for the ETL9445. 13/27 ETL9444/9445–ETL9344/9345 Figure 5 : Output Configurations. 14/27 ETL9444/9445–ETL9344/9345 Figure 6 : ETL9444/L9445 Input/output Characteristics. 15/27 ETL9444/9445–ETL9344/9345 Figure 6a : ETL9444/L9445 Input/output Characteristics. 16/27 ETL9444/9445–ETL9344/9345 Figure 6b : ETL9344/L9345 Input/output Characteristics. 17/27 ETL9444/9445–ETL9344/9345 ETL9444/L9445, ETL9344/L9345 INSTRUCTION SET Table 1 is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table. Table 2 provides the mnemonic, operand, machine code, data flow, skip conditions, and description associated with each instruction in the ETL9444/L9445 instruction set. Table 1 : ETL9444/9445 ETL9344/9345 Instruction Set Table Symbols. INTERNAL ARCHITECTURE SYMBOLS INSTRUCTION OPERAND SYMBOLS Symbol Definition Symbol Definition A B Br Bd C D EN G IL 4-bit Accumulator 7-bit RAM Address Register Upper 3 Bits of B (register address) Lower 4 Bits of B (digit address) 1-bit Carry Register 4-bit Data Output Port 4-bit Enable Register 4-bit Register to Latch Data for G I/O Port Two 1-bit latches associated with the IN 3 or IN 0 inputs. 4-bit Input Port 8-bit TRI-STATE I/O Port 4-bit contents of RAM memory pointed to by B register. 11-bit ROM Address Register (program counter) 8-bit Register to Latch Data for L I/O Port 11-bit Subroutine Save Register A 11-bit Subroutine Save Register B 11-bit Subroutine Save Register C 4-bit Shift Register and Counter Logic-controlled Clock Output d 4-bit Operand Field, 0-15 Binary (RAM digit select) 3-bit Operand Field, 0-7 Binary (RAM register select) 11-bit Operand Field, 0-2047 Binary (ROM address) 4-bit Operand Field, 0-15 Binary (immediate data) Contents of RAM location addressed by s. Contents of ROM location addressed by t. IN L M PC Q SA SB SC SIO SK 18/27 r a y RAM(s) ROM(t) OPERATIONAL SYMBOLS Symbol + ➞ ↔ = A ⊕ : Definition Plus Minus Replaces Is exchanged with. Is equal to. The one’s complement of A. Exclusive-OR Range of Values ETL9444/9445–ETL9344/9345 Table 2 : ETL9444/L9445 Instruction Set. ARITHMETIC INSTRUCTIONS Mnem Operand Hex Code Machine Language Code (binary) Data Flow Skip Conditions Description ASC 30 |_______________ 0 0 1 1 | 0 0 0 0 | A + C + RAM(B) → A Carry → C Carry Add with Carry Skip on Carry ADD 31 |_______________ 0 0 1 1 | 0 0 0 1 | A + RAM(B) → A None Add RAM to A ADT 4A |_______________ 0 1 0 0 | 1 0 1 0 | A + 10 1 0 → A None Add Ten to A 5- |_______________ 0101| y | A+y→A Carry Add Immediate Skip on Carry (y ≠ 0) CASC 10 |_______________ 0 0 0 1 | 0 0 0 0 | A + RAM(B) + C → A Carry → C Carry Complement and Add with Carry, Skip on Carry CLRA 00 |_______________ 0000|0000| 0→A None Clear A COMP 40 |_______________ 0100|0000| A→A None Ones Complement of A to A AISC y NOP 44 |_______________ 0 1 0 0 | 0 1 0 0 | None None No Operation RC 32 |_______________ 0 0 1 1 | 0 0 1 0 | ”0” → C None Reset C SC 22 |_______________ 0 0 1 0 | 0 0 1 0 | ”1” → C None Set C XOR 02 |_______________ 0 0 0 0 | 0 0 1 0 | A ⊕ RAM(B) → A None Exclusive-OR Ram with A TRANSFER OF CONTROL INSTRUCTIONS Hex Mnem Operand Code JID Machine Language Code (binary) Data Flow Skip Conditions Description FF |_________________ 1 1 1 1 | 1 1 1 1 | ROM (PC 1 0 : 8 A, M) → PC 7 : 0 None Jump Indirect (note 3) 6– | 0 1 1 0 | 0 | a 1 0 : 8 | A → PC _________________ | a7:0 | _________________ None Jump JMP a JP a |1| a6 :0 | A → PC 6 : 0 _________________ (pages 2, 3 only) or |11 | a5 :0 | A → PC 5 : 0 _________________ (all other pages) None Jump within Page (note 4) JSRP a |10| a5 :0 | PC + 1 → SA → SB → SC _________________ 00010 → PC 1 0 :6 a → PC 5 :0 None Jump to Subroutine Page (note 5) JSR a 6– | 0 1 1 0 | 1 | a 1 0 : 8 | PC + 1 → SA → SB → SC _________________ | a7:0 | a → PC _________________ None Jump to Subroutine RET 48 | 0 1 0 0 | 1 0 0 0 | SC → SB → SA → PC _________________ None Return from Subroutine RETSK 49 | 0 1 0 0 | 1 0 0 1 | SC → SB → SA → PC _________________ Always Skip on Return Return from Subroutine then Skip 19/27 ETL9444/9445–ETL9344/9345 MEMORY REFERENCE INSTRUCTIONS Hex Mnem Operand Code Machine Language Code (binary) Data Flow Skip Conditions Description CAMQ 33 3C |_______________ 0 0 1 1 | 0 0 1 1 | A → Q7 :4 |_______________ 0 0 1 1 | 1 1 0 0 | RAM (B) → Q 3 : 0 None Copy A, RAM to Q CQMA 33 2C |_______________ 0 0 1 1 | 0 0 1 1 | Q 7 : 4 → RAM(B) |_______________ 0 0 1 0 | 1 1 0 0 | Q3 :0 → A None Copy Q to RAM A None Load RAM into A, Exclusive-OR Br with r None Load A with RAM pointed to directly by r.d. RAM(B) → A Br ⊕ r → Br LD r –5 |_______________ 0 0|r|0101| (r = 0:3) LDD r.d 23 |_______________ 0 0 1 0 | 0 0 1 1 | RAM(r.d) → A |0 | r | d | _______________ BF |_______________ 1 0 1 1 | 1 1 1 1 | ROM (PC 1 0 : 8A.M) → Q None SB → SC LQID Load Q Indirect (note 3) RMB 0 1 2 3 4C 45 42 43 |_______________ 0100|1100| |_______________ 0100|0101| |_______________ 0100|0010| |_______________ 0100|0011| 0 0 0 0 → → → → RAM RAM RAM RAM (B) 0 (B) 1 (B) 2 (B) 3 None Reset RAM Bit SMB 0 1 2 3 4D 47 46 4B |_______________ 0100|1101| |_______________ 0100|1101| |_______________ 0100|0110| |_______________ 0100|1011| 1 1 1 1 → → → → RAM RAM RAM RAM (B) 0 (B) 1 (B) 2 (B) 3 None Set RAM Bit STII y 7– |_______________ 0111| y | y → RAM (B) Bd + 1 → Bd None Store Memory Immediate and Increment Bd X r –6 |_______________ 0 0 | r | 0 1 1 0 | RAM (B) ↔ A Br ⊕ r → Br (r = 0:3) None Exchange RAM with A, Exclusive-OR Br with r XAD r.d 23 |_______________ 0 0 1 0 | 0 0 1 1 | RAM (r.d) ↔ A |_______________ 1| r | d | None Exchange A with RAM pointed to directly by r.d. XDS r –7 |_______________ 0 0 | r | 0 1 1 1 | RAM (B) ↔ A Bd – 1 → Bd (r = 0:3) Br ⊕ r → Br Bd Exchange RAM with A and Decrements Decrement Bd, Past 0 Exclusive-OR Br with r XIS r –4 |_______________ 0 0 | r | 0 1 0 0 | RAM (B) ↔ A Bd + 1 → Bd (r = 0:3) Br ⊕ r → Br Bd Increments Past 15 20/27 Exchange RAM with A and Increment Bd, Exclusive-OR Br with r ETL9444/9445–ETL9344/9345 REGISTER REFERENCE INSTRUCTIONS Hex Mnem Operand Code Machine Language Code (binary) Data Flow Skip Conditions Description CAB 50 |_______________ 0 1 0 1 | 0 0 0 0 | A → Bd None Copy A to Bd CBA 4E |_______________ 0 1 0 0 | 1 1 1 0 | Bd → A None Copy Bd to A |_______________ 0 0 | r | (d-1) | r.d → B (r = 0:3) (d = 0.9:15) or |_______________ 0011|0011| |_______________ 1 | r | d | (any r, any d) Skip until not a LBI 33 6– |_______________ 0 0 1 1 | 0 0 0 1 | y → EN |_______________ 0110| y | None Load EN Immediate (note 7) 12 |_______________ 0 0 0 1 | 0 0 1 0 | A → Br (0 → A 3 ) None Exchange A with Br LBI r.d 33 LEI y XABR Load B Immediate with r.d (note 6) TEST INSTRUCTIONS Hex Mnem Operand Code Machine Language Code (binary) Data Flow Skip Conditions Description SKC 20 |_______________ 0010|0000| C = ”1” SKE 21 |_______________ 0010|0001| A = RAM(B) Skip if A Equals RAM SKGZ 33 21 |_______________ 0011|0011| |_______________ 0010|0001| G 3:0 = 0 0 1 2 3 33 01 11 03 13 |_______________ 0011|0011| |_______________ 0000|0001| |_______________ 0001|0001| |_______________ 0000|0011| |_______________ 0001|0011| 0 1 2 3 01 11 03 13 |_______________ 0000|0001| |_______________ 0001|0001| |_______________ 0000|0011| |_______________ 0001|0011| RAM(B) 0 = 0 RAM(B) 1 = 0 RAM(B) 2 = 0 RAM(B) 3 = 0 Skip if RAM bit is zero. 41 |_______________ 0100|0001| A time-base counter carry has occured since last test. Skip on Timer (note 3) SKGBZ SKMBZ SKT 1st Byte 2nd Byte Skip if C is true. Skip if G is zero (all 4 bits). Skip if G Bit is zero. G0 G1 G2 G3 = = = = 0 0 0 0 21/27 ETL9444/9445–ETL9344/9345 INPUT/OUTPUT INSTRUCTIONS Hex Mnem Operand Code Machine Language Code (binary) Data Flow Skip Conditions Description ING 33 2A |_______________ 0011|0011| G→A |_______________ 0010|1010| None Input G Ports to A ININ 33 28 |_______________ 0 0 1 1 | 0 0 1 1 | IN → A |_______________ 0010|1000| None Input IN Inputs to A (note 2) INIL 33 29 |_______________ 0 0 1 1 | 0 0 1 1 | IL 3 , CKO, ”0”, IL 0 → A |_______________ 0010|1001| None Input IL Latches to A (note 3) INL 33 2E |_______________ 0 0 1 1 | 0 0 1 1 | L 7 : 4 → RAM(B) |_______________ 0 0 1 0 | 1 1 1 0 | L3: 0 → A None Input L Ports to RAM, A OBD 33 3E |_______________ 0 0 1 1 | 0 0 1 1 | Bd → D |_______________ 0011|1110| None Output Bd to D Outputs 33 5– |_______________ 0011|0011| y→G |_______________ 0101| y | None Output to G Ports Immediate OMG 33 3A |_______________ 0 0 1 1 | 0 0 1 1 | RAM(B) → G |_______________ 0011|1010| None Output RAM to G Ports XAS 4F |_______________ 0 1 0 0 | 1 1 1 1 | A ↔ SIO, C → SKL None Exchange A with SIO (note 3) OGI y Notes : 1.All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where 0 signifies the least significant bit (low-order, right-most bit). For example, A 3 indicates the most significant (left-most) bit of the 4-bit A register. 2.The ININ instruction is not available on the 24-pin ETL9445 or ETL9345 since these devices do not contain the IN inputs. 3.For additional information on the operation of the XAS, JID, LQUID, INIL and SKT instructions, see below. 4.The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page. 5.A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3, JSRP may not jump to the last word in page 2. 6.LBI is a single-byte instruction if d = 0, 9, 10, 11, 12, 13, 14 or 15. The machine code for the lower 4 bits equals the binary value of the ”d” data minus 1, e.g., to load the lower four bits of B (Bd) with the value 9 (1001 2), the lower 4 bits of the LBI instruction equal 8 (10002). To load 0, the lower 4 bits of the LBI instruction should equal 15 (1111 2). 7.Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a ”1” or ”0” in each bit of EN corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register). The following information is provided to assist the user in understanding the operation of several unique instructions and to provide notes useful to programmers in writing ETL9444/L9445 programs. XAS INSTRUCTION XAS (Exchange A with SIO) exchanges the 4-bit contents of the accumulator with the 4-bit contents of the SIO register. The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the value of the EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register, above). If SIO is selected as a shift register, an XAS instruction must be performed once every 4 instruction cycles to effect a continuous data stream. 22/27 JID INSTRUCTION JID (Jump Indirect) is an indirect addressing instruction, transferring program control to a new ROM location pointed to indirectly by A and M. It loads the lower 8 bits of the ROM address register PC with the contents of ROM addressed by the 11-bit word, PC10:8 A, M. PC10, PC9 and PC8 are not affected by this instruction. Note that JID requires 2 instruction cycles to execute. INIL INSTRUCTION INIL (Input IL Latches to A) inputs 2 latches, IL3 and IL0 (see figure 7) and CKO into A. The IL 3 and IL0 latches are set if a low-going pulse (”1” to ”0”) has ETL9444/9445–ETL9344/9345 occurred on the IN3 and IN0 inputs since the last INIL instruction, provided the input pulse stays low for at least two instruction times. Execution of an INIL inputs IL3 and IL0 into A3 and A0 respectively, and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and IN0 lines. If CKO is mask programmed as a general purpose input, an INIL will input the state of CKO into A2. If CKO has not been so programmed, a ”1” will be placed in A2. A ”0” is always placed in A1 upon the execution of an INIL. The general purpose inputs IN3-IN0 are input to A upon execution of an ININ instruction. (see table 2, ININ instruction). INIL is useful in recognizing pulses of short duration or pulses which occur too often to be read conveniently by an ININ instruction. Note : IL latches are not cleared on reset : IL3 and IL0 not input on ETL9444/L9445. LQID INSTRUCTION LQID (Load Q Indirect) loads the 8-bit Q register with the contents of ROM pointed to by the 11-bit word PC10, PC9, PC8, A, M. LQID can be used for table lookup or code conversion such as BCD to sevensegment. The LQID instruction ”pushes” the stack (PC + 1 → SA → SB → SC) and replaces the least significant 8 bits of PC as follows : A – PC7:4, RAM (B) → PC3:0, leaving PC10, PC9 and PC8 unchanged. The ROM data pointed to by the new address is fetched and loaded into the Q latches. Next, the stack is ”popped” (SC → SB → SA → PC), restoring the saved value of PC to continue sequential program execution. Since LQID pushes SB → SC, the previous contents of SC are lost. Also, when LQID pops the stack, the previously pushed contents of SB are left in SC. The net result is that the contents of SB are placed in SC (SB → SC). Note that LQID takes two instruction cycle times to execute. Figure 7 : INIL Hardware Implementation. SKT INSTRUCTION The SKT (Skip On Timer) instruction tests the state of an internal 10-bit time-base counter. This counter divides the instruction cycle clock, frequency by 1024 and provides a latched indication of counter overflow. The SKT instruction tests this latch, executing the next program instruction if the latch is not set. If the latch has been set since the previous test, the next program instruction is skipped and the latch is reset. The features associated with this instruction, therefore, allow the ETL9344/L9345 to generate its own time-base for real-time processing rather than relying on an external input signal. For example, using a 2.097MHz crystal as the timebase to the clock generator, the instruction cycle clock frequency will be 65kHz (crystal frequency ÷ 32) and the binary counter output pulse frequency willbe 64Hz. For time-of-day or similar real-time processing, the SKT instruction can call a routine which increments a ”seconds” counter every 64 ticks. INSTRUCTION SET NOTES a. The first word of a ETL9444/L9445 program (ROM address 0) must be a CLRA (Clear A) instruction. b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of the skipped instruction. Thus all program paths except JID and LQID take the same number of cycle times whether instructions are skipped or executed. JID and LQID instructions take 2 cycles if executed and 1 cycle if skipped. c. The ROM is organized into 32 pages of 64 words each. The Program Counter is an 11-bit binary counter, and will count through page boundaries. If a JP, JSRP, JID or LQID instruction is located in the last word of a page, the instruction operates as if it were in the next page. For example : a JP located in the last work of a page will jump to a location in the next page. Also, a LQID or JID located in the last word of page 3, 7, 11, 15, 19, 23 or 27 will access data in the next group of four pages. 23/27 ETL9444/9445–ETL9344/9345 OPTION LIST The ETL9444/L9445 mask programmable options are assigned numbers which correspond with the ETL9444 pins. The following is a list of ETL9444 options. When specifying ETL9445 chip, Options 9, 10, 19, and 20 must all be set to zero. The options are programmed at the same time as the ROM pattern to provide the user with the hardware flexibility to interface to various I/O components using little or no external circuitry. Option 1 = 0 : Ground Pin - no options available Option 2 : CKO Output = 0 : clock generator output to crystal/resonator (0 not allowable value if option 3 = 3) = 1 : pin is RAM power supply (VR) input = 2 : general purpose input. load device to VCC = 3 : general purpose input, Hi-Z Option 3 : CKI Input = 0 : oscillator input divided by 32 (2MHz max.) = 1 : oscillator input divided by 16 (1MHz max.) = 2 : oscillator input divided by 8 (500kHz max.) = 3 : single-pin RC controlled oscillator divided by 4 = 4 : oscillator input divided by 4 (Schmitt) Option 4 : RESET Input = 0 : load device to VCC = 1 : Hi-Z input Driver Option 5 : L7 = 0 : Standard output = 1 : Open-drain output = 2 : High current LED direct segment drive output = 3 : High current TRI-STATE push-pull output = 4 : Low-current LED direct segment drive output = 5 : Low-current TRI-STATE push-pull output Option 6 : L6 Driver same as Option 5 Option 7 : L5 Driver same as Option 5 Option 8 : L4 Driver same as Option 5 Option 9 : IN1 Input = 0 : load device to VCC = 1 : Hi-Z input Option 10 : IN2 Input same as Option 9 24/27 Option 11 : VCC pin = 0 : 4.5V to 6.3V operation = 1 : 4.5V to 9.5V operation Option 12 : L3 Driver same as Option 5 Option 14 : L2 Driver same as Option 5 Option 14 : L1 Driver same as Option 5 Option 15 : L0 Driver same as Option 5 Option 16 : SI Input same as Option 9 Option 17 : SO Driver = 0 : standard output = 1 : open-drain output = 2 : push-pull output Option 18 : SK Driver same as Option 17 Option 19 : IN0 Input same as Option 9 Option 20 : IN3 Input same as Option 9 Option 21 : G0 I/O Port = 0 : very-high current standard output = 1 : very-high current open-drain output = 2 : high current standard output = 3 : high current open-drain output = 4 : standard LSTTL output (fanout = 1) = 5 : open-drain LSTTL output (fanout = 1) Option 22 : G1 I/O Port same as Option 21 Option 23 : G2 I/O Port same as Option 21 Option 24 : G3 I/O Port same as Option 21 Option 25 : D3 Output same as Option 21 Option 26 : D2 Output same as Option 21 Option 27 : D1 Output same as Option 21 Option 28 : D0 Output same as Option 21 Option 29 : L Input Levels = 0 : standard TTL input levels (”0” = 0.8V, ”1” = 2.0V) ETL9444/9445–ETL9344/9345 = 1 : higher voltage input levels (”0” = 1.2V, ”1” = 3.6V) Option 30 : IN Input Levels same as Option 29 Option 31 : G Input Levels same as Option 29 Option 32 : SI Input Levels same as Option 29 Option 33 : RESET Input = 0 : Schmitt trigger input TEST MODE (Non-Standard Operation) The SO output has been configured to provide for standard test procedures for the custom-programmed ETL9444. With SO forced to logic ”1”, two test modes are provided, depending upon the value of SI : a. RAM and Internal Logic Test Mode (SI = 1) b. ROM Test Mode (SI = 0) These special test modes should not be employed by the user ; they are intended for manufacturing test only. APPLICATION EXAMPLE : ETL9444 General Controller Figure 8 shows and interconnect diagram for a ETL9444 used as a general controller. Operation of the system is as follows : 1. The L7-L0 outputs are configured as LED Direct Drive outputs, allowing direct connection to the segments of the display. = 1 : standard TTL input levels = 2 : higher voltage input levels Option 34 : CKO Input Levels (CKO = input Option 2 = 2.3) same as Option 29 Option 35 COP Bonding = 0 : ETL9444 (28-pin device) = 1 : ETL9445 (24-pin device) = 2 : both 28 and 24 pin versions 2. The D 3-D0 outputs drive the digits of the multiplexed display directly and scan the columns of the 4 x 4 keyboard matrix. 3. The IN3-IN0 inputs are used to input the 4 rows of the keyboard matrix. Reading the IN lines in conjunction with the current value of the D outputs allows detection, debouncing, and decoding of any one of the 16 keyswitches. 4. CKI is configured as a single-pin oscillator input allowing system timing to be controlled by a single-pin RC network. CKO is therefore available for use as a general-purpose input. 5. SI is selected as the input to a binary counter input. With SIO used as a binary counter, SO and SK can be used as general purpose outputs. 6. The 4 bidirectional G I/O ports (G 3-G-0) are available for use as required by the user’s application. 7. Normal reset operation is selected. Figure 8 : ETL9444 Keyboard/display Interface. 25/27 ETL9444/9445–ETL9344/9345 PHYSICAL DIMENSIONS 28–PINS – PLASTIC PACKAGE 24–PINS – PLASTIC PACKAGE 26/27 ETL9444/9445–ETL9344/9345 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All rights reserved. 2 Purchase of I C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I 2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I 2C Standard Specification as defined by Philips. SGS-THOMSON Microelectronics Group of Companies Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 27/27