HCC/HCF4046B MICROPOWER PHASE-LOCKED LOOP . . . . . .. . . .. .. QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE VERY LOW POWER CONSUMPTION : 100µW (TYP.) AT VCO fo = 10kHz, VDD = 5V OPERATING FREQUENCY RANGE : UP TO 1.4MHz (TYP.) AT VDD = 10V LOW FREQUENCY DRIFT : 0.06%/°C (typ.) AT VDD = 10V CHOICE OF TWO PHASE COMPARATORS : 1) EXCLUSIVE - OR NETWORK 2) EDGE-CONTROLLED MEMORY NETWORK WITH PHASE-PULSE OUTPUT FOR LOCK INDICATION HIGH VCO LINEARITY : 1% (TYP.) VCO INHIBIT CONTROL FOR ON-OFF KEYING AND ULTRA-LOW STANDBY POWER CONSUMPTION SOURCE-FOLLOWER OUTPUT OF VCO CONTROL INPUT (demod. output) ZENER DIODE TO ASSIST SUPPLY REGULATION 5V, 10V AND 15V PARAMETRIC RATING INPUT CURRENT OF 100nA AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD N°. 13A, ”STANDARD SPECIFICATIONS FOR DESCRIPTION OF ”B” SERIES CMOS DEVICES” EY (Plastic Package) F (Ceramic Package) C1 (Chip Carrier) ORDER CODES : HCC4046BF HCF4046BEY HCF4043BC1 PIN CONNECTIONS DESCRIPTION The HCC4046B (extended temperature range) and HCF4046B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package. The HCC/HCF4046B COS/MOS Micropower PhaseLocked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2V zener diode is provided for supply regulation if necessary. June 1989 1/13 HCC/HCF4046B VCO Section The VCO requires one external capacitor C1 and one or two external resistors (R1 or R1 and R2). Resistor R1 and capacitor C1 determine the frequency range of the VCO and resistor R2 enables the VCO to have a frequency offset if required. The high input impedance (1012Ω ) of the VCO simplifiers the design of low-pass filters by permitting the designer a wide choice of resistor-to-capacitor ratios. In order not to load the low-pass filter, a source-follower output of the VCO input voltage is provided at terminal 10 (DEMODULATED OUTPUT). If this terminal is used, a load resistor (RS) of 10 kΩ or more should be connected from this terminal to VSS. If unused this terminal should be left open. The VCO can be connected either directly or through frequency dividers to the comparator input of the phase comparators. A full COS/MOSlogic swing is available at the output of the VCO and allows direct coupling to COS/MOS frequency dividers such as the HCC/HCF4024B, HCC/HCF4018B, HCC/HCF4020B, HCC/HCF4022B, HCC/HCF4029B,and HBC/HBF4059A. One or more HCC/HCF4018B (Presettable Divide-by-N Counter) or HCC/HCF4029B (Presettable Up/Down Counter), or HBC/HBF4059A (Programmable Divide-by-”N” Counter), together with the HCC/HCF4046B (Phase-Locked Loop) can be used to build a micropower low-frequency synthesizer. A logic 0 on the INHIBIT input ”enables” the VCO and the source follower, while a logic 1 ”turns off” both to minimize stand-by power consumption. Phase Comparators The phase-comparator signal input (terminal 14) can be direct-coupled provided the signal swing is within COS/MOS logic levels [logic ”0” ≤ 30 % (VDD – VSS ), logic ”1” ≥ 70 % (VDD - VSS)]. For smaller swings the signal must be capacitively coupled to the self-biasing amplifier at the signal input. Phase comparator I is an exclusive-OR network ; it operates analagously to an over-driven balanced mixer. To maximize the lock range, the signal-and comparator-input frequencies must have a 50% duty cycle. With no signal or noise on the signal input, this phase comparator has an average output voltage equal to VDD/2. The low-pass filter connected to the output of phase comparator I supplies the averaged voltage to the VCO input, and causes the VCO to oscillate at the center frequency (fo). The frequency range of input signals on which the PLL will lock if it was initially out of lock is defined as the frequency capture range (2 fc). The frequency range of input signals on which the loop will stay locked if it was initially in lock is defined as the frequency lock range (2 fL). The capture range is ≤ the 2/13 lock range. With phase comparator I the range of frequencies over which the PLL can acquire lock (capture range) is dependent on the low-pass-filter characteristics, and can be made as large as the lock range. Phase-comparator I enables a PLL system to remain in lock in spite of high amounts of noise in the input signal. One characteristic of this type of phase comparator is that it may lock onto input frequencies that are close to harmonics of the VCO center-frequency. A second characteristic is that the phase angle between the signal and the comparator input varies between 0° and 180°, and is 90° at the center frequency. Fig. (a) shows the typical, triangular, phase-to-output response characteristic of phase-comparator I. Typical waveforms for a COS/MOS phase-locked-loop employing phase comparator I in locked condition of fo is shown in fig. (b). Phase-comparator II is an edge-controlled digital memory network. It consists of four flip-flop stages, control gating, and a three-stage output-circuit comprising p- and n-type drivers having a common output node. When the p-MOS or n-MOS drivers are ON they pull the output up to VDD or down to VSS, respectively. This type of phase comparator acts only on the positive edges of the signal and comparator inputs. The duty cycles of the signal and comparator inputs are not important since positive transitions control the PLL system utilizing this type of comparator. If the signal-input frequency is higher than the comparator-input frequency, the p-type output driver is maintained ON most of the time, and both the n- and p-drivers OFF (3 state) the remainder of the time. If the signal-input frequency is lower than the comparator-input frequency, the n-type output driver is maintained ON most of the time, and both the n- and p-drivers OFF (3 state) the remainder of the time. If the signal and comparator-input frequencies are the same, but the signal input lags the comparator input in phase, the n-type output driver is maintained ON for a time corresponding to the phase difference. If the signal and comparatorinput frequencies are the same, but the comparator input lags the signal in phase, the p-type output driver is maintained ON for a time corresponding to the phase difference. Subsequently, the capacitor voltage of the low-pass filter connected to this phase comparator is adjusted until the signal and comparator inputs are equal in both phase and frequency. At this stable point both p- and n-type output drivers remain OFF and thus the phase comparator output becomes an open circuit and holds the voltage on the capacitor of the low-pass filter constant. Moreover the signal at the ”phase pulses” output is a high level which can be used for indicating a locked condition. Thus, for phase comparator II, no phase difference exists between signal and comparator HCC/HCF4046B input over the full VCO frequency range. Moreover, the power dissipation due to the low-pass filter is reduced when this type of phase comparator is used because both the p- and n-type output drivers are OFF for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range, independent of the low-pass filter. With no signal present at the signal input, the VCO is adjusted to its lowest frequency for phase comparator II. Fig. (c) shows typical waveforms for a COS/MOS PLL employing phase comparator II in a locked condition. Figure a : Phase-Comparator I Characteristics at Low-Pass Filter Output. Figure b : Typical Waveforms for COS/MOS Phase Locked-Loop Employing Phase Comparator I in Locked Condition of fo. Figure C : Typical Waveforms For COS/MOS Phase-locked Loop Employing Phase Comparator II In Locked Condition. 3/13 HCC/HCF4046B FUNCTIONAL DIAGRAM VDD S-2299 VSS ALL INPUTS ARE PROTECTED BY COS/MOS PROTECTION NETWORK ABSOLUTE MAXIMUM RATINGS Symbol V DD * Parameter Supply Voltage : HC C Types H C F Types Value Unit – 0.5 to + 20 – 0.5 to + 18 V V Vi Input Voltage – 0.5 to V DD + 0.5 V II DC Input Current (any one input) ± 10 mA Total Power Dissipation (per package) Dissipation per Output Transistor for T o p = Full Package-temperature Range 200 mW 100 mW Pto t T op Operating Temperature : HCC Types H CF Types – 55 to + 125 – 40 to + 85 °C °C T stg Storage Temperature – 65 to + 150 °C Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability. * All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol V DD VI Top 4/13 Parameter Supply Voltage : HC C Types H C F Types Input Voltage Operating Temperature : H CC Types H C F Types Value Unit 3 to 18 3 to 15 V V 0 to V DD V – 55 to + 125 – 40 to + 85 °C °C HCC/HCF4046B STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions) Symbol Parameter V CO SECTION Output High V OH Voltage V OL Output Low Voltage I OH Output Drive Current HCC Types HCF Types I OL Output Sink Current HCC Types HCF Types I IH , I IL Input Leakage Current VI (V) Test Conditions Value VO |I O | V D D T L o w* 25 °C T Hi g h * (V) (µA) (V) Min. Max. Min. Typ. Max. Min. Max. 0/ 5 0/10 0/15 5/0 10/0 15/0 0/ 5 0/ 5 0/10 0/15 0/ 5 0/ 5 0/10 0/15 0/ 5 0/10 0/15 0/ 5 0/10 0/15 < < < < < < 2.5 4.6 9.5 13.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 0.4 0.5 1.5 HCC Types 0/18 Any Input HCF 0/15 Types PHASE COMPARATOR SECTION Total Device 0/ 5 I DD Current 0/10 Pin 14 = Open 0/15 Pin 5 = VDD 0/20 Pin 14 =VSS 0/ 5 or V DD HCC 0/10 Pin 5 = V DD Types 0/15 0/20 0/ 5 HCF 0/10 Types 0/15 Output 0/ 5 2.5 I OH Drive 4.6 HCC 0/ 5 Current Types 0/10 9.5 0/15 13.5 0/ 5 2.5 HCF 0/ 5 4.6 Types 0/10 9.5 0/15 13.5 1 1 1 1 1 1 5 10 15 5 10 15 5 5 10 15 5 5 10 15 5 10 15 5 10 15 4.95 9.95 14.95 4.95 9.95 14.95 5 10 15 0.05 0.05 0.05 – 2 – 0.64 – 1.6 – 4.2 – 1.53 – 0.52 – 1.3 – 3.6 0.64 1.6 4.2 0.52 1.3 3.6 4.95 9.95 14.95 0.05 0.05 0.05 – 1.6 – 0.51 – 1.3 – 3.4 – 1.36 – 0.44 – 1.1 – 3.0 0.51 1.3 3.4 0.44 1.1 3.0 – 3.2 – 1 – 2.6 – 6.8 – 3.2 – 1 – 2.6 – 6.8 1 2.6 6.8 1 2.6 6.8 0.05 0.05 0.05 – 1.15 – 0.36 – 0.9 – 2.4 – 1.1 – 0.36 – 0.9 – 2.4 0.36 0.9 2.4 0.36 0.9 2.4 ± 0.1 ± 10– 5 ± 0.1 ± 1 15 ± 0.3 ± 10– 5 ± 0.3 ± 1 5 10 15 20 5 10 15 20 5 10 15 5 5 10 15 5 5 10 15 0.1 0.5 1.5 4 5 10 20 100 20 40 80 – 2 – 0.64 – 1.6 – 4.2 – 1.53 – 0.52 – 1.3 – 3.6 – 1.6 – 0.51 – 1.3 – 3.4 – 1.36 – 0.44 – 1.1 – 3.0 0.1 0.5 1.5 4 5 10 20 100 20 40 80 0.1 0.5 1.5 4 150 300 600 3000 150 300 600 – 1.15 – 0.36 – 0.9 – 2.4 – 1.1 – 0.36 – 0.9 – 2.4 V mA 18 0.05 0.25 0.75 2 0.04 0.04 0.04 0.08 0.04 0.04 0.04 – 3.2 – 1 – 2.6 – 6.8 – 3.2 – 1 – 2.6 – 6.8 Unit µA mA µA mA * TLow = – 55°C for HCC device : – 40°C for HCF device. * THigh = + 125°C for HCC device : + 85°C for HCF device. The Noise Margin for both ”1” and ”0” level is : 1V min. with VDD = 5V, 2V min. with VDD = 10V, 2.5V min. with VDD = 15V. 5/13 HCC/HCF4046B STATIC ELECTRICAL CHARACTERISTICS (continued) Symbol I OL V IH V IL I IH , I IL I OUT CI Test Conditions Value T * 25 °C T Hi g h * V |I | V L o w V Parameter I O O DD (V) (V) (µA) (V) Min. Max. Min. Typ. Max. Min. Max. 0/ 5 0.4 5 0.64 0.51 1 0.36 Output HCC Sink 0/10 0.5 10 1.6 1.3 2.6 0.9 Types Current 0/15 1.5 15 4.2 3.4 6.8 2.4 0/ 5 0.4 5 0.52 0.44 1 0.36 HCF 0/10 0.5 10 1.3 1.1 2.6 0.9 Types 0/15 1.5 15 3.6 3.0 6.8 2.4 Input High 0.5/4.5 < 1 5 3.5 3.5 3.5 Voltage 1/9 <1 10 7 7 7 1.5/13.5 < 1 15 11 11 11 Input Low 4.5/0.5 < 1 5 1.5 1.5 1.5 Voltage 9/1 <1 10 3 3 3 13.5/1.5 < 1 15 4 4 4 Input HCC 0/18 18 ± 0.1 ± 10– 5 ± 0.1 ± 1 Leakage Types Any Input Current HCF (except. 15 ± 0.3 ± 10– 5 ± 0.3 ± 1 Types 0/15 pin 14) 3-state Leakage Current HCC Types 0/18 HCF Types 0/15 Input Capacitance 0/18 0/15 Any Input 18 ± 0.4 ± 10– 4 ± 0.4 ± 12 15 ± 1.0 ± 10 ± 7.5 5 –4 ± 1.0 7.5 * TLow = – 55°C for HCC device : – 40°C for HCF device. * THigh = + 125°C for HCC device : + 85°C for HCF device. The Noise Margin for both ”1” and ”0” level is : 1V min. with VDD = 5V, 2V min. with VDD = 10V, 2.5V min. with VDD = 15V. 6/13 Unit mA V V µA µA pF HCC/HCF4046B ELECTRICAL CARACTERISTICS (T amb = 25 o C) Symbol VCO SECTION Operating Power PD Dissipation fmax Test Conditions Parameter Maximum Frequency Linearity Typ. Max. 5 70 140 10 800 1600 15 3000 6000 R1 = 10 KΩ C1 = 50 pF R2 = ∞ VCOIN = VDD 5 10 0.3 0.6 0.6 1.2 15 0.8 1.6 5 10 0.5 1 0.8 1.4 15 1.4 2.4 n C1 = 50 pF VCOIN = VDD VCOIN=2.5V ± 0.3 R1=10 KΩ R1=100 KΩ VCOIN=5V ± 1 5 10 1.7 0.5 VCOIN=5V ± 2.5 R1=400 KΩ VCOIN=7.5V ± 1.5 R1=100 KΩ 10 15 4 0.5 ±5 R1=1 MΩ % 15 7 5 10 ±0.12 ±0.04 15 ±0.015 Temperature Frequency Stability (frequency offset) fmin ≠ 0 5 10 ±0.09 ±0.07 15 ±0.03 5, 10, 15 5 50 100 200 10 50 100 15 40 80 5, 10, 15 1.8 2.5 5 0.3 10 0.7 Output Duty Cycle VCO Output Transition Time RS > 10 KΩ RS=100 KΩ RS=300 KΩ VZ Zener Diode Voltage RS=500 KΩ IZ = 50 µA RZ Zener Dynamic Resistance IZ = 1 mA VCOIN=2.5±0.3V ±2.5 VCOIN=5 V ±5 VCOIN=7.5 V PHASE COMPARATOR SECTION R14 Pin 14 (signal in) Input Resistance A.C. Coupled Signal Input Voltage Sensitivity * (peak to paek) µW MHz Temperature Frequency Stability (no frequency offset) fmin = 0 Source Follower Output (demodulated Output): Offset Voltage VCOIN - VDEM Source Follower Output (demodulated Output): Linearity Unit Programmable with external components R1, R2 and C1 VCOIN=7.5V V CO tTHL tTLH Min. fo = 10 KHz R1 = 10 MΩ VDD R2 = ∞ V COIN = 2 R1 = 5 KΩ R2 = ∞ Center Frequency (fo) and Frequency Range fmax - fmin Value VDD (V) fin = 100 KHz sine wave 15 4.45 0.9 5.5 40 5 1 2 10 0.2 0.4 15 5 0.1 180 0.2 360 10 330 660 15 900 1800 %/ oC % ns V % 7.5 V Ω MΩ mV 7/13 HCC/HCF4046B ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions Value V D D (V) Min. Typ. Max. Unit PHASE COMPARATOR SECTION (cont’d) T PHL T PL H T PHZ T PL Z t r, tf Propagation Delay Time High to Low Level Pins 14 to 13 Propagation Delay Time Low to High, Level Propagation Delay Time 3-state High Level to High Impedance Pins 14 to 13 Low Level to High Impedance Input Rise or Fall Time Comparator Pin 3 Signal Pin 14 5 225 450 10 100 200 15 65 130 5 350 700 10 150 300 15 100 200 5 225 450 10 100 200 15 65 130 5 285 570 10 130 260 15 95 190 5 50 10 1 15 0.3 5 500 10 20 15 T T HL , T TL H Transition Time * For sine wave the frequency must be greater than 10KHZ for Phase Comparator II. 8/13 ns ns ns ns µs µs 2.5 5 100 200 10 50 100 15 40 80 ns HCC/HCF4046B DESIGN INFORMATION This information is a guide for approximating the values of external components for the HCC/HCF 4046B in a Phase-Locked-Loop system. The selected external components must be within the following ranges : 5kΩ ≤ R1, R2, RS ≤ 1MΩ CHARACTERISTICS C1 ≥ 100pF at VDD ≥ 5V C1 ≥ 50pF at VDD ≥ 10V USING PHASE COMPARATOR I VCO WITHOUT VCO WITH OFFSET R2 = ∞ OFFSET USING PHASE COMPARATOR II VCO WITHOUT VCO WITH OFFSET R2 = ∞ OFFSET VCO in PLL System will Adjust to centre frequency fo VCO in PLL System will Adjust to Lowest Operating Frequency fmin VCO Frequency For No Signal Input Frequency Lock Range, 2 fL 2 fL = full VCO frequency range 2 fL = fmax - fmin Frequency Capture Range, 2 fC fC = fL Loop Filter Component Selection Phase Angle Between Signal and Comparator Locks on Harmonics of Centre Frequency Signal Input Noise Rejection 90o at Centre Frequency (f o), approximating 0o and 180o at ends of lock range (2 fL) Always 0o in lock Yes No High Low * G.S. Mosckytz ”miniaturized RC filters using phase Lockedloop” BSTJ, may 1965 9/13 HCC/HCF4046B Plastic DIP16 (0.25) MECHANICAL DATA mm DIM. MIN. a1 0.51 B 0.77 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 10/13 HCC/HCF4046B Ceramic DIP16/1 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 20 0.787 B 7 0.276 D E 3.3 0.130 0.38 e3 0.015 17.78 0.700 F 2.29 2.79 0.090 0.110 G 0.4 0.55 0.016 0.022 H 1.17 1.52 0.046 0.060 L 0.22 0.31 0.009 0.012 M 0.51 1.27 0.020 0.050 N P Q 10.3 7.8 8.05 5.08 0.406 0.307 0.317 0.200 P053D 11/13 HCC/HCF4046B PLCC20 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 9.78 10.03 0.385 0.395 B 8.89 9.04 0.350 0.356 D 4.2 4.57 0.165 0.180 d1 2.54 0.100 d2 0.56 0.022 E 7.37 8.38 0.290 0.330 e 1.27 0.050 e3 5.08 0.200 F 0.38 0.015 G 0.101 0.004 M 1.27 0.050 M1 1.14 0.045 P027A 12/13 HCC/HCF4046B Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A 13/13