HCF4006B 18-STAGE STATIC SHIFT REGISTER ■ ■ ■ ■ ■ ■ ■ ■ ■ PERMANENT REGISTER STORAGE WITH CLOCK LINE "HIGH" OR "LOW" ... NO INFORMATION RECIRCULATION REQUIRED FULLY STATIC OPERATION SHIFTING RATES UP TO 12MHzat 10V (Typ.) STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION The HCF4006B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4006B is comprised of 4 separate "shift register" sections; two sections of four stages and two sections of five stages with an output tap at the fourth stage. Each section has an independent "single rail" data path. A common clock signal is DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF4006BEY HCF4006BM1 HCF4006M013TR used for all stages. Data is shifted to the next stage on negative going transitions of the clock. Through appropriate connections of inputs and outputs, multiple register sections of 4, 5, 8 and 9 stages or single register sections of 10, 12, 13, 14, 16, 17 and 18 can be implemented using one HCF4006B package. Longer shift register sections can be assembled by using more than one HCF4006B. To facilitate cascading stages when clock rise and fall times are slow, an optional output (D1+4’) that is delayed one-half clock-cycle, is provided (see truth table for output from pin 2) PIN CONNECTION September 2001 1/8 HCF4006B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 4, 5, 6 2 D1 to D4 D1+4’ 13, 11, 10, 8 Dn + 4 12, 9 Dn + 5 3 7 CLOCK VSS Data inputs Delayed Optional Output 4 stage shift register Output 5 stage shift register Output Clock Input 14 VDD Negative Supply Voltage Positive Supply Voltage TRUTH TABLE FOR SHIFT REGISTER STAGE FUNCTIONAL DIAGRAM D CLOCK* D+1 L L H H X NO CHANGE TRUTH TABLE FOR OUTPUT FROM PIN 2 D1 + 4 2/8 D1 + 4’ L L H H X NO CHANGE * : Level Change X : Don’t Care LOGIC DIAGRAM CLOCK* HCF4006B ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current PD Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C 3/8 HCF4006B DC SPECIFICATIONS Test Condition Symbol IL VOH VOL VIH VIL IOH IOL II CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Input Leakage Current Input Capacitance VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Value |IO| VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 Any Input Any Input 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25°C Min. Typ. Max. 0.04 0.04 0.04 0.08 5 10 20 100 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -3.2 -1 -2.6 -6.8 1 2.6 6.8 ±0.1 5 7.5 0.05 0.05 0.05 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 4/8 V V 1.5 3 4 ±1 µA V 3.5 7 11 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±10-5 Max. 150 300 600 3000 0.05 0.05 0.05 3.5 7 11 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 Max. Unit V mA mA ±1 µA pF HCF4006B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time tTLH tTHL Output Transition Time tW tr, tf tsetup fMAX Clock Pulse Width Clock Input Rise or Fall Time* Data Setup Time Maximum Clock Input Frequency VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Value (*) Min. Typ. 200 100 80 100 50 40 100 45 30 15 15 15 50 25 20 5 12 16 Unit Max. ns ns ns µs ns MHz (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) 5/8 HCF4006B Plastic DIP-14 MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 1.39 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L Z 3.3 1.27 0.130 2.54 0.050 0.100 P001A 6/8 HCF4006B SO-14 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8° (max.) PO13G 7/8 HCF4006B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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