HCC40105B HCF40105B FIFO REGISTER . .. . .. . .. .. INDEPENDENT ASYNCHRONOUS INPUTS AND OUTPUTS 3-STATE OUTPUTS EXPANDABLE IN EITHER DIRECTION STATUS INDICATORS ON INPUT AND OUTPUT RESET CAPABILITY STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT CURRENT OF 100nA AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD No 13A, ”STANDARD SPECIFICATIONS FOR DESCRIPTION OF ”B” SERIES CMOS DEVICES” DESCRIPTION The HCC40105B (extended temperature range) and HCF40105B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package. READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output. EY (Plastic Package) F (Ceramic Package) C1 (Chip Carrier) ORDER CODES : HCC40105BF HCF40105BEY HCF40105BC1 PIN CONNECTIONS The HCC/HCF40105B is a low-power first-in-first-out (FIFO) ”elastic” storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A ”1” signifies that the position’s data is filled and a ”0” denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the ”0” state and sees a ”1” in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to ”0”. The first and last control flip-flops have buffered outputs. Since all empty locations ”bubble” automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA-OUT June 1989 1/12 HCC/HCF40105B FUNCTIONAL DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V DD * Parameter Supply Voltage : HCC Types HC F Types Value Unit – 0.5 to + 20 – 0.5 to + 18 V V Vi Input Voltage – 0.5 to V DD + 0.5 V II DC Input Current (any one input) ± 10 mA Total Power Dissipation (per package) Dissipation per Output Transistor for T o p = Full Package-temperature Range 200 mW 100 mW Pto t T op Operating Temperature : H CC Types H C F Types – 55 to + 125 – 40 to + 85 °C °C T stg Storage Temperature – 65 to + 150 °C Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability. * All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol V DD VI Top 2/12 Parameter Supply Voltage : HC C Types H CF Types Input Voltage Operating Temperature : H CC Types H C F Types Value Unit 3 to 18 3 to 15 V V 0 to V DD V – 55 to + 125 – 40 to + 85 °C °C HCC/HCF40105B LOGIC DIAGRAM TIMING DIAGRAM 3/12 HCC/HCF40105B STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions) Symbol IL Parameter Quiescent Current HCC Types HCF Types V OH V OL V IH V IL I OH Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Output Drive Current HCC Types HCF Types I OL Output Sink Current HCC Types HCF Types I IH , I IL Input Leakage Current Test Conditions VO |I O | V D D T L o w* (V) (µA) (V) Min. Max. 0/ 5 5 5 0/10 10 10 0/15 15 20 0/20 20 100 0/ 5 5 20 0/10 10 40 0/15 15 80 0/ 5 <1 5 4.95 0/10 <1 10 9.95 0/15 <1 15 14.95 5/0 <1 5 0.05 10/0 <1 10 0.05 15/0 <1 15 0.05 0.5/4.5 < 1 5 3.5 1/9 <1 10 7 1.5/13.5 < 1 15 11 4.5/0.5 < 1 5 1.5 9/1 <1 10 3 13.5/1.5 < 1 15 4 0/ 5 2.5 5 – 2 0/ 5 4.6 5 – 0.64 0/10 9.5 10 – 1.6 0/15 13.5 15 – 4.2 0/ 5 2.5 5 – 1.53 0/ 5 4.6 5 – 0.52 0/10 9.5 10 – 1.3 0/15 13.5 15 – 3.6 0/ 5 0.4 5 0.64 0/10 0.5 10 1.6 0/15 1.5 15 4.2 0/ 5 0.4 5 0.52 0/10 0.5 10 1.3 0/15 1.5 15 3.6 VI (V) HCC Types 0/18 HCF 0/15 Types I O H,I O L ** 3-State HCC 0/18 Output Types Leakage HCF 0/15 Current Types Input Capacitance CI * * Value 25 °C Min. Typ. Max. 0.04 5 0.04 10 0.04 20 0.08 100 0.04 20 0.04 40 0.04 80 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 – 1.6 – 3.2 – 0.51 – 1 – 1.3 – 2.6 – 3.4 – 6.8 – 1.36 – 3.2 – 0.44 – 1 – 1.1 – 2.6 – 3.0 – 6.8 0.51 1 1.3 2.6 3.4 6.8 0.44 1 1.1 2.6 3.0 6.8 T Hi g h * Min. Max. 150 300 600 3000 150 300 600 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 – 1.15 – 0.36 – 0.9 – 2.4 – 1.1 – 0.36 – 0.9 – 2.4 0.36 0.9 2.4 0.36 0.9 2.4 18 ± 0.1 ±10 – 5 ± 0.1 ± 1 15 ± 0.3 ±10 – 5 ± 0.3 ± 1 0/18 18 ± 0.4 ±10 – 4 ± 0.4 ± 12 0/15 15 ± 1.0 ±10 – 4 ± 1.0 ± 7.5 5 7.5 TLo w = – 55°C for HCC device : – 40°C for HCF device. THigh = + 125°C for HCC device : + 85°C for HCF device. The Noise Margin for both ”1” and ”0” level is : 1V min. with VDD = 5V, 2V min. with VDD = 10V, 2.5 V min. with VDD = 15V. * * Forced output disable. 4/12 µA V V V V mA mA µA Any Input Any Input Unit µA pF HCC/HCF40105B DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25 °C, C L = 50 pF, R L = 200 kΩ, typical temperature coefficient for all V D D values is 0.3 %/°C, all input rise and fall time = 20 ns) Symbol t P HL t P HL Parameter Propagation Delay Time Shift-out or Reset to Data-out Ready Propagation Delay Time Shift-in to Data-in Ready t P ZH, t P ZL Propagation Delay Time 3-state Control to Data-out t P HZ , t P L Z Propagation Delay Time 3-State Control to Data-out tPLH Ripple-through Delay Input to Output t THL , t TL H Transition Time fI t WH t WL tr tf tf tse tup Shift-in or Shift-out Rate Shift-in Pulse Width Shift-out Pulse Width Shift-in or Shift-out Rise Time Shift-in Fall Time Shift-out Fall Time Data Setup Time Test Conditions Value V D D (V) Min. Typ. Max. 5 185 370 10 90 180 15 65 130 5 160 320 10 65 130 15 45 90 5 140 280 10 60 120 15 40 80 5 100 200 10 50 100 15 40 80 5 2 4 10 1 2 15 0.7 1.4 5 100 200 10 50 100 15 40 80 5 1.5 3 10 3 6 15 4 8 5 200 100 10 80 40 15 60 30 5 360 180 10 160 80 15 100 50 10 15 15 15 5 15 10 15 15 15 5 15 10 5 15 5 0 0 15 0 ns ns ns µs ns MHz ns 15 5 ns ns 5 10 Unit µs µs µs ns 5/12 HCC/HCF40105B DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Symbol t h o ld t WL t WL Parameter Data Hold Time Data–in Ready Pulse Width Data–out Ready Pulse Width Test Conditions Value V D D (V) Min. 5 350 175 10 150 75 15 120 60 Master Reset Pulse Width Max. 260 520 10 100 120 15 70 140 5 220 440 10 90 180 665 130 5 200 100 10 90 45 15 60 30 Unit ns 5 15 t WH Typ. Output Low (sink) Current Characteristics. Output High (source) Current Characteristics. Typical Transition Time vs. Load Capacitance. Typical Dynamic Power Dissipation vs. Frequency. 6/12 ns ns ns HCC/HCF40105B TEST CIRCUITS Quiescent Device Current. Input Voltage. Input Leakage Current. Dynamic Power Dissipation. TYPICAL APPLICATIONS EXPANSION, 4 BITS–WIDE–BY–16 N–BITS LONG. 7/12 HCC/HCF40105B EXPANSION, 8 BITS–WIDE–BY–16 N–BITS LONG. APPLICATIONS INFORMATION LOADING DATA Data can be entered whenever the DATA-IN READY (DIR) flag is high, by a low to high transition on the SHIFT-IN (SI) input. This input must go low momentarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily, until the data have been transferred tothe second location. The flag will remain low when all 16-word locations are filled with valid data, and further pulses on the SI input will be ignored until DIR goes high. UNLOADING DATA As soon as the first word has rippled to the output, DATA-OUT READY (DOR) goes high, and data can be removed by afalling edge on theSO input. This falling edge causes the DOR signal to go low while the word on the output is dumped and the next word moves to the output. As long as valid data are available in the FIFO, the DOR signal will go high again signifying that the next word is ready at the output. When the FIFO is empty, DOR will remain low, and any further commands will be ignored until a ”1” marker ripples down to the last control register, when DOR goes high. Unloading of data is inhibited while the 3state control input is high. The 3-state control signal should not be shifted from high to low (data outputs 8/12 turned on)while the SHIFT-OUT is at logic 0. This level change would cause the first word to be shifted out (unloaded) immediately and the data to be lost. CASCADING The HCC/HCF40105B can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than 4 bits, the DIR and the DOR outputs must be gated together with AND gates. Their outputs drive the SI and SO inputs in parallel, if expanding is done in both directions. 3-STATE OUTPUTS In order to facilitate data busing, 3-state outputs are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. MASTER RESET A high on the MASTER RESET (MR) sets all the control logic marker bits to ”0”. DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. HCC/HCF40105B Plastic DIP14 MECHANICAL DATA mm DIM. MIN. a1 0.51 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L Z 3.3 1.27 0.130 2.54 0.050 0.100 P001A 9/12 HCC/HCF40105B Ceramic DIP14/1 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 20 0.787 B 7.0 0.276 D E 3.3 0.130 0.38 e3 0.015 15.24 0.600 F 2.29 2.79 0.090 0.110 G 0.4 0.55 0.016 0.022 H 1.17 1.52 0.046 0.060 L 0.22 0.31 0.009 0.012 M 1.52 2.54 0.060 0.100 N P Q 10.3 7.8 8.05 5.08 0.406 0.307 0.317 0.200 P053C 10/12 HCC/HCF40105B PLCC20 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 9.78 10.03 0.385 0.395 B 8.89 9.04 0.350 0.356 D 4.2 4.57 0.165 0.180 d1 2.54 0.100 d2 0.56 0.022 E 7.37 8.38 0.290 0.330 e 1.27 0.050 e3 5.08 0.200 F 0.38 0.015 G 0.101 0.004 M 1.27 0.050 M1 1.14 0.045 P027A 11/12 HCC/HCF40105B Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A 12/12