STMICROELECTRONICS HCF4029BM1

HCC4029B
HCF4029B
PRESETTABLE UP/DOWN COUNTER
BINARY OR BCD DECADE
.
.
.
..
.
..
.
..
MEDIUM SPEED OPERATION - 8MHz (typ.) @
CL = 50pF AND VDD-VSS = 10V
MULTI-PACKAGE PARALLEL CLOCKING FOR
SYNCHRONOUS HIGH SPEED OUTPUT RESPONSE OR RIPPLE CLOCKING FOR SLOW
CLOCK INPUT RISE AND FALL TIMES
”PRESET ENABLE” AND INDIVIDUAL ”JAM”
INPUTS PROVIDED
BINARY OR DECADE UP/DOWN COUNTING
BCD OUTPUTS IN DECADE MODE
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD No. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Package)
M1
(Micro Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4029BF
HCF4029BM1
HCF4029BEY
HCF4029BC1
DESCRIPTION
The HCC4029B (extended temperature range) and
HCF4029B (intermediate temperature range) are
monolithic integrated circuit, available in 16-lead
dual in-line plastic or ceramic package and plastic
micro package. The HCC/HCF4029B consists of a
four-stage binary or BCD-decade up/down counter
with provisions for look-ahead carry in both counting
modes. The inputs consist of a single CLOCK,
CARRY-IN (CLOCK ENABLE), BINARY/DECADE,
UP/DOWN, PRESET ENABLE, and four individual
JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT
signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS
to preset the counter to any state asynchronously
with the clock. A low on each JAM line, when the
PRESET-ENABLE signal is high, resets the counter
to its zero count. The counter is advanced one count
at the positive transition of the clock when the
CARRY-IN and PRESET ENABLE signals, are low.
Advancement is inhibited when the CARRY-IN or
PRESET ENABLE signals are high. The CARRYOUT signal is normally high and goes low when the
September 1988
PIN CONNECTIONS
NC = No Internal Connection
1/13
HCC/HCF4029B
counter reaches its maximum count in the UP mode
or the minimum count in the DOWN mode provided
the CARRY-IN signal is low. The CARRY-IN signal
in the low state can thus be considered a CLOCK
ENABLE. The CARRY-IN terminal must be connected to VSS whennot in use. Binary counting is accomplished when the BINARY/DECADE input is
high ; the counter counts in the decade mode when
the BINARY/DECADE input is low. The counter
counts Up when to UP/DOWN INPUT is high, and
Down when the UP/DOWN INPUT is low. Multiple
packages can be connected in either a parallelclocking or a ripple-clocking arrangement as shown
in cascading counter packages. Parallel clocking
provides synchronous control and hence faster response from all counting outputs. Ripple-clocking
allows for longer clock input rise and fall times.
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATING
Symbol
VDD *
Vi
II
Ptot
Parameter
Supply Voltage: HCC Types
HCF Types
Input Voltage
DC Input Current (any one input)
Total Power Dissipation (per package)
Dissipation per Output Transistor
for Top = Full Package Temperature Range
Value
Unit
-0.5 to +20
-0.5 to +18
V
V
-0.5 to VDD + 0.5
± 10
V
mA
200
mW
100
mW
Top
Operating Temperature: HCC Types
HCF Types
-55 to +125
-40 to +85
o
Tstg
Storage Temperature
-65 to +150
o
o
C
C
C
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress ratingonly and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for external periods may affect device reliability.
All voltage values are referred to VSS pin voltage.
2/13
HCC/HCF4029B
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
VI
Top
Parameter
Supply Voltage: HCC Types
HCF Types
Input Voltage
Operating Temperature: HCC Types
HCF Types
Value
Unit
3 to 18
3 to 15
0 to VDD
V
V
V
o
-55 to +125
-40 to +85
o
C
C
LOGIC DIAGRAMS
TRUTH TABLES
CLOCK
TE
PE
X
X
O
O
X
O
X
I
O
X
I
I
I
X
Q
Q NC
X
I
X
Q
Q NC
X DON’T CARE
J
Q
Q
Control Input
Logic Level
O
I
Q
I
Q
O
BIN/DEC
(B/D)
I
O
Binary Count
Decade Count
UP/DOWN
(U/D)
I
O
Up Count
Down Count
Preset Enable
(PE)
I
O
Jam In
No Jam
No Counter
Advance at Pos.
Clock Transition
I
Carry In (Cl)
(Clock Enable)
O
Action
Advance Counter
at Pos. Clock
Transition
3/13
HCC/HCF4029B
TIMING DIAGRAMS
Binary Mode
Decade Mode
4/13
HCC/HCF4029B
STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)
Test Conditios
Symbol
IL
Parameter
Quiescent
Current
HCC
Types
HCF
Types
V OH
VOL
Output High
Voltage
Output Low
Voltage
VI
(V)
VO
(V)
V IL
IOH
HCF
Types
IOL
Output
Sink
Current
HCC
Types
HCF
Types
IIH, IIL
CI
Input
Leakage
Current
HCC
Types
HCF
Types
Input Capacitance
25 oC
Min. Typ. Max.
THIGH *
Min. Max.
5
0.04
5
150
0/10
0/15
10
15
10
20
0.04
0.04
10
20
300
600
0/20
20
100
0.08
100
3000
0/5
5
20
0.04
20
150
0/10
10
40
0.04
40
300
0/15
0/5
80
0.04
80
<1
15
5
4.95
4.95
4.95
0/10
<1
10
9.95
9.95
9.95
0/15
5/0
<1
<1
15
5
14.95
10/0
<1
10
0.5/4.5
<1
<1
15
5
3.5
3.5
3.5
1/9
<1
10
7
7
7
1.5/13.5
4.5/0.5
<1
<1
15
5
11
9/1
<1
10
13.5/1.5
2.5
<1
0/5
15
5
-2
-1.6
-3.2
-1.15
0/5
4.6
5
-0.64
-0.51
-1
-0.36
0/10
0/15
9.5
13.5
10
15
-1.6
-4.2
-1.3
-3.4
-2.6
-6.8
-0.9
-2.4
0/5
2.5
5
-1.53
-1.36
-3.2
-1.1
0/5
0/10
4.6
9.5
5
10
-0.52
-1.3
-0.44
-1.1
-1
-2.6
-0.36
-0.9
0/15
13.5
15
-3.6
-3.0
-6.8
-2.4
0/5
0/10
0.4
0.5
5
10
0.64
1.6
0.51
1.3
1
2.6
0.36
0.9
0/15
1.5
15
4.2
3.4
6.8
2.4
0/5
0/10
0.4
0.5
5
10
0.52
1.3
0.44
1.1
1
2.6
0.36
0.9
0/15
1.5
15
3.6
3.0
6.8
2.4
Input Low
Voltage
HCC
Types
TLOW *
Min. Max.
5
Input High
Voltage
Output
Drive
Current
|IO| VDD
(µA) (V)
0/5
15/0
VIH
Value
0/18
14.95
Any Input
µA
600
V
14.95
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
11
V
0.05
V
11
1.5
1.5
1.5
3
3
3
4
4
mA
mA
18
±0.1
±10-5
±0.1
±1
15
±0.3
±10
±0.3
±1
5
-5
V
4
Any Input
0/15
Unit
7.5
µA
pF
* TLOW = -55 oC for HCC device: -40 oC for HCF device.
* THIGH = +125 oC for HCC device: +85 oC for HCF device.
The Noise Margin for both ”1” and ”0” level is: 1V min. with VDD = 5 V, 2 V min. with VDD = 10 V, 2.5 V min. with VDD = 15 V
5/13
HCC/HCF4029B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25 o C, C L = 50 pF, RL = 200 KΩ,
o
typical temperature coefficent for all VDD values is 03 %/ C, all input rise and fall times= 20 ns)
Symbol
Parameter
tPLH
tPHL
Propagation Delay Time (Q Outputs)
tPLH
tPHL
Propagation Delay Time (Carry Output)
tTLH
tTHL
Transition Time (Q Outputs, Carry Output)
tW
Minimum Clock Pulse Width
tr, tf **
Clock Rise and Fall Time
tsetup *
Minimum Setup Time (Carry Input)
tsetup
Minimum Setup Time (B/D or UD)
fmax
Maximum Clock Input Frequency
PRESET ENABLE
Propagation Delay Time (Q Outputs)
tPLH
tPHL
tPLH
tPHL
Propagation Delay Time (Carry Output)
tW
Minimum Preset Enable (Pulse Width)
trem *
Minimum Preset Enable (Removal Time)
CARRY INPUT
Propagation Delay Time (Carry Output)
tPHL
tPLH
tsetup ***
Minimum Setup Time (Carry In)
thold
Minimum Hold Time (Carry In)
Test Conditions
VDD (V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Min.
2
4
5.5
Value
Typ.
250
120
90
280
130
95
100
50
40
90
45
30
30
10
6
170
70
50
4
8
11
Max.
500
240
180
560
260
190
200
100
80
180
90
60
15
15
15
60
20
12
340
140
100
Unit
ns
ns
ns
ns
µs
ns
MHz
5
10
15
5
10
15
5
10
15
5
10
15
235
100
80
320
145
105
65
35
25
100
55
40
470
200
160
640
290
210
130
70
50
200
110
80
5
10
15
5
10
15
5
10
15
170
70
50
25
15
12
100
35
30
340
140
100
50
30
25
200
70
60
ns
ns
ns
ns
ns
* From Up/Down, Binary/Decade, Carry In or Preset Enable Control Inputs to Clock Edge
** If more than one unit is cascated in the parallel clocked application tr should be made less than or equal to the sum of the fixed propagation
delay at 15 pF and the transition time of the carry output driving stage for the estimated capacitance load.
*** From Carry in to Clock Edge.
6/13
HCC/HCF4029B
Typical Output Low (sink) Current Characteristics.
Minimum Output Low (sink) Current Charac-
Typical Output High (source) Current Characteristics.
Minimum Output High (source) Current Characteristics.
7/13
HCC/HCF4029B
APPLICATIONS
Conversion of Clock up, Clock Down Input Signals to Clock and Up/Down Inputs Signals.
The HCC/HCF4029B CLOCK and UP/DOWN inputs are used directly in most applications. In applications where CLOCK UP and CLOCK DOWN
inputs are provided, conversion to the
HCC/HCF4029B CLOCK and UP/DOWN inputs
can easily be realized by use of the circuit.
HCC/HCF4029B changes count on positive transitions of CLOCK UP or CLOCK DOWN inputs. For
the gate configuration shown below, when counting
up the CLOCK DOWN input must be maintained
high and conversely when counting down the
CLOCK UP input must be maintained high.
Cascading Counter Packages.
*
CARRY-OUT lines at the 2nd, 3rd, et., stages may have a negative-going glitch pulse resulting from differential delays of different
HCC/HCF4029B IC’s. These negative-going glitches do not affect proper HCC/HCF4029B operation. However, if the CARRY-OUT signals
are used to trigger other edge-sensitive logic devices, such as FF’s or counters, the CARRY-OUT signals should be gated with the clock signal
using a 2-input NOR gate such as HCC/HCF4001B.
Ripple Clocking Mode : The Up/Down control can be changed at any count. The only restriction on changing the Up/Down control is that the
clock input to the first counting stage must be high.
8/13
HCC/HCF4029B
Plastic DIP16 (0.25) MECHANICAL DATA
mm
DIM.
MIN.
a1
0.51
B
0.77
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
9/13
HCC/HCF4029B
Ceramic DIP16/1 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
20
0.787
B
7
0.276
D
E
3.3
0.130
0.38
e3
0.015
17.78
0.700
F
2.29
2.79
0.090
0.110
G
0.4
0.55
0.016
0.022
H
1.17
1.52
0.046
0.060
L
0.22
0.31
0.009
0.012
M
0.51
1.27
0.020
0.050
N
P
Q
10.3
7.8
8.05
5.08
0.406
0.307
0.317
0.200
P053D
10/13
HCC/HCF4029B
SO16 (Narrow) MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.2
a2
MAX.
0.004
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45° (typ.)
D
9.8
E
5.8
10
0.385
6.2
0.228
0.393
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8° (max.)
P013H
11/13
HCC/HCF4029B
PLCC20 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
9.78
10.03
0.385
0.395
B
8.89
9.04
0.350
0.356
D
4.2
4.57
0.165
0.180
d1
2.54
0.100
d2
0.56
0.022
E
7.37
8.38
0.290
0.330
e
1.27
0.050
e3
5.08
0.200
F
0.38
0.015
G
0.101
0.004
M
1.27
0.050
M1
1.14
0.045
P027A
12/13
HCC/HCF4029B
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
13/13