STMICROELECTRONICS HCF4031BEY

HCC/HCF4031B
64-STAGE STATIC SHIFT REGISTER
.
.
..
.
.
..
..
FULLY STATIC OPERATION : DC to 16MHz
(TYP.) @ VDD – VSS = 15V
STANDARD TTL DRIVE CAPABILITY ON Q
OUTPUT
RECIRCULATION CAPABILITY
THREE CASCADING MODES :
DIRECT CLOCKING FOR HIGH-SPEED
OPERATION
DELAYED CLOCKING FOR REDUCED CLOCK
DRIVE REQUIREMENTS
ADDITIONAL 1/2 STAGE FOR SLOW CLOCKS
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA at 18V AND 25°C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD NO. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4031BF
HCF4031BEY
HCF4031BC1
PIN CONNECTIONS
DESCRIPTION
The HCC4031B (extended temperature range) and
HCF4031B (intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package.
The HCC/HCF4031B is a static shift register that
contains 64 D-type, master-slave flip-flop stages
and one stage which is a D-type master flip-flop only
(referred to as a 1/2 stage). The logic level present
at the DATA input is transferred into the first stage
and shifted one stage at each positive-going clock
transition. Maximum clock frequencies up to 16
Megahertz (typical) can be obtained. Because fully
static operation is allowed, information can be permanently stored with the clock line in either the low
or high state. The HCC/HCF4031B has a MODE
CONTROL input that, when in the high state, allows
operation in the recirculating mode. The MODE
CONTROL input can also be used to select between
two separate data sources. Register packages can
be cascaded and the clock lines driven directly for
high-speed operation. Alternatively, a delayed clock
output(CLD) is provided that enables cascading regJune 1989
1/12
HCC/HCF4031B
ister packages while allowing reduced clock drive
fan-out and transition-time requirements. A third
cascading option makes use of the Q’ output from
the 1/2 stage, which is available on the next nega-
tive-going transition of the clock after the Q output
occurs. This delayed output, like the delayed clock
CLD, is used with clocks having slow rise and fall
times.
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V DD*
Parameter
Supply Voltage : HC C Types
H C F Types
VI
Input Voltage
II
Value
Unit
– 0.5 to + 20
– 0.5 to + 18
V
V
– 0.5 to V DD + 0.5
V
DC Input Current (any one input)
± 10
mA
Pt ot
Total Power Dissipation (per package)
Dissipation per Output Transistor
for T o p = Full Package-temperature Range
200
mW
100
mW
Top
Operating Temperature : HCC Types
H CF Types
– 55 to + 125
– 40 to + 85
°C
°C
Tstg
Storage Temperature
– 65 to + 150
°C
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at theseor any other conditions abovethose indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for external periods may affect device reliability.
* All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
V DD
VI
T op
2/12
Parameter
Value
Unit
Supply Voltage : HCC Types
HC F Types
3 to + 18
3 to + 15
V
V
Input Voltage
0 to V DD
V
– 55 to + 125
– 40 to + 85
°C
°C
Operating Temperature : H CC Types
H C F Types
HCC/HCF4031B
LOGIC DIAGRAM AND TRUTH TABLES
INPUT CONTROL CIRCUIT
Data
Recirc.
Mode
Bit Into
Stage 1
1
X
0
1
0
X
0
0
X
1
1
1
X
0
1
0
TYPICAL STAGE
Data
0
1
X
1 = HIGH LEVEL
OUTPUT FROM Q’ (pin 5)
CL
–
–/
–
–/
–\
–
D ata + 1
Data + 6 4
0
0
1
1
NC
X
0 = LOW LEVEL
X = DON’T CARE
CL
–\
–
–\
–
–
–/
Data + 64.5
0
1
NC
NC = NO CHANGE
3/12
HCC/HCF4031B
STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)
Symbol
IL
Parameter
Quiescent
Current
HCC
Types
HCF
Types
V OH
V OL
V IH
V IL
I OH
I OL
Output High
Voltage
Output Low
Voltage
Input High
Voltage
Input Low
Voltage
Output
Source
Current
(Source)
Q, Q, Q
CL D
HCC
Types
HCF
Types
Output
HCC
Sink
Current Q Types
HCF
Types
I OL
I IH , I IL
CI
Output
Sink
Current
Q, Q’
CL D
Input
Leakage
Current
HCC
Types
HCF
Types
Test Conditions
VO
|I O | V D D
VI
(V)
(V)
(µA) (V)
0/ 5
5
0/10
10
0/15
15
0/20
20
0/ 5
5
0/10
10
0/15
15
0/ 5
<1
5
0/10
<1
10
0/15
<1
15
5/0
<1
5
10/0
<1
10
15/0
<1
15
0.5/4.5 < 1
5
1/9
<1
10
1.5/13.5 < 1
15
4.5/0.5 < 1
5
9/1
<1
10
13.5/1.5 < 1
15
0/ 5
2.5
5
0/ 5
4.6
5
0/10
9.5
10
0/15
13.5
15
0/ 5
2.5
5
0/ 5
4.6
5
0/10
9.5
10
0/15
13.5
15
0/ 5
0.4
5
0/10
0.5
10
0/15
1.5
15
0/ 5
0.4
5
0/10
0.5
10
0/15
1.5
15
0/ 5
0.4
5
0/10
0.5
10
0/15
1.5
15
0/ 5
0.4
5
0/10
0.5
10
0/15
1.5
15
HCC 0/18
Types
HCF
0/15
Types
Input Capacitance
T L o w*
Min. Max.
5
10
20
100
20
40
80
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
– 2
– 0.64
– 1.6
– 4.2
– 1.53
– 0.52
– 1.3
– 3.6
2.56
6.4
16.8
2.08
5.01
13.6
0.64
1.6
4.2
0.52
1.3
3.6
Value
25 °C
Min. Typ. Max.
0.04
5
0.04
10
0.04
20
0.08 100
0.04
20
0.04
40
0.04
80
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
– 1.6 – 3.2
– 0.51 – 1
– 1.3 – 2.6
– 3.4 – 6.8
– 1.36 – 3.2
– 0.44 – 1
– 1.1 – 2.6
– 3.0 – 6.8
2.04
4
5.2
10.4
13.6 27.2
1.74
4
4.42 10.4
11.56 27.2
0.51
1
1.3
2.6
3.4
6.8
0.44
1
1.1
2.6
3.0
6.8
18
± 0.1
±10 – 5 ± 0.1
± 1
15
± 0.3
±10 – 5 ± 0.3
± 1
T Hi g h *
Min. Max.
150
300
600
3000
150
300
600
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
– 1.15
– 0.36
– 0.9
– 2.4
– 1.1
– 0.36
– 0.9
– 2.4
1.44
3.6
9.6
1.43
3.74
9.52
0.36
0.9
2.4
0.36
0.9
2.4
5
7.5
* TLow = – 55°C for HCC device : – 40°C for HCF device.
* THigh = + 125°C for HCC device : + 85°C for HCF device.
The Noise Margin for both ”1” and ”0” level is : 1V min. with V DD = 5V, 2V min. with VDD = 10V, 2.5 V min. with VDD = 15V.
4/12
µA
V
V
V
V
mA
mA
mA
µA
Any Input
Any Input
Unit
pF
HCC/HCF4031B
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, C L = 50pF, R L = 200kΩ,
typical temperature coefficient for all V DD values is 0.3%/°C, all input rise and fall times = 20ns)
Symbol
Parameter
Test Conditions
Value
V D D (V) Min.
Typ.
Max.
t P HL ,
Propagation Delay Time :
t PL H, t PL H Clock to Q,
Clock to Q
5
250
500
10
110
220
15
90
180
t P HL ,
Propagation Delay Time :
t PL H, t PHL Clock to Q’
Clock to Q
5
190
380
10
80
160
15
65
130
Clock to CL D
5
100
200
10
50
100
t THL ’ , t T L H Transition Time :
(any output, except Qt THL )
t T HL
tset up
t h o ld
tW
f max
t r, t f
Q,
Data Setup Time
Data Hold Time
Clock Pulse Width
Maximum Clock Input
Frequency**
Clock Input Rise or Fall Time*
15
40
80
5
100
200
10
50
100
15
40
80
5
50
100
10
25
50
15
20
40
5
30
60
10
15
30
15
10
20
5
30
60
10
15
30
15
10
20
5
120
240
10
50
100
15
40
80
5
2
4
10
5
10
15
6
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
MHz
5
1000
10
1000
15
200
µs
* If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of
the propagation delay at 50pF and the transmition time of the output driving stage.
* * Maximum Clock Frequency for Cascaded Units;
a) Using Delayed Clock Feature in Recirculation Mode :
1
fmax =
where n = nimber of packages
(n-1) CLD prop. delay + Q prop. delay + set-up time
b) Not Usng Delaye Clock :
1
fmax =
propagation delay + set-up time
5/12
HCC/HCF4031B
Typical Output Low (sink) Current Characteristics.
Minimum
teristics.
Typical Output High (source) Current Characteristics.
Minimum Output High (source) Current Characteristics.
6/12
Output Low (sink) Current Charac-
HCC/HCF4031B
TYPICAL APPLICATIONS
CASCADING USING DIRECT CLOCKING FOR HIGH SPEED OPERATION (SEE CLOCK RISE AND FALL
TIME REQUIREMENT).
CASCADING USING DELAYED CLOCKING FOR REDUCED CLOCK DRIVE REQUIREMENTS.
7/12
HCC/HCF4031B
TYPICAL APPLICATIONS (continued)
CASCADING USING HALF- CLOCK-PULSE DELAYED DATA OUTPUT (Q’) TO PERMIT USE OF SLOW
RISE AND FALL TIME CLOCK INPUTS.
TEST CIRCUITS
Quiescent Device Current.
Input Leakage Current.
8/12
Noise Immunity.
HCC/HCF4031B
Plastic DIP16 (0.25) MECHANICAL DATA
mm
DIM.
MIN.
a1
0.51
B
0.77
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
9/12
HCC/HCF4031B
Ceramic DIP16/1 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
20
0.787
B
7
0.276
D
E
3.3
0.130
0.38
e3
0.015
17.78
0.700
F
2.29
2.79
0.090
0.110
G
0.4
0.55
0.016
0.022
H
1.17
1.52
0.046
0.060
L
0.22
0.31
0.009
0.012
M
0.51
1.27
0.020
0.050
N
P
Q
10.3
7.8
8.05
5.08
0.406
0.307
0.317
0.200
P053D
10/12
HCC/HCF4031B
PLCC20 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
9.78
10.03
0.385
0.395
B
8.89
9.04
0.350
0.356
D
4.2
4.57
0.165
0.180
d1
2.54
0.100
d2
0.56
0.022
E
7.37
8.38
0.290
0.330
e
1.27
0.050
e3
5.08
0.200
F
0.38
0.015
G
0.101
0.004
M
1.27
0.050
M1
1.14
0.045
P027A
11/12
HCC/HCF4031B
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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