STMICROELECTRONICS IRF740

IRF740

N - CHANNEL 400V - 0.48 Ω - 10 A - TO-220
PowerMESH MOSFET
TYPE
IRF740
■
■
■
■
■
V DSS
R DS(on)
ID
400 V
< 0.55 Ω
10 A
TYPICAL RDS(on) = 0.48 Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
VERY LOW INTRINSIC CAPACITANCES
GATE CHARGE MINIMIZED
DESCRIPTION
This power MOSFET is designed using the
company’s consolidated strip layout-based MESH
OVERLAY process. This technology matches
and improves the performances compared with
standard parts from various sources.
APPLICATIONS
■ HIGH CURRENT SWITCHING
■ UNINTERRUPTIBLE POWER SUPPLY (UPS)
■ DC/DC COVERTERS FOR TELECOM,
INDUSTRIAL, AND LIGHTING EQUIPMENT.
1
2
3
TO-220
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V DS
V DGR
Value
Un it
Drain-source Voltage (V GS = 0)
Parameter
400
V
Drain- gate Voltage (R GS = 20 kΩ)
400
V
G ate-source Voltage
± 20
V
ID
Drain Current (continuous) at Tc = 25 o C
10
A
ID
Drain Current (continuous) at Tc = 100 oC
6.3
A
Drain Current (pulsed)
40
A
V GS
I DM (•)
P tot
dv/dt( 1 )
Ts tg
Tj
o
T otal Dissipation at Tc = 25 C
125
W
Derating Factor
1.0
W /o C
Peak Diode Recovery voltage slope
4.0
V/ns
Storage Temperature
Max. Operating Junction Temperature
-65 to 150
o
C
150
o
C
(•) Pulse width limited by safe operating area
( 1) ISD ≤10 A, di/dt ≤120 Α/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
First Digit of the Datecode Being Z or K Identifies Silicon Characterized in this Datasheet
October 1998
1/8
IRF740
THERMAL DATA
R thj -case
Rthj -amb
R thc-sink
Tl
Thermal Resistance Junction-case
Max
Thermal Resistance Junction-ambient
Max
Thermal Resistance Case-sink
Typ
Maximum Lead Temperature For Soldering Purpose
o
1.0
62.5
0.5
300
C/W
oC/W
o
C/W
o
C
Max Valu e
Unit
AVALANCHE CHARACTERISTICS
Symbo l
Parameter
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
10
A
E AS
Single Pulse Avalanche Energy
o
(starting Tj = 25 C, I D = IAR , VDD = 50 V)
520
mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
Symbo l
V (BR)DSS
Parameter
Drain-source
Breakdown Voltage
Test Con ditions
I D = 250 µA
V DS = Max Rating
Zero G ate Voltage
Drain Current (V GS = 0) V DS = Max Rating
IGSS
Gate-body Leakage
Current (VDS = 0)
T yp.
Max.
400
V GS = 0
I DSS
Min.
Unit
V
T c = 125 oC
V GS = ± 20 V
1
50
µA
µA
± 100
nA
ON (∗)
Symbo l
Parameter
Test Con ditions
ID = 250 µA
V GS(th)
Gate Threshold
Voltage
R DS(on)
Static Drain-source O n V GS = 10V
Resistance
I D(o n)
V DS = V GS
Min.
T yp.
Max.
Unit
2
3
4
V
0.48
0.55
Ω
ID = 5.3 A
10
On State Drain Current V DS > ID(o n) x R DS(on )ma x
V GS = 10 V
A
DYNAMIC
Symbo l
g f s (∗)
C iss
C os s
C rss
2/8
Parameter
Test Con ditions
Forward
Transconductance
V DS > ID(o n) x R DS(on )ma x
Input Capacitance
Output Capacitance
Reverse T ransfer
Capacitance
V DS = 25 V
f = 1 MHz
ID = 6 A
V GS = 0
Min.
T yp.
5.8
Max.
Unit
S
1400
220
27
pF
pF
pF
IRF740
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
Parameter
Test Con ditions
Min.
T yp.
Max.
Unit
t d(on)
tr
Turn-on Time
Rise Time
V DD = 200 V ID = 5 A
VGS = 10 V
R G = 4.7 Ω
(see test circuit, figure 3)
17
10
Qg
Q gs
Q gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V DD = 320 V
35
11
12
43
nC
nC
nC
T yp.
Max.
Unit
I D = 10.7 A V GS = 10V
ns
ns
SWITCHING OFF
Symbo l
tr (Voff)
tf
tc
Parameter
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Con ditions
Min.
10
10
17
V DD = 320 V ID = 10 A
R G = 4.7 Ω V GS = 10 V
(see test circuit, figure 5)
ns
ns
ns
SOURCE DRAIN DIODE
Symbo l
ISD
I SDM (•)
V SD (∗)
t rr
Q rr
I RRM
Parameter
Test Con ditions
Min.
T yp.
Source-drain Current
Source-drain Current
(pulsed)
Forward On Voltage
I SD = 10 A
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD =10 A di/dt = 100 A/µs
T j = 150 o C
V DD = 100 V
(see test circuit, figure 5)
V GS = 0
Max.
Unit
10
40
A
A
1.6
V
370
ns
3.2
µC
17
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
3/8
IRF740
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/8
IRF740
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
5/8
IRF740
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 1: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/8
IRF740
TO-220 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.40
4.60
0.173
0.181
C
1.23
1.32
0.048
0.051
D
2.40
2.72
0.094
D1
0.107
1.27
0.050
E
0.49
0.70
0.019
0.027
F
0.61
0.88
0.024
0.034
F1
1.14
1.70
0.044
0.067
F2
1.14
1.70
0.044
0.067
G
4.95
5.15
0.194
0.203
G1
2.4
2.7
0.094
0.106
H2
10.0
10.40
0.393
0.409
14.0
0.511
L2
16.4
L4
0.645
13.0
0.551
2.65
2.95
0.104
0.116
L6
15.25
15.75
0.600
0.620
L7
6.2
6.6
0.244
0.260
L9
3.5
3.93
0.137
0.154
DIA.
3.75
3.85
0.147
0.151
D1
C
D
A
E
L5
H2
G
G1
F1
L2
F2
F
Dia.
L5
L9
L7
L6
L4
P011C
7/8
IRF740
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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 1998 STMicroelectronics – Printed in Italy – All Rights Reserved
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