Revised January 2004 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description Features The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high level on the respective input. ■ Wide supply voltage range: 3.0V to 15V ■ High noise immunity: 0.45 VDD (typ.) ■ Low power TTL compatibility: or 1 driving 74LS ■ Low power: Fan out of 2 driving 74L 50 nW (typ.) ■ Medium speed operation: 12 MHz (typ.) with 10V supply All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS. Ordering Code: Order Number Package Number Package Description CD4027BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4027BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Truth Table Inputs tn−1 (Note 1) CL (Note 3) J Outputs tn (Note 2) K S R Q Q Q I X O O O I O X O O O I I O O X O O O O I X I O O I O I X X O O X X X X I O X I (No Change) X X X O I X O I X X X I I X I I O I = HIGH Level O = LOW Level X = Don’t Care = LOW-to-HIGH = HIGH-to-LOW Top View Note 1: tn−1 refers to the time interval prior to the positive clock pulse transition Note 2: tn refers to the time intervals after the positive clock pulse transition Note 3: Level Change © 2004 Fairchild Semiconductor Corporation DS005958 www.fairchildsemi.com CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset October 1987 CD4027BC Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 5) (Note 5) DC Supply Voltage (VDD ) Input Voltage (VIN) −0.5 VDC to +18 VDC DC Supply Voltage (VDD) −0.5V to VDD +0.5 VDC −65°C to +150°C Storage Temperature Range (TS) 700 mW Small Outline 500 mW −55°C to +125°C Note 4: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. Lead Temperature (TL) Note 5: VSS = 0V unless otherwise specified. 260°C (Soldering, 10 seconds) 0V to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line 3V to 15 VDC Input Voltage (VIN) DC Electrical Characteristics (Note 6) Symbol IDD VOL VOH VIL VIH IOL IOH IIN Parameter Quiescent Device Current −55°C Conditions Min +25°C Max Min Typ +125°C Max Min Max VDD = 5V, VIN = VDD or VSS 1 1 VDD = 10V, VIN = VDD or VSS 2 2 60 VDD = 15V, VIN = VDD or VSS 4 4 120 30 LOW Level |IO| < 1 µA Output Voltage VDD = 5V 0.05 0 0.05 0.05 VDD = 10V 0.05 0 0.05 0.05 VDD = 15V 0.05 0 0.05 0.05 HIGH Level |IO| < 1 µA Output Voltage VDD = 5V 4.95 4.95 5 VDD = 10V 9.95 9.95 10 9.95 VDD = 15V 14.95 14.95 15 14.95 µA V 4.95 V LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 Input Voltage VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0 VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 Input Voltage VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0 VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 Current (Note 7) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9 VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4 HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 Current (Note 7) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9 VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4 Input Current Units V V 0.36 mA mA VDD = 15V, VIN = 0V −0.1 −10−5 −0.1 −1.0 VDD = 15V, VIN = 15V 0.1 10−5 0.1 1.0 µA Note 6: VSS = 0V unless otherwise specified. Note 7: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD4027BC Absolute Maximum Ratings(Note 4) CD4027BC AC Electrical Characteristics (Note 8) TA = 25°C, CL = 50 pF, trCL = tfCL = 20 ns, unless otherwise specified Symbol tPHL or tPLH tPHL or tPLH tPHL or tPLH tS tTHL or tTLH fCL trCL or tfCL tW tWH Typ Max Propagation Delay Time Parameter VDD = 5V Conditions Min 200 400 from Clock to Q or Q VDD = 10V 80 160 VDD = 15V 65 130 Propagation Delay Time VDD = 5V 170 340 from Set to Q or Reset to Q VDD = 10V 70 140 VDD = 15V 55 110 Propagation Delay Time VDD = 5V 110 220 from Set to Q or VDD = 10V 50 100 Reset to Q VDD = 15V 40 80 Minimum Data Setup Time Transition Time VDD = 5V 135 270 VDD = 10V 55 110 VDD = 15V 45 90 VDD = 5V 100 200 VDD = 10V 50 100 VDD = 15V 40 80 Maximum Clock Frequency VDD = 5V 2.5 5 (Toggle Mode) VDD = 10V 6.2 12.5 VDD = 15V 7.6 15.5 Maximum Clock Rise VDD = 5V 15 and Fall Time VDD = 10V 10 VDD = 15V 5 Units ns ns ns ns ns MHz µs Minimum Clock Pulse VDD = 5V 100 200 Width (tWH = tWL) VDD = 10V 40 80 VDD = 15V 32 65 Minimum Set and VDD = 5V 80 160 Reset Pulse Width VDD = 10V 30 60 VDD = 15V 25 50 7.5 CIN Average Input Capacitance Any Input 5 CPD Power Dissipation Capacity Per Flip-Flop 35 ns ns pF pF (Note 9) Note 8: AC Parameters are guaranteed by DC correlated testing. Note 9: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application note, AN-90. Typical Applications Ripple Binary Counters Shift Registers www.fairchildsemi.com 4 CD4027BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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