FAIRCHILD FOD8316V

FOD8316
2.5A Output Current, IGBT Drive Optocoupler with
Desaturation Detection and Isolated Fault Sensing
Features
Description
■ High Noise Immunity characterized by common mode
The FOD8316 is an advanced 2.5A Output Current
IGBT Drive Optocoupler, capable of driving most 1200V/
150A IGBTs. It is ideally suited for fast switching driving
of power IGBTs and MOSFETs used in motor control
inverter applications and high performance power
systems. It offers critical protection features necessary
for preventing fault conditions that lead to destructive
thermal runaway of IGBTs.
■
■
■
■
■
■
■
■
■
■
■
■
■
■
rejection
– 35kV/µs Minimum Common Mode Rejection
(Vcm = 1500Vpk)
2.5A peak output current driving capability for most
1200V/150A IGBT
Optically isolated fault sensing feedback
“Soft” IGBT turn-off
Built-in IGBT protection
– Desaturation detection
– Under voltage lockout protection
1,414V (peak) working voltage rating
8,000V (peak) transient isolation voltage rating
Wide supply voltage range from 15V to 30V
– Use of P-Channel MOSFETs at output stage
enables output voltage swing close to the supply
rail (rail-to-rail output)
3.3V/5V, CMOS/TTL compatible inputs
High Speed
– 500ns max. propagation delay over full operating
temperature range
Extended industrial temperate range, -40°C to 100°C
temperature range
Safety and regulatory
– UL1577, 4,243 VRMS for 1 min.
– DIN EN/IEC 60747-5-5
RDS(ON) of 1Ω (typ.) offers lower power dissipation
User configurable: inverting, non-inverting, auto-reset,
auto-shutdown
8mm creepage and clearance distances
It utilizes Fairchild’s patented coplanar packaging
technology, Optoplanar®, and optimized IC design to
achieve high noise immunity, characterized by high
common mode rejection and power supply rejection
specifications.
It consists of an integrated gate drive optocoupler featuring low RDS(ON) CMOS transistors to drive the IGBT from
rail to rail and an integrated high speed isolated feedback for fault sensing. The device is housed in a compact 16-pin small outline plastic package which meets
the 8mm creepage and clearance requirements.
Applications
■ Industrial inverter
■ Induction heating
■ Isolated IGBT drive
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
September 2012
VIN+
VIN–
UVLO
(VDD2 – VE)
X
X
Active
X
X
X
DESAT
Detected?
FAULT
VO
X
X
Low
Yes
Low
Low
Low
X
X
X
X
Low
X
High
X
X
X
Low
High
Low
Not Active
No
High
High
Pin Definitions
Pin #
Name
Description
1
VIN+
Non inverting gate drive control input
2
VIN–
Inverting gate drive control input
3
VDD1
Positive input supply voltage (3V to 5.5V)
4
GND1
Input ground
5
RESET
FAULT reset input
6
FAULT
Fault output (open drain)
7
VLED1+
LED 1 anode (must be left unconnected)
8
VLED1-
9
VSS
10
VSS
Output supply voltage (negative)
11
VO
Gate drive output voltage
LED 1 cathode (must be connected to ground)
Output supply voltage (negative)
Source of pull-up PMOS transistor
12
VS
13
VDD2
14
DESAT
Desaturation voltage input
15
VLED2+
LED 2 anode (must be left unconnected)
16
VE
Positive output supply voltage
Output Supply Voltage/IGBT Emitter
VIN+
1
16 VE
VIN–
2
15 VLED2+
VDD1
3
14 DESAT
GND1
4
13 VDD2
RESET
5
12 VS
FAULT
6
11 VO
VLED1+
7
10 VSS
VLED1-*
8
9
VSS
*Pin 8 (VLED1-) is internally connected to Pin 4 (GND1).
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
2
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Truth Table
VLED1+
7
Output IC
VDD1 3
13
Input IC
12
VIN+ 1
VIN– 2
VDD2
VS
FAULT 6
GND1
VLED1–
Driver
LED1
Gate Drive
Optocoupler
UVLO
11
4
8
Shield
DESAT
9,10
14
RESET
VO
5
Fault
16
LED2
VSS
DESAT
VE
Fault Sense
Optocoupler
Shield
15
VLED2+
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
3
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Block Diagram
As per DIN EN/IEC 60747-5-5. This optocoupler is suitable for “safe electrical insulation” only within the safety limit
data. Compliance with the safety ratings shall be ensured by means of protective circuits.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Installation Classifications per DIN VDE 0110/1.89 Table 1
For Rated Mains Voltage < 150Vrms
I–IV
For Rated Mains Voltage < 300Vrms
I–IV
For Rated Mains Voltage < 450Vrms
I–IV
For Rated Mains Voltage < 600Vrms
I–IV
For Rated Mains Voltage < 1000Vrms
I–III
Climatic Classification
40/100/21
Pollution Degree (DIN VDE 0110/1.89)
2
CTI
Comparative Tracking Index
175
VPR
Input to Output Test Voltage, Method b,
VIORM x 1.875 = VPR, 100% Production Test with
tm = 1 sec., Partial Discharge < 5pC
2651
Vpeak
Input to Output Test Voltage, Method a,
VIORM x 1.5 = VPR, Type and Sample Test with
tm = 60 sec.,Partial Discharge < 5 pC
2121
Vpeak
VIORM
Max Working Insulation Voltage
1,414
Vpeak
VIOTM
Highest Allowable Over Voltage
8000
Vpeak
External Creepage
8
mm
External Clearance
8
mm
Insulation Thickness
0.5
mm
Case Temperature
150
°C
Input Power
100
mW
Output Power
600
mW
109
Ω
Safety Limit Values – Maximum Values Allowed in the
Event of a Failure
TCase
PS,INPUT
PS,OUTPUT
RIO
Insulation Resistance at TS, VIO = 500V
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
4
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Safety and Insulation Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
TSTG
Storage Temperature
TOPR
TJ
Value
Units
-40 to +125
ºC
Operating Temperature
-40 to +100
ºC
Junction Temperature
-40 to +125
ºC
260 for 10 sec
ºC
15
mA
TSOL
Lead Wave Solder Temperature
(no solder immersion)
IFAULT
Fault Output Current
Refer to page 27 for reflow temperature profile.
Current(1)
IO(PEAK)
Peak Output
VE – VSS
Negative Output Supply Voltage(2)
VDD2 – VE
Positive Output Supply Voltage
VO(peak)
VDD2 – VSS
VDD1
VIN+, VIN- and VRESET
VFAULT
VS
A
V
-0.5 to 35 – (VE – VSS)
V
Gate Drive Output Voltage
-0.5 to 35
V
Output Supply Voltage
-0.5 to 35
V
Positive Input Supply Voltage
-0.5 to 6
V
Input Voltages
-0.5 to VDD1
V
Fault Pin Voltage
-0.5 to VDD1
V
VSS + 6.5 to VDD2
V
VE to VE + 11
V
100
mW
600
mW
Source of Pull-up PMOS Transistor Voltage
DESAT Voltage
VDESAT
3
0 to 15
Dissipation(3)(5)
PDI
Input Power
PDO
Output Power Dissipation(4)(5)
Notes:
1. Maximum pulse width = 10µs, maximum duty cycle = 0.2%.
2. This negative output supply voltage is optional. It’s only needed when negative gate drive is implemented. Refer to
“Dual Supply Operation – Negative Bias at Vss” on page 23.
3. No derating required across temperature range.
4. Derate linearly above 64°C, free air temperature at a rate of 10.2mW/°C
5. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected
to conditions outside these ratings.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
TA
VDD1
VDD2 – VSS
Parameter
Ambient Operating Temperature
Min.
Max.
Unit
-40
+100
ºC
Supply Voltage(6)
3
5.5
V
Total Output Supply Voltage
15
30
V
Input
VE – VSS
Negative Output Supply Voltage
0
15
V
VDD2 – VE
Positive Output Supply Voltage(6)
15
30 – (VE – VSS)
V
VSS + 7.5
VDD2
V
VS
Source of Pull-up PMOS Transistor Voltage
Note:
6. During power up or down, it is important to ensure that VIN+ remains low until both the input and output supply
voltages reaches the proper recommended operating voltages to avoid any momentary instability at the output state.
See also the discussion in the “Time to Good Power” section on page 23.
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
5
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Absolute Maximum Ratings (TA = 25ºC unless otherwise specified)
Apply over all recommended conditions, typical value is measured at TA = 25ºC
Symbol
Parameter
Conditions
Min.
VISO
Input-Output Isolation
Voltage
TA = 25ºC, R.H.< 50%, t = 1.0min,
II-O ≤ 10µA, 50Hz(7)(8)(9)
RISO
Isolation Resistance
VI-O = 500V(7)
CISO
Isolation Capacitance
VI-O = 0V, Freq =
Typ.
Max.
4,243
1.0MHz(7)
Units
VRMS
1011
Ω
1
pF
Notes:
7. Device is considered a two terminal device: Pins 1 to 8 are shorted together and Pins 9 to 16 are shorted together.
8. 4,243 VRMS for 1 minute duration is equivalent to 5,091 VRMS for 1 second duration.
9. The Input-Output Isolation Voltage is a dielectric voltage rating as per UL1577. It should not be regarded as an
input-output continuous voltage rating. For the continuous working voltage rating refer to your equipment level safety
specification or DIN EN/IEC 60747-5-5 Safety and Insulation Ratings Table.
Electrical Characteristics
Apply over all recommended conditions, typical value is measured at VDD1 = 5V, VDD2 – VSS = 30V, VE – VSS = 0V,
TA = 25°C unless otherwise specified.
Symbol
Parameter
Conditions
VIN+L, VIN-L,
VRESETL
Logic Low Input Voltages
VIN+H, VIN-H,
VRESETH
Logic High Input Voltages
IIN+L, IIN-L,
IRESETL
Logic Low Input Currents
VIN = 0.4V
IFAULTL
FAULT Logic Low Output Current
VFAULT = 0.4V
IFAULTH
FAULT Logic High Output Current VFAULT = VDD1
High Level Output Current
VO = VDD2 – 3V
IOH
Low Level Output Current
Typ.
Max.
0.8
2.0
-0.5
VO = VDD2 – 6V(10)
IOL
Min.
VO = VSS + 3V
Units Figure
V
V
-0.001
mA
5.0
12.0
mA
1, 32
-40
0.002
µA
32
-1
-3
A
2, 7, 33
-2.5
1
A
3
VO = VSS + 6V(11)
2.5
90
185
VS – 1.0V
VS – 0.5V
A
3, 34
A
IOLF
Low Level Output Current During
Fault Condition
VO – VSS = 14V
VOH
High Level Output Voltage
IO = –100mA(12)(13)(14)
VOL
Low Level Output Voltage
IO = 100mA
IDD1H
High Level Supply Current
IDD1L
Low Level Supply Current
IDD2H
High Level Output Supply Current VO = Open(14)
1
3
mA
IDD2L
Low Level Output Supply Current
VO = Open
0.8
2.8
mA
10, 11,
37
ISH
High Level Source Current
IO = 0mA
0.65
1.5
mA
37
ISL
Low Level Source Current
IO = 0mA
0.6
1.4
mA
37
IEL
VE Low Level Supply Current
-0.5
-0.2
mA
13, 37
IEH
VE High Level Supply Current
-0.5
-0.25
mA
-0.13
-0.25
10
36
ICHG
IDSCHG
230
mA
V
5, 7, 35
0.1
0.5
V
6, 8, 35
VIN+ = VDD1 = 5.5V,
VIN– = 0V
14
17
mA
9, 36
VIN+ = VIN- = 0V,
VDD1 = 5.5V
2
3
mA
Blanking Capacitor Charge
Current
VDESAT = 2V(14)(15)
Blanking Capacitor
Discharge Current
VDESAT = 7V
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
-0.37
4, 38
mA
12, 38
mA
38
www.fairchildsemi.com
6
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Isolation Characteristics
Apply over all recommended conditions, typical value is measured at VDD1 = 5V, VDD2 – VSS = 30V, VE – VSS = 0V,
TA = 25°C unless otherwise specified.
Symbol
VUVLO+
VUVLOUVLOHYS
VDESAT
Parameter
Conditions
Under Voltage Lockout
Threshold(14)
VO > 5V @ 25°C
Under Voltage Lockout
Threshold Hysteresis
DESAT Threshold(14)
Min.
VO < 5V @ 25°C
Typ.
Max.
11.5
13.5
Units Figure
V
9
10
V
@ 25°C
0.4
1.5
V
VDD2 – VE > VULVO- ,
VO < 5V
6.0
7.0
9.0
V
15, 29,
39
16, 38
Notes:
10. Maximum pulse width = 10µs, maximum duty cycle = 0.2%.
11. Maximum pulse width = 4.99ms, maximum duty cycle = 99.8%.
12. VOH is measured with the DC load current in this testing (Maximum pulse width = 1ms,
Maximum duty cycle = 20%).When driving capacitive loads, VOH will approach VDD as IOH approaches zero units.
13. Positive Output supply voltage (VDD2 – VE) should be at least 15V. This is to ensure adequate margin in excess of
the maximum Under Voltage Lockout Threshold VUVLO+ of 13.5V.
14. When VDD2 – VE > VUVLO and output state VO of the FOD8316 is allowed to go high, the DESAT detection feature
will be active and will provide the primary source of IGBT protection. UVLO is needed to ensure DESAT detection
is functional.
15. The blanking time, tBLANK is adjustable by an external capacitor (CBLANK) where tBLANK = CBLANK * (VDESAT/ICHG)
Switching Characteristics
Apply over all recommended conditions, typical value is measured at VDD1 = 5V, VDD2 – VSS = 30V, VE – VSS = 0V,
TA = 25°C unless otherwise specified.
Symbol
Parameter
tPHL
Propagation Delay Time to
Logic Low Output(17)
tPLH
Propagation Delay Time to
Logic High Output(18)
PWD
Pulse Width Distortion,
| tPHL – tPLH|(19)
PDD Skew
Conditions
Min.
Rg = 10Ω, Cg = 10nF,
f = 10kHz,
Duty Cycle = 50%(16)
Typ.
Max.
300
500
ns
250
500
ns
50
300
ns
350
ns
–350
Propagation Delay Difference
Between Any Two Parts or
Channels, ( tPHL – tPLH)(20)
Units Figure
17, 18,
19, 20,
21, 22,
40, 48
tR
Output Rise Time (10% – 90%)
34
ns
tF
Output Fall Time (90% – 10%)
34
ns
850
ns
23, 41
tDESAT(90%)
DESAT Sense to 90% VO Delay(21)
tDESAT(10%)
(21)
DESAT Sense to 10% VO Delay
Rg = 10Ω, Cg = 10nF,
VDD2 – VSS = 30V
2
3
µs
24, 26,
27, 41
5
µs
25, 41,
49
ns
41
µs
28, 42,
49
tDESAT(FAULT)
DESAT Sense to Low Level FAULT
Signal Delay(22)
1.8
tDESAT(LOW)
DESAT Sense to DESAT Low
Propagation Delay(23)
850
tRESET(FAULT)
RESET to High Level FAULT Signal
Delay(24)
PWRESET
RESET Signal Pulse Width
tUVLO ON
UVLO Turn On Delay(25)
tUVLO OFF
(26)
UVLO Turn Off Delay
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
3
6
1.2
VDD2 = 20V in
1.0ms Ramp
40, 48
20
µs
4
µs
3
µs
29, 43
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7
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Electrical Characteristics (Continued)
Apply over all recommended conditions, typical value is measured at VDD1 = 5V, VDD2 – VSS = 30V, VE – VSS = 0V,
TA = 25°C unless otherwise specified.
Symbol
tGP
Parameter
Conditions
(27)
VDD2 = 0 to 30V in
10µs Ramp
Time to Good Power
Min.
Typ.
Max.
Units Figure
30
µs
30, 31,
43
| CMH |
Common Mode Transient
Immunity at Output High
TA = 25ºC, VDD1 = 5V,
VDD2 = 25V,
VSS = Ground,
VCM = 1500Vpk(28)
35
50
kV/µs
45, 46
| CML |
Common Mode Transient
Immunity at Output Low
TA = 25ºC, VDD1 = 5V,
VDD2 = 25V,
VSS = Ground,
VCM = 1500Vpk(29)
35
50
kV/µs
44, 47
Notes:
16. This load condition approximates the gate load of a 1200 V/150A IGBT.
17. tPHL propagation delay is measured from the 50% level on the falling edge of the input pulse(VIN+, VIN-) to the 50%
level of the falling edge of the VO signal. Refer to Figure 48.
18. tPHL propagation delay is measured from the 50% level on the rising edge of the input pulse (VIN+, VIN-) to the 50%
level of the rising edge of the VO signal. Refer to Figure 48.
19. PWD is defined as | tPHL – tPLH | for any given device.
20. The difference between tPHL and tPLH between any two FOD8316 parts under same operating conditions, with equal
loads.
21. This is the amount of time the DESAT threshold must be exceeded before VO begins to go low. This is supply voltage
dependent. See Figure 49.
22. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
See Figure 49.
23. This is the amount of time the DESAT threshold must be exceeded before VO begins to go low, and the FAULT
output to go low. See Figure 49.
24. This is the amount of time from when RESET is asserted low, until FAULT output goes high. See Figure 49.
25. tUVLO ON UVLO Turn On Delay is measured from VUVLO+ threshold voltage of the output supply voltage (VDD2) to
the 5V level of the rising edge of the VO signal.
26. tUVLO OFF UVLO Turn Off Delay is measured from VUVLO– threshold voltage of the output supply voltage (VDD2) to
the 5V level of the falling edge of the VO signal.
27. tGP Time to Good Power is measured from 13.5V level of the rising edge of the output supply voltage (VDD2) to the
5V level of the rising edge of the VO signal.
28. Common mode transient immunity at output high state is the maximum tolerable negative dVCM/dt on the trailing
edge of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V or
FAULT > 2 V).
29.Common mode transient immunity at output low state is the maximum positive tolerable dVCM/dt on the leading
edge of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V or FAULT
< 0.8 V).
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
8
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Switching Characteristics (Continued)
Figure 1. Fault Logic Low Output Current (IFAULTL) vs.
Fault Logic Low Output Voltage (VFAULTL)
Figure 2. Output High Current (IOH) vs. Temperature
7
IOH – OUTPUT HIGH CURRENT (A)
IFAULTL – FAULT CURRENT (mA)
50
40
30
20
VDD1 = 5V
VIN+ = 5V
ILED2+ = 10mA
TA = 25°C
10
0
0
1
2
3
4
6
5
VO = V DD2 – 6V
4
3
VO = V DD2 – 3V
2
1
VDD2 – V SS = 30V
VDD1 = 5V
0
-40
-20
0
5
VFAULTL – FAULT VOLTAGE (V)
6
5
VO = V SS + 6V
4
3
VO = V SS + 3V
2
1
100
VDD2 – V SS = 30V
VDD1 = 5V
-20
0
20
40
60
80
TA = -40°C
TA = 25°C
175
125
100
75
VDD2 – V SS = 30V
VDD1 = 5V
50
25
0
100
TA = 100°C
150
5
10
15
20
25
30
VO – OUTPUT VOLTAGE (V)
Figure 5. Output High Voltage (VOH–VDD2) vs. Temperature
Figure 6. Output Low Voltage (VOL) vs. Temperature
0.1
0.25
IO = -650μA
0
VOL – OUTPUT LOW VOLTAGE (V)
(VOH–VDD2) – HIGH OUTPUT VOLTAGE DROP (V)
80
200
TA – TEMPERATURE (°C)
-0.1
IO = -100mA
-0.2
-0.3
-0.5
-40
60
225
IOLF – LOW LEVEL OUTPUT CURRENT
DURING FAULT CONDITIONS (mA)
IOL – OUTPUT LOW CURRENT (A)
7
-0.4
40
Figure 4. Low Level Output Current (IOLF) vs.
Output Voltage (VO)
Figure 3. Output Low Current (IOL) vs. Temperature
0
-40
20
TA – TEMPERATURE (°C)
VDD2 – V SS = 30V
VDD1 = 5V
VIN+ = 5V
-20
0
20
40
60
80
0.15
IO = 100mA
0.10
0.05
0
-40
100
TA – TEMPERATURE (°C)
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
0.20
VDD2 – V SS = 30V
VDD1 = 5V
VIN+ = 0V
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
www.fairchildsemi.com
9
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Typical Performance Characteristics
Figure 7. Output High Voltage (VOH) vs.
Output High Current (IOH)
29
TA = -40°C
25°C
28
100°C
27
26
VDD2 – V SS = 30V
VDD1 = 5V
VIN+ = 5V
25
0
0.5
1.0
1.5
Figure 8. Output Low Voltage (VOL) vs.
Output Low Current (IOL)
5
VOL – OUTPUT LOW VOLTAGE (V)
VOH – OUTPUT HIGH VOLTAGE (V)
30
2.0
VDD2 – V SS = 30V
VDD1 = 5V
VIN+ = 0V
4
3
TA = 100°C
2
25°C
-40°C
1
0
2.5
0
0.5
IOH – OUTPUT HIGH CURRENT (A)
Figure 9. Supply Current (IDD1) vs. Temperature
IDD2 – OUTPUT SUPPLY CURRENT (mA)
IDD1 – SUPPLY CURRENT (mA)
15
2.5
IDD1H
10
5
IDD1L
-20
0
20
40
60
80
1.2
IDD2H
1.0
0.8
IDD2L
0.6
VDD2 – V SS = 30V
VDD1 = 5V
VIN+ = 5V (IDD2H) or 0V (IDD2L)
0.4
-40
100
-20
0
TA – TEMPERATURE (°C)
20
40
60
80
100
TA – TEMPERATURE (°C)
Figure 11. Output Supply Current (IDD2) vs.
Output Supply Voltage (VDD2)
Figure 12. Blanking Capacitor Charging Current (ICHG)
vs. Temperature
1.2
-0.15
ICHG – BLANKING CAPACITOR CHARGING
CURRENT (mA)
IDD2 – OUTPUT SUPPLY CURRENT (mA)
2.0
1.4
VDD1 = 5.5V
VIN+ = 5V (IDD1H) or 0V (I DD1L)
VDD1 = 5V
VIN+ = 5V (IDD2H) or 0V (IDD2L)
1.0
IDD2H
0.8
IDD2L
0.6
0.4
15
1.5
Figure 10. Output Supply Current (IDD2) vs. Temperature
20
0
-40
1.0
IOL – OUTPUT LOW CURRENT (A)
20
25
-0.20
-0.25
-0.30
-40
30
VDD2 – OUTPUT SUPPLY VOLTAGE (V)
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
VDD2 – V SS = 30V
VDD1 = 5V
VIN+ = 5V
VDESAT = 0V to 6V
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
www.fairchildsemi.com
10
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Typical Performance Characteristics (Continued)
Figure 13. Supply Current (IE) vs. Temperature
Figure 14. Source Current (IS) vs. Output Current (IO)
-0.10
3.0
IS – SOURCE CURRENT (mA)
IE – SUPPLY CURRENT (mA)
-0.15
IEL
-0.20
IEH
-0.25
-0.30
-0.35
VDD2 – V SS = 30V
VDD1 = 5V
VIN+ = 5V (IEH) / 0V (IEL)
-0.40
-40
-20
0
20
40
60
80
2.5
2.0
1.5
1.0
0.5
0
100
-40°C
25°C
100°C
VDD2 – V SS = 30V
VDD1 = 5V
VIN+ = 5V
0
0.5
TA – TEMPERATURE (°C)
Figure 15. Under Voltage Lockout Threshold (VUVLO)
vs. Temperature
V UVLO – UNDER VOLTAGE LOCKOUT THRESHOLD (V)
1.0
1.5
2.0
IO – OUTPUT CURRENT (mA)
Figure 16. DESAT Threshold (VDESAT) vs. Temperature
8.0
VDESAT – DESAT THRESHOLD (V)
15
V UVLO+
10
V UVLO–
5
7.5
7.0
6.5
VDD2 – V SS = 30V
VDD1 = 5V
VIN+ = 5V
VDD1 = 5V
VIN+ = 5V
0
-40
-20
0
20
40
60
80
6.0
-40
100
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
TA – TEMPERATURE (°C)
Figure 18. Propagation Delay (tP) vs.
Supply Voltage (VDD2)
Figure 17. Propagation Delay (tP) vs. Temperature
0.5
0.45
tP – PROPAGATION DELAY (μs)
tP – PROPAGATION DELAY (μs)
0.40
0.4
tPLH
0.3
tPHL
0.2
0.1
-40
VDD2 – V SS = 30V
VDD1 = 5V
f = 10kHz 50% Duty Cycle
RL = 10Ω, CL = 10nF
-20
0
20
40
60
80
tPLH
0.30
tPHL
0.25
0.20
0.15
0.10
15
100
TA – TEMPERATURE (°C)
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
0.35
VDD1 = 5V
f = 10kHz 50% Duty Cycle
RL = 10Ω, CL = 10nF
20
25
30
VDD2 – SUPPLY VOLTAGE (V)
www.fairchildsemi.com
11
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Typical Performance Characteristics (Continued)
Figure 20. Propagation Delay Time to
Logic Low Output (tPHL) vs. Temperature
Figure 19. Propagation Delay Time to
Logic High Output (tPLH) vs. Temperature
0.35
VDD2 – V SS = 30V
f = 10kHz 50% Duty Cycle
RL = 10Ω, CL = 10nF
tPHL – PROPAGATION DELAY (μs)
tPLH – PROPAGATION DELAY (μs)
0.45
0.40
0.35
0.30
VDD1 = 4.5V
VDD1 = 5.0V
VDD1 = 5.5V
0.25
-40
-20
0
20
40
60
80
VDD2 – V SS = 30V
f = 10kHz 50% Duty Cycle
RL = 10Ω, CL = 10nF
0.30
0.25
0.20
VDD1 = 4.5V
VDD1 = 5.0V
VDD1 = 5.5V
0.15
-40
100
-20
0
TA – TEMPERATURE (°C)
Figure 21. Propagation Delay (tP) vs. Load Capacitance (CL)
VDD2 – V SS = 30V
VDD1 = 5V
f = 10kHz 50% Duty Cycle
RL = 10Ω
0.35
tP – PROPAGATION DELAY (μs)
tP – PROPAGATION DELAY (μs)
60
80
100
0.40
tPLH
0.30
tPHL
0.25
0
20
40
60
80
0.35
tPLH
0.30
tPHL
0.25
0.20
100
VDD2 – V SS = 30V
VDD1 = 5V
f = 10kHz 50% Duty Cycle
CL = 10nF
0
10
CL – LOAD CAPACITANCE (nF)
Figure 23. DESAT Sense to 90% VO (tDESAT(90%))
vs. Temperature
1.2
VDD2 – V SS = 30V
VDD1 = 5V
VIN+ = 5V
RL = 10Ω, CL = 10nF
1.1
1.0
0.9
0.8
-40
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
20
30
40
50
RL – LOAD RESISTANCE (Ω)
tDESAT(10%) – DESAT SENSE TO 10% VO DELAY (μs)
tDESAT(90%) – DESAT SENSE TO 90% VO DELAY (μs)
40
Figure 22. Propagation Delay (tP) vs. Load Resistance (RL)
0.40
0.20
20
TA – TEMPERATURE (°C)
Figure 24. DESAT Sense to 10% VO Delay (tDESAT(10%))
vs. Temperature
3.0
VDD2 – V SS = 15 or 30V
VDD1 = 5V
VIN+ = 5V
RL = 10Ω, CL = 10nF
2.5
VDD2 – V SS = 30V
2.0
VDD2 – V SS = 15V
1.5
1.0
-40
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
www.fairchildsemi.com
12
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Typical Performance Characteristics (Continued)
Figure 25. DESAT Sense to Low Fault Signal Delay (tDESAT(FAULT))
vs. Temperature
0.008
VDD2 – V SS = 30V
VDD1 = 5V
VIN+ = 5V
RL = 10Ω, CL = 10nF
2.4
tDESAT(10%) – DESAT SENSE TO 10% VO
tDESAT(FAULT) – DESAT SENSE TO LOW FAULT
SIGNAL DELAY (μs)
2.6
2.2
VE – V SS = 0V
VE – V SS = 15V
2.0
1.8
1.6
-40
-20
0
20
40
60
80
100
Figure 26. DESAT Sense to 10% VO Delay (tDESAT(10%))
vs. Load Capacitance (CL)
VDD2 – V SS = 15V or 30V
VDD1 = 5V
VIN+ = 5V
RL = 10Ω
0.006
VDD2 – V SS = 30V
0.004
0.002
0
VDD2 – V SS = 15V
0
5
Figure 27. DESAT Sense to 10% VO Delay (tDESAT(10%))
vs. Load Resistance (RL)
15
20
25
30
Figure 28. RESET to High Level FAULT Signal
Delay (tRESET(FAULT)) vs. Temperature
0.0030
10
VDD2 – V SS = 15V or 30V
VDD1 = 5V
VIN+ = 5V
CL = 10nF
0.0250
VDD2 – V SS = 30V
0.0020
VDD2 – V SS = 15V
0.0015
0.0010
10
20
30
40
50
9
VDD1 = 5.0V
6
VDD1 = 4.5V
5
4
-40
100
tGP – TIME TO GOOD POWER (μs)
VDD2 = 20V
VDD1 = 5V
VIN+ = 5V
f = 50Hz, 50% Duty Cycle
tR = 1ms
6
tUVLO ON
4
tUVLO OFF
2
-20
0
20
40
60
80
0
20
40
60
80
100
Figure 30. Time to Good Power (tGP)
vs. Supply Voltage (VDD2)
VDD1 = 5V
VIN+ = 5V
f = 50Hz, 50% Duty Cycle
80
60
40
20
0
15
100
TA – TEMPERATURE (°C)
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
-20
TA – TEMPERATURE (°C)
10
0
-40
VDD1 = 5.5V
7
Figure 29. Under Voltage Lockout Threshold Delay (tUVLO)
vs. Temperature
8
VDD2 – V SS = 30V
VIN+ = 5V
RL = 10Ω, CL = 10nF
8
RL – LOAD RESISTANCE (Ω)
tUVLO – UNDER VOLTAGE LOCKOUT
THRESHOLD DELAY (μs)
10
CL – LOAD CAPACITANCE (nF)
tRESET(FAULT) – RESET TO HIGH LEVEL FAULT
SIGNAL DELAY (μs)
tDESAT(10%) – DESAT SENSE TO 10% VO DELAY (μs)
TA – TEMPERATURE (°C)
20
25
30
VDD2 – SUPPLY VOLTAGE (V)
www.fairchildsemi.com
13
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Typical Performance Characteristics (Continued)
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Typical Performance Characteristics (Continued)
Figure 31. Time to Good Power (tGP)
vs. Temperature
tGP – TIME TO GOOD POWER (μs)
120
100
VDD2 = 15V to 30V
VDD1 = 5V
VIN+ = 5V
f = 50Hz 50% Duty Cycle
80
60
40
20
0
-40
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
14
+
–
5V
VFAULT
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
A
0.1μF
10mA
0.1μF
–
+
IFAULT
VFAULT = 0.4V for IFAULTL
VDD2 13
9
Switch A closed for IFAULTL
Switch A opened for IFAULTH
VFAULT = 5.0V for IFAULTH
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 32. Fault Output Current (IFAULTL) and (IFAULTH) Test Circuit
Pulse Gen
PW = 10μs
Period = 5ms
+
–
0.1μF
5V
–
+
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
VDD2 13
+
–
0.1μF
0.1μF 47μF
VE
0.1μF 47μF
+
–
VO
+
–
30V
3kΩ
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 33. High Level Output Current (IOH) Test Circuit
Pulse Gen
PW = 4.99ms
Period = 5ms
+
–
0.1μF
5V
–
+
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
0.1μF
+
–
VE
+
–
30V
VDD2 13
0.1μF 47μF
3kΩ
VO
+
–
9
0.1μF 47μF
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 34. Low Level Output Current (IOL) Test Circuit
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
15
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Test Circuits
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Test Circuits (Continued)
A
B
5V
0.1μF
+
–
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
0.1μF
VDD2 13
+
–
100mA
pulsed
VO
B
A
3kΩ
Switch A for VOH test
Switch B for VOL test
VE
0.1μF
30V
+
–
100mA
pulsed
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 35. High Level (VOH) and Low Level (VOL) Output Voltage Test Circuit
A
B
+
–
5V
0.1μF
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
IDD1
Switch A for IDD1H test
Switch B for IDD1L test
VDD2 13
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 36. High Level (IDD1H) and Low Level (IDD1L) Supply Current Test Circuit
A
B
0.1μF
5V
+
–
FOD8316
IE
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
Switch A for IDD2H, ISH and IEH test
Switch B for IDD2L, ISL and IEL test
VDD2 13
0.1μF
VE
+
–
IDD2
IS
VO
0.1μF
30V
+
–
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 37. High Level (IDD2H), Low Level (IDD2L) Output Supply Current,
High Level (ISH), Low Level (ISL) Source Current,
VE High Level (IEH), and VE Low Level (IEL) Supply Current Test Circuit
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
16
5V
+
–
VE 16
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VDESAT
+
–
0.1μF
FOD8316
1
ICHG/DSCHG
0.1μF
VE
+
–
VDD2 13
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
VRL
VO
RL
0.1μF
IOLF
3K
30V
+
–
10nF
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 38. Low Level Output Current During Fault Conditions (IOLF), Blanking Capacitor Charge Current (ICHG),
Blanking Capacitor Discharging Current (IDSCHG) and DESAT Threshold (VDESAT) Test Circuit
5V
0.1μF
+
–
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
VDD2 13
DC Sweep
0 to 15V
(100 steps)
Parameter
Analyzer
VO
0.1μF
+
–
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 39. Under Voltage Lockout Threshold (VUVLO) Test Circuit
F = 10kHz
DC = 50%
+
–
0.1μF
5V
+
–
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
0.1μF
VE
+
–
VDD2 13
VCL
VO
RL
3K
0.1μF
30V
+
–
10nF
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 40. Propagation Delay (tPLH, tPHL), Pulse Width Distortion (PWD),
Rise Time (tR) and Fall Time (tF) Test Circuit
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
17
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Test Circuits (Continued)
Low to High
+
–
5V
0.1μF
+
–
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
100pF
+
–
VE
VDD2 13
VO
RL
3K
VFAULT
0.1μF
0.1μF
+
–
30V
10nF
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 41. DESAT Sense (tDESAT(90%), tDESAT(10%)), DESAT Fault (tDESAT(FAULT)), and (tDESAT(LOW)) Test Circuit
0.1μF
5V
+
–
3K
FOD8316
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
–
8
VLED1-*
VSS
Strobe 8V
0.1μF
+
–
VE
VDD2 13
VO
RL
+
VFAULT
VE 16
1
0.1μF
+
–
30V
10nF
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 42. Reset Delay (tRESET(FAULT)) Test Circuit
0.1μF
5V
+
–
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
0.1μF
VE
+
–
VDD2 13
VO
+
3K
0.1μF
VDD2**
–
9
**1.0ms ramp for tUVLO
10μs ramp for tGP
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 43. Under Voltage Lockout Delay (tUVLO) and Time to Good Power (tGP) Test Circuit
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
18
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Test Circuits (Continued)
5V
0.1μF
1kΩ
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
25V
0.1μF
VDD2 13
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
SCOPE
10Ω
300pF
10nF
9
VCM
Floating GND
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 44. Common Mode Low (CML) Test Circuit @ LED1 Off
5V
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
10Ω
8
VLED1-*
VSS
10nF
25V
0.1μF
VDD2 13
0.1μF
1kΩ
300pF
Floating GND
9
SCOPE
VCM
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 45. Common Mode High (CMH) Test Circuit @ LED1 On
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
19
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Test Circuits (Continued)
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Test Circuits (Continued)
5V
0.1μF
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
10Ω
8
VLED1-*
VSS
10nF
25V
VDD2 13
0.1μF
1kΩ
SCOPE
300pF
9
VCM
Floating GND
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 46. Common Mode High (CMH) Test Circuit @ LED2 Off
5V
0.1μF
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
750Ω
25V
VDD2 13
0.1μF
1kΩ
SCOPE
300pF
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
10Ω
8
VLED1-*
VSS
10nF
VCM
9
+
–
9V
Floating GND
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 47. Common Mode Low (CML) Test Circuit @ LED2 On
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
20
VIN+
2.5V
VIN–
0V
2.5V
tR
tF
90%
50%
10%
VO
tPLH
tPHL
Figure 48. Propagation Delay (tPLH, tPHL), Rise Time (tR) and Fall Time (tF) Timing Diagram
RESET
50%
7V
VDESAT
tDESAT (LOW)
tRESET (FAULT)
50%
tDESAT (90%)
90%
VO
10%
tDESAT (10%)
50% (0.5 x VDD1)
FAULT
tDESAT (FAULT)
Figure 49. Definitions for Fault Reset Input (RESET), Desaturation Voltage Input (DESAT), Output Voltage (VO)
and Fault Output (FAULT) Timing Waveforms
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
21
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Timing Diagrams
Micro
Controller
5V +
1kΩ
1
VIN+
2
VE
16
VIN–
VLED2+
15
3
VDD1
DESAT
14
4
GND1
VDD2
13
5
RESET
VS
12
6
FAULT
VO
11
7
VLED1+
VSS
10
8
VLED1-
VSS
9
0.1μF
–
330pF
FOD8316
C2
1μF
C3
10μF
100pF
100Ω
+
–
C1
1μF
DDESAT
+
–
VF
VDD2 = 15V
+
Q1
VCE
Rg
+
–
D1
VSS = –8V
–
3-Phase
Output
Q2
+
VCE
–
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 50. Recommended Application Circuit
Functional Description
The relationship between the inputs and output are
illustrated in the Figure 52.
The typical application circuit is shown in Figure 50 and
the functional behavioral of the FOD8316 is illustrated by
the detailed internal schematic shown in Figure 51. This
helps explain the interaction and sequence of internal
and external signals, together with the timing diagrams.
1. Non-Inverting and Inverting Inputs
During normal operation, when no fault is detected, the
FAULT output, which is an open-drain configuration, will
be latched to high state. This allows the gate driver to be
controlled by the input logic signal.
There are two CMOS/TTL compatible inputs, VIN+ and
VIN- to control the IGBT, in non-inverting and inverting
configurations respectively. When VIN- is set to low, VIN+
controls the driver output, VO, in non-inverting configuration. When VIN+ is set to high, VIN- controls the driver
output in inverting configuration.
When a fault is detected, the FAULT output will be
latched to low state. This condition will remain until the
RESET pin is also pulled low for a period longer than
PWRESET. While setting the RESET pin to a low state,
the input pins must be pulled to low to ensure an output
state (VIN+ is low or VIN- is high).
250μA
+
–
VLED+
VDD1 3
7
VIN+ 1
VIN– 2
FAULT
14
Gate Drive
Optocoupler
16
UVLO Comparator
6
–
+
13
12V
12
4
GND1
VLED1–
VE
VDD2
VS
Delay
8
11
Q
R S
RESET
DESAT
VDESAT
5
Fault Sense
Optocoupler
VO
50x
5μs Pulse
Generator
1x
9,10
VSS
15
VLED2+
Figure 51. Detailed Internal Schematic
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
22
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Application Information
4. “Soft” Turn-Off
A pair of PMOS and NMOS transistors made up the
output driver stage, which facilitates close to rail-to-rail
output swing. This feature allows a tight control of gate
voltage during on-state and short circuit condition. The
output driver is typically capable of sinking 2A and sourcing 2A at room temperature. Due to the low RDS(ON) of
the MOSFETs, the power dissipation is reduced as
compared to those bipolar-type driver output stages. The
absolute maximum rating of the output peak current,
IO(PEAK) is 3A, thus the careful selection of the gate
resistor, Rg, is required to limit the short circuit current of
the IGBT.
The soft turn-off feature ensures the safe turn off of the
IGBT under fault condition. This reduces the voltage
spike on the collector of the IGBT. Without this, the IGBT
would see a heavy spike on the collector and hence
resulting in a permanent damage to the device when it’s
turned off immediately.
5. Under Voltage Lockout
Under voltage detection prevents the application of
insufficient gate voltage to the IGBT. This could be dangerous, as it would drive the IGBT out of saturation and
into the linear operation where the losses are very high
and quickly overheated. This feature ensures the proper
operating of the IGBTs. The output voltage, VO, remains
low irregardless of the inputs as long as the supply voltage, VDD2 – VE, is less than VULVO+. When the supply
voltage falls below VULVO- , VO will go low, as illustrated
in Figure 54.
As shown in Figure 51, the gate driver output is influenced by signals from the photodetector circuitry, the
UVLO comparator and the DESAT signals. Under no
fault condition, normal operation resumes while the supply voltage is above the UVLO threshold, the output of
the photodetector will drive the MOSFETs of the output
stage.
6. Time to Good Power
At initial power up, the LED is off and the output of the
gate driver should be in the low or off state. Sometimes
race conditions exist that causes the output to follow the
VD (assuming VDD2 and VE are connected externally),
until all of the circuits in the output IC have stabilized.
This condition can result in output transitions or transients that are coupled to the driven IGBT. These
transients can cause the high and low side IGBTs to
conduct shoot-through current that may result in destructive damage to the power semiconductor devices.
Fairchild has introduced an initial turn-on delay which is
generally regarded as “time to good power”. This delay,
typically 30µs, is only present during the initial power-up
of the device. Once powered, the “time to good power”
delay is determined by the delay of the UVLO circuitry. If
the LED is “ON” during the initial turn-on activation, low
to high transition at the output of the gate driver will only
occur 30µs after the VDD2 power is applied.
The logic circuitry of the output stage will ensure that the
push-pull devices will never be turned “ON” simultaneously. When the output of the photodetector is high,
the output, VO will be pulled to high state by turning on
the PMOS. When the output of the photodetector is low,
VO will be pulled to low state by turning on the NMOS.
When VDD2 supply goes below VUVLO, which is the designated ULVO threshold at the comparator, VO will be
pulled down to low state regardless of photodetector
output.
When desaturation is detected, VO will turn off slowly as
it is pulled low by the NMOS1X device, the input to the
Fault Sense circuitry will be latched to high state and
turns on the LED. When VO goes below 2V, the
NMOS50X device turns on again, clamping the IGBT
gate firmly to VSS. The Fault Sense signal will remain
latched in the high state until the LED of the gate driver
circuitry turns off.
7. Dual Supply Operation – Negative Bias at Vss
3. Desaturation Protection, FAULT Output
The IGBT’s off-state noise immunity can be enhanced by
providing a negative gate to emitter bias when the IGBT
is in the off-state. This static off-state bias can be
supplied by connecting a separate negative voltage
source between the VE (pin 16) and VSS (pin 9 &10).
Figure 51 illustrates the two distinct grounds. The
primary ground reference is the IGBT’s emitter
connection - VE, pin 16. The under-voltage threshold and
desaturation voltage detection are referenced to the
IGBT’s emitter (VE) ground.
Desaturation detection protection ensures the protection
of the IGBT at short circuit by monitoring the collectoremitter voltage of the IGBT in the half bridge. When the
DESAT voltage goes up and reaches above the
threshold voltage, a short circuit condition is detected
and the driver output stage will execute a “soft” IGBT
turn-off and will be eventually driven low. This sequence
is illustrated in Figure 53. The FAULT open-drain output
is triggered active low to report a desaturation error. It
could only be cleared by activating active low by the
external controller to the RESET input.
The recommended application circuit, Figure 50, shows
the interconnection of the VDD2 and VE supplies. The
IGBT’s gate to emitter voltage is the absolute value sum
of the VDD2 supply and the VSS reverse bias. The
negative voltage supply at VSS appears at the gate drive
input, VO, when the FOD8316 is in the low state. When
The DESAT fault detector should be disabled for a short
time period (blanking time) before the IGBT turns on to
allow the collector voltage to fall below DESAT threshold. This blanking period protects against false trigger of
the DESAT while the IGBT is turning on.
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
23
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
2. Gate Driver Output
Figure 50 shows the operation with a dual or split power
supply. The Vss supply provides the negative gate bias,
and VDD2 + VSS supplies power to the output IC. The
VSS and VDD2 supplies require three power supply
bypass capacitors. These capacitors provide the low
equivalent series resistant (ESR) paths for the
instantaneous gate charging and discharging currents.
VIN–
VIN+
VO
Figure 52. Input/Output Relationship
Normal
Operation
VIN–
VIN+
RESET
Fault Condition
Reset
0V
5V
0V
Blanking
Time
7V
VDESAT
VO
FAULT
Figure 53. Timing Relationship Among Desatuation Voltage (DESAT), Fault Output (FAULT) and
Fault Reset Input (RESET)
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
24
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Selecting capacitors with low ESR will optimize the
available output current. C3 is a low ESR 1812 style,
10µF, multilayer ceramic capacitor. This capacitor is the
primary filter for the Vss and VDD2 supplies. C1 and C2
are also low ESR capacitors. They provide the primary
gate charge and discharge paths. The Schottky diode,
D1, is connected between VE and VSS to protect against
a reverse voltage greater than 0.5V.
the input drives the output high, the output voltage, VO,
will have the potential of the VDD2 and VSS.
5V
VIN+
0V
VUVLO+
VUVLO–
VDD2 – VE
VO
Figure 54. Under Voltage Lockout (UVLO) for Output Side
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
25
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
VIN–
Part Number
Package
Packing Method
FOD8316
SO 16-Pin
Tube (50 units per tube)
FOD8316R2
SO 16-Pin
Tape and Reel (750 units per reel)
FOD8316V
SO 16-Pin, DIN EN/IEC 60747-5-5 option
Tube (50 units per tube)
FOD8316R2V
SO 16-Pin, DIN EN/IEC 60747-5-5 option
Tape and reel (750 units per reel)
All packages are lead free per JEDEC: J-STD-020B standard.
Marking Information
1
2
3
8316 V
D X YY KK
4
6
5
J
8
7
Definitions
1
Fairchild logo
2
Device number, e.g., ‘8316’ for FOD8316
3
DIN EN/IEC60747-5-5 Option (only appears on
component ordered with this option)
4
Plant code, e.g., ‘D’
5
Last digit year code, e.g., ‘B’ for 2011
6
Two digit work week ranging from ‘01’ to ‘53’
7
Lot traceability code
8
Package assembly code, J
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
26
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Ordering Information
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Reflow Profile
Temperature (°C)
TP
260
240
TL
220
200
180
160
140
120
100
80
60
40
20
0
Max. Ramp-up Rate = 3°C/S
Max. Ramp-down Rate = 6°C/S
tP
Tsmax
tL
Preheat Area
Tsmin
ts
120
240
360
Time 25°C to Peak
Time (seconds)
Profile Freature
Pb-Free Assembly Profile
Temperature Min. (Tsmin)
150°C
Temperature Max. (Tsmax)
200°C
Time (tS) from (Tsmin to Tsmax)
60–120 seconds
Ramp-up Rate (tL to tP)
3°C/second max.
Liquidous Temperature (TL)
217°C
Time (tL) Maintained Above (TL)
60–150 seconds
Peak Body Package Temperature
260°C +0°C / –5°C
Time (tP) within 5°C of 260°C
30 seconds
Ramp-down Rate (TP to TL)
6°C/second max.
Time 25°C to Peak Temperature
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
8 minutes max.
www.fairchildsemi.com
27
0.406 ± 0.10
(10.312 ± 0.254)
RECOMMENDED LAND PATTERN
16 15 14 13 12 11 10
9
0.295 ± 0.010
(7.493 ± 0.254)
1
2
3
4
5
0.050
(1.27)
0.138 ± 0.005
(3.505 ± 0.127)
6
7
0.458 (11.63)
0.085
(2.16)
8
0.025
(0.64)
0.018
(0.457)
0.050
(1.27)
0.345 ± 0.100
(8.763 ± 0.254)
9°
All leads to be
coplanar ± 0.002
0.8°
0.025 Min.
Dimensions in inches (millimeters)
0.408 ± 0.010
(10.363 ± 0.254)
0.008 ± 0.003
(0.203 ± 0.076)
Standoff
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0
www.fairchildsemi.com
28
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Package Dimensions
FOD8316 — 2.5A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
29
www.fairchildsemi.com
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.0