STMICROELECTRONICS L5951

L5951
TRIPLE OUTPUT MULTIFUNCTION VOLTAGE REGULATOR
FOR CAR RADIO WITH IDR/CLASS 2 INTERFACE
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3 VOLTAGE REGULATORS:
3.3V (100mA) STANDBY REGULATOR
5V (100mA) STANDBY REGULATOR
7.8V (100mA)
OUT OF REGULATION DETECTION FOR 5VSTANDBY REGULATOR
WIDE OPERATING SUPPLY VOLTAGE
RANGE FROM 4.5V UP TO 26.5V FOR
TRANSIENT 34V
VERY LOW STANDBY QUIESCENT
CURRENT (<150µA)
INPUT TO OUTPUT SIGNAL TRANSFER
FUNCTION PROGRAMMABLE
LVS FUNCTION
TTL AND CMOS COMPATIBLE INPUTS
OUTPUT CURRENT LIMITATION
CONTROLLED OUTPUT SLOPE FOR LOW
EMI
OVERTEMPERATURE SHUT-DOWN
ABLE TO SURVIVE UNDER LOSS OF
SO24
ORDERING NUMBER: L5951
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GROUND OR BATTERY
ESD PROTECTED
DESCRIPTION
The L5951 is a monolithic triple regulator integrated
with a SAE J1850 Integrated Driver / Receiver realized in advanced Multipower-BCD technology. It is
intended to drive single wire J1850 communications,
and offer microcontroller power and power management for automotive or industrial applications.
BLOCK DIAGRAM
VBAT
SUPPLY
SELECTOR
3V
STANDBY
REG1
5V
STANDBY
REG2
LVS
BANDGAP
REFERENCE
RESET
RESET
EN
ENABLE/
PROTECTION
LOGIC
SLEEP
7.8V
REG3
BUS DRIVER
WAVESHAPING
FILTER
TX
4X
4XEN AND
LOOPBACK
LOOP
RX
BUS
LOSS
OF GND
PROTECTION
DIGITAL OUTPUT
DRIVER
LOAD
GND
D99AU991
January 2001
1/13
L5951
1
FUNCTIONAL DESCRIPTION
1.1 General Features
The L5951 is an integrated circuit which provides a J1850 physical layer as well three voltage regulators. The
L5951 was developed to provide the power and Class 2/IDR interface for a microcontroller.
1.2 REG1 Output Voltage
The REG1 regulator output is equal to 3.3V. The 3.3V regulator is non low drop out and can handle currents up
to 100mA with short citcuit limit of 280mA.
1.3 REG2 Output Voltage
The REG2 regulator output is equal to 5V and can handle currents up to 100mA with short citcuit limit of 280mA.
The output stage of the 5V regulator is low dropout.
1.4 REG3 Output Voltage
The REG3 regulator output is equal to 7.8V and can handle currents up to 100mA with short citcuit limit of
280mA. The output stage of the 7.8V regulator is low dropout. REG3 regulator is controlled by the EN (enable)
pin of the IC. REG3 can be turned on and off by toggling the EN pin. A logic "1" on the EN pin enables REG3,
while a logic "0" on the EN pin disables REG3. The maximum voltage when REG3 is off must be less than 0.2V.
Sleep* Input - The Class 2 transmitter can be turned on and turned off by the Sleep* pin. Once the voltage level
is above 2VDC, the transmitter is enabled. If the Sleep* pin drops below 0.8VDC, and EN is "0" the transceiver
goes into a low power mode. In low power mode, REG3 and the transceiver are disabled. The L5951 will still
receive messages and send them to the microcontroller out of the RX pin.
* denotes active low
LVS input - Reg1 and Reg2 are supplied by Vbat pin. The device could then dissipate a lot of power, causing
thermal shutdown at high voltage. For this reason a secondary low voltage supply (LVS) can be used to reduce
power dissipation.
Reset* Output - The L5951 has low voltage or no voltage circuitry that is a warning to the microcontroller. If
REG2 drops 0.3VDC below its normal operating voltage, the Reset* pin will go to a logic "0". Between the voltage levels of 4.65VDC (min) and 5.10VDC (max) on REG2, a reset will occur. There is a hysterisis of 50mV on
the Reset* pin.
* denotes active low
Low Input Voltage Operation - If battery voltage level drops below 7.0V, the outputs are to remain alive and
ready for the return of normal voltage battery levels. The L5951 will be able to retrieve data off the BUS and
send it to the micrprocessor when the supply voltage is as low as 4.9V. The regulators should stay the same
voltage as the battery voltage down to 7.0V minus operating headroom for the 7.8V regulator. BUS VOH,min are
not guaranteed over all conditions below VBAT = 9.0V.
Waveshaping - Messages sent by the microcontroller to the transceiver are routed to a waveshaping circuit.
The digital signal is rounded at the switching points in order to reduce EMI emissions. A second order function,
I = C*dV/dt, is used to control the rise and fall times of the transmission. The rise and fall times are controlled
by an external resistor Rext . The waveshaping circuit can be enabled and disabled by the 4X pin. A logic "1"
will disable the waveshape circuit and a logic "0" will enable the waveshape circuit. In 4X mode, the speed of
the BUS is increased by a factor of four. Any signal coming from the microcontroller and going to the BUS must
be waveshaped. If loopback(LOOP) is enabled, the signal coming from the micro through the TX pin is routed
to the RX pin back to the micro with or without it being waveshaped. A logic "1" enables loopback and a logic"0"
disables loopback.
Nodes - The transmitter provides a wave-shaped 0 to 7.7 VDC waveform on the BUS output. It also receives
waveforms and transmits a digital level signal back to a logic IC. The transmitter can drive up to 32 remote transceivers. These remote nodes may be at ground potentials that are ±2 VDC, with respect to the assembly. Under
this condition, waveshaping will only be maintained during 3 of the 4 corners. The L5951 is a remote node on
the Class 2/IDR Bus. Each remote transceiver has a 470 + 10% pF capacitor on its output for EMI suppression,
2/13
L5951
as well as a 10.6 kW + 5% pull down resistor to ground. The main node has a 3,300 + 10% pF capacitor on its
output for EMI suppression, as well as a 1.5 kΩ + 5% pull down resistor to ground. With more than 26 nodes
there is no primary node , all nodes will have the 470 ±10% pF capacitor and the 10.6kΩ ±5% pull down resistor.
No matter how many remote nodes are on the Class 2/IDR Bus, the RC of the Class 2/IDR Bus is maintained
at approximately 5ms. The minimum and maximum load on the Class 2/IDR Bus is given below :
Capacitance
Resistance to Ground
Minimum Nodes
(3.33 · .9) + (.47 · .9) = 3.39 nF
(1.5 · 1.05) || (10.6 · 1.05) = 1.38 kΩ
Maximum Nodes
(3.3 · 1.1) + 25·(0.47 · 1.1) = 16.55 nF (1.5 · 0.95) || (10.6 · 0.95) / 25 = 314Ω
1.5 Protection
The L5951 can survive under the following conditions: shorting the outputs to BAT and GND, loss of BAT, loss
of IC GND, double battery(+26.5V), 4000V ESD, 34V load dump. L5951 will not handle a reverse battery condition. External components must be implemented for reverse battery protection.
Thermal Shutdown: thermal shutdown is broken down into two areas; V1 and V2 ouputs, and the other is V3
output and the Class 2 Bus Driver. V1 and V2 outputs shutdown at 160°C and returns to normal operation at
130°C. The V3 output and Class 2 Bus Driver shutdown at 150°C and return to normal operation at 120°C.
Current Limiting: each voltage regulator will contain its own current protection, and the maximum allowable current for all three regulators is 280mA.
Short Circuit: If the outputs are short circuited, the IC will begin current limiting and eventually the thermal shutdown will kick in. Current limiting will not disable the outputs.
Overvoltage: The IC will not operate if the BAT voltage reaches 30V or above. V1 and V2 will not be shutdown,
but all other outputs will not operate.
Loss of Ground & Loss of Battery Connection: in this conditions a very small leakage on BUS is generated.
1.6 Protocol Description
The L5951 uses a Variable Pulse Width (VPW) modulated protocol. One frame consists of an entire message
not containing more than 12 bytes. The first bit of each byte will be the most significant bit (MSB). A transmitted
message begins with a SOF signal and ends with the EOF signal.
The data to be transmitted has to be in a specific format as follows:
idle,SOF,DATA, CRC, EOD, NB, IFR, EOF, IFS, idle
Definitions below:
idle:
Logic level low on communication bus
SOF:
Start of Frame
DATA:
Data Bytes
CRC:
Cyclic Redundancy Check Error Detection Byte
EOD:
End of DATA(only when IFR is used)
NB:
Normalization Bit
IFR:
In-Frame Response Byte(s)
EOF:
End of Frame
IFS:
Inter-Frame Separation
BRK:
Break(can occur on network at any time)
Idle - Logic level low on bus any time after IFS.
Start of Frame (SOF) - The SOF signals the receiver that a new frame is beginning. SOF signal is a logic level
3/13
L5951
high pulse identified by a pulse width of about t = 200µs.
DATA - Total number of bytes that can be transmitted (from SOF to EOF) is 12 bytes.
Cyclic Redundancy Check (CRC) - A method for determining if the message received is the same as the message transmitted. If an invalid CRC number is detected, then an error will be detected. The SOF signal is not
used to determine the CRC. All bits in the CRC are initially "ones" to avoid confusion with a data stream that are
all "zeros".
End of Data (EOD) - Used to signal the receiver about the end of data transmission. If there is a IRF signal, the
sender of the frame will expect one or more bytes in the IFR following the EOD. If there is no IFR used, then the
bus would stay in a logic level low state resulting in a EOF. EOD signal is recognized by a logic level low pulse
for a duration of about 200µs.
Normalization Bit (NB) - The sole reason for the NB is to define the start of the in-frame response. The first bit
the the IFR is passive, therefore it is necessary to have a signal that follows EOD. There are two forms to the
NB. First of all, the NB is a logic level high pulse. The two forms are distinguished by thier pulse widths. The first
form has a pulse width of about 64µs and indicates if the IFR contains a CRC or not. The second form has a
longer pulse width of about 128µs and also indicates if there is a CRC in the IFR or not. The manufacturer can
manipulate the NB to any of the two methods.
In-Frame Response (IFR) - Response bytes are sent by the receiver of the transmission and start after the
EOD. If the IFR stays at a logic level low for a period of time then the frame must be considered to be complete.
IFR bytes can be used to send a signal back to the originator indicating the correct CRC number to confirm the
correct message was sent.
End of Frame (EOF) - Indicates the end of a frame. Once the last byte is transmitted, the bus will be in a logic
level low state for a period of time indicating the end of the frame. EOF signal is recognized by a low pulse for
a width of about 280µs.
Inter-Frame Separation (IFS) - IFS is used to synchronize the receivers at various nodes.
ABSOLUTE MAXIMUM RATINGS
Symbol
VS
VDIAG
VIN
VOUT
Parameter
Value
Unit
DC Operating Supply Voltage
-0.6 to 26.5
V
Diagnostic output voltage
-0.6 to 5.5
V
Input Control Voltage (EN, Sleep, 4X, Loop, TX)
-0.6 to 5.5
V
Output Control Voltage (Reset *)
-0.3 to 5.5
V
VS
Peak Supply Voltage t = 50ms
34
V
Top
Operating Temperature Range
-40 to 85
°C
Tstg
Storage Temperature Range
-40 to 150
°C
Value
Unit
50
°C/W
* denotes active low
THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal resistance junction to ambient (*)
(*) With 6cm2 on board heat sink area.
4/13
L5951
PIN CONNECTION
REG1
1
24
LVS
RESET
2
23
REG2
REXT
3
22
REG3
GND_REG
4
21
BAT
GND_TX
5
20
GND_TX
GND_TX
6
19
GND_TX
GND_TX
7
18
GND_TX
GND_TX
8
17
GND_TX
SLEEP
9
16
BUS
EN
10
15
LOAD
4X
11
14
TX
LOOP
12
13
RX
D99AU992
PIN FUNCTIONS
N.
Name
Function
1
REG1
2
Reset *
3
Rext
4
GND_REG
,6,7,8,17,
18,19,20
GND_TX
9
Sleep *
Transceiver Enable Input
0
EN
Enable for Regulator #3
11
4X
4XBus mode (41.6K Baud)
12
LOOP
13
RX
Serial Data Output to mC
14
TX
Serial Data Input from mC
15
Load
External Pull Down to Gnd
16
Bus
Bus Output to Vehicle
21
Bat
Battery Supply
22
REG3
Regulator #3
23
REG2
Regulator #2
24
LVS
Regulator #1
Reset Output to µC
Waveshaping Resistor
Regulator Ground
Transceiver Ground
Loopback Enable
Low Voltage Supply
*denotes active low for Sleep and Reset.
5/13
L5951
ELECTRICAL CHARACTERISTICS
(Tamb = 25°C, VBAT = 14.4V unless otherwise specified. Standard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA)
Symbol
Iq,ST-BY
Parameter
Standby Quiescent Current
Maximum QuiescentCurrent VBAT
Maximum QuiescentCurrent LVS
EN Switch Input Current
VENL, ENH EN Input Threshold Voltage
VRES, L
VRES
Test Condition
Min.
Typ.
Max.
Unit
350
µA
110
µA
VBAT = 14V, IREG1 = 100mA,
IREG2 = 100mA, IREG3 = 100mA,
IBUS = 30mA
LVS = 0V
LVS = 10V
10
10.5
mA
mA
VBAT = 14V, IREG1 = 100mA,
IREG2 = 100mA, IREG3 = 100mA,
IBUS = 30mA LVS = 10V
750
µA
0
0
µA
µA
EN, Sleep* = 0V, VBAT = 14V,
IREG2 = 50mA, IREG1 = 50mA
EN, Sleep* = 0V, VBAT = 14V,
IREG2 = 500µA, IREG1 = 250mA
VBAT = 14V, EN ≥ 2V
VBAT = 14V, EN ≥ 0.8V
VBAT = 14V, VIL
VBAT = 14V, VIH
2
Reset* Output Low Voltage
Set VBATso VREG2 drops 0.30V
0
Reset* Output Voltage Threshold
Decrease VBATso VREG2 drops
until Reset* drops
VRES, HYS Reset Threshold Hysteresis
0.02
0.8
V
0.4
V
VREG2
- 0.20
V
50
mV
(*) Denotes active low.
3.3V/100mA DC Characteristics for Regulator Output 1
VREG1
Output Voltage
IREG1 =100mA
∆Vline
Line Regulation
∆Vload
Load Regulation
VDROPOUT Dropout Voltage (Measure VBAT VREG1 when VREG1 drops 0.1V)
Ilim1
SVR1
3.14
3.3
3.46
V
7V ≤ VBAT ≤ 26V
(Measure ∆VREG1 Across VBAT
Range)
7
15
mV
0.5mA ≤ IREG1 ≤ 100mA
(Measure ∆VREG1 Across VLOAD
Range)
8
50
mV
1
0.12
2.2
1.5
V
V
IREG1 = 100mA
IREG1 = 5mA
Current Limit
Reg1 Supply Voltage Rejection
IREG1 = IREG2 = IREG3 = 50mA
f = 20 to 20kHz
VBAT = 14Vdc, 1Vac,pp
200
mA
45
dB
5V/100mA Regulator Output 2
VREG2
Output Voltage
IREG2 =100mA
∆Vline
Line Regulation
7V ≤ VBAT ≤ 26V
(Measure ∆VREG2 Across VBAT
Range)
6/13
4.75
5
5.25
V
6
40
mV
L5951
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25°C, VBAT = 14.4V unless otherwise specified. Standard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA)
Symbol
∆Vload
Parameter
Load Regulation
VDROPOUT Dropout Voltage (Measure VBAT VREG2 when VREG2 drops 0.1V)
Ilim2
SVR2
Test Condition
Min.
Typ.
Max.
Unit
0.5mA ≤ IREG2 ≤ 100mA
(Measure ∆VREG2 Across VLOAD
Range)
14
100
mV
IREG2 =100mA
IREG2 =5mA
450
22
mV
mV
200
mA
45
dB
Current Limit
Reg2 Supply Voltage Rejection
IREG1 = IREG2 = IREG3 = 50mA
f = 20 to 20kHz
VBAT = 14Vdc, 1Vac,pp
7.8V/100mA Regulator Output 3
VREG3
Output Voltage
IREG3 =100mA - 8.8V ≤ VBAT ≤
Range
DVline
Line Regulation
DVload
Load Regulation
VDROPOUT Dropout Voltage
(Measure VBAT - VREG3 when
VREG3 drops 0.1V)
Ilim3
SVR3
7.60
8
V
8.8V ≤ VBAT ≤ 26V
(Measure ∆VREG3 Across VBAT
Range)
50
mV
5mA ≤ IREG3 ≤ 100mA
(Measure ∆VREG3 Across VLOAD
Range)
50
mV
IREG3 = 100mA
IREG3 = 5mA
Current Limit
Reg3 Supply Voltage Rejection
IREG1 = IREG2 = IREG3 = 50mA
f = 20 to 20kHz
VBAT = 14Vdc, 1Vac,pp
7.8
0.5
0.04
V
V
200
mA
45
dB
DC Characteristics for Class 2 Transceiver
Standard Loads: I REG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA
BUSih
BUSil
BUS Guaranteed
Input Voltages
Verify RX > 3 VDC
Verify RX < 3 VDC
BUSHyst
BUS Hysteresis
BUSItoh - BUShhtol
BUSov
BUS Output Voltage
TX = 5 VDC,
BUS = 257 to 1380Ω to gnd
VBAT - 8.2 to 16 VDC
VBAT - 6.0 to 8.2 VDC
TX = 0V
4.25
3.7
3.50
V
V
0.15
V
7.2
5
V
V
IBUSshort
BUS Short Circuit Current
TX = 5VDC
BUS = -2 to 4.8VDC
170
mA
IBUSleak
BUS Leakage Current
BUS = -2 to 0 VDC
BUS = 0 to VBAT
0
0
mA
mA
0.045
V
LOADON Load Output
I LOAD = 6mA
7/13
L5951
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25°C, VBAT = 14.4V unless otherwise specified. Standard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
LOADDio Load Output (Unpowered)
V BAT = 0V, ILOAD = 6mA
0.7
V
IBUSloss BUS & LOADCurrent during loss
ILOADloss of assembly VBAT or GND
IVBAT = 0mA,
BUS = -18 to 9VDC
LOAD = -18 to 0 VDC
11
39
µA
µA
TXVIL
TXVIH
TX Input Voltage
ITXVIL
ITXVIH
TX Input Current
TX = 5VDC
TX = 0VDC
110
0
µA
µA
4Trip1
4Trip2
4X Input Trip Point Voltages
Normal Mode
4X Mode
1.4
V
I4Xvih
I4Xvil
4X Input Current
4X = 5 VDC
4X = 0 VDC
0
0
µA
µA
LTrip1
LTrip2
LOOP Input Trip Point Voltages
Normal Mode
Loopback Mode
ILvih
ILvil
LOOP Input Current
LOOP = 5VDC
LOOP = 0VDC
VRXhigh
RX Output Voltage, High
VRXlow
IRX
0.8
2
0.8
2
V
V
V
V
0
µA
BUS = 7V, IRX = -200µA
4.85
V
RX Output Voltage, Low
BUS = 0V, IRX = 1.6mA
0.2
V
RX Output Current
RX = high (Short circuit protection
limits)
5
mA
Sleep* Input Voltage
TX = 5VDC
Verify BUS > 3.725
Verify BUS < 4.025
Sleep* VIH
Sleep*VIL
ISleepvih
ISleepvil
Verify BUS < 3.875VDC
Verify BUS > 3.875VDC
Sleep* Input Current
2
0.8
V
V
0.2
0
µA
µA
TX = 7.812Hz square wave
See Figure 1
Min and Max Loaded BUS
15
µs
TX = 7.812Hz square wave
See Figure 1
Min and Max Loaded BUS
14
µs
TX = 7.812Hz square wave
See Figure 2
Load BUS with 3.300pF and
1.38kΩ
Meas. @ 1.5V levels
Meas. @ 6.25V levels
77
48
µs
µs
Sleep* = 5VDC
Sleep* = 0VDC
* Denotes active low for Sleep and Reset.
AC Characteristics for Class 2 Transceiver
Standard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA
BUSLTOH BUS Voltage Rise Times
BUSHTOL BUS Voltage Fall Times
tWbus
8/13
BUS Pulse Width Distortion
L5951
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25°C, VBAT = 14.4V unless otherwise specified. Standard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA)
Symbol
V1
V2
BUSDLY
Parameter
Test Condition
Typ.
Max.
Unit
Spectral Content Limit
(Measure spectral peak from
0.53MHz to 1.6MHz)
VBAT = 9V to 16V, no ground
offset, 0.53 ≤ f ≤ 1MHz.
VBAT = 9V to 16V, no ground
offset, 1 ≤ f ≤ 1.67MHz.
100
µV
80
µV
Propagation Delay
Measure Delay Between TX Trip
Point and RX Trip Point
16
µs
TX to BUS Delay
Measure from 2.5V on TX to
3.875V on BUS
4X Mode
Normal Mode
3.5
14.5
µs
µs
See Figure 4
Measured from BUS Threshold
Voltage
1.5
1.9
µs
µs
TX4XDLY
TXNormDLY
RXLTOHdly RX Output Delay Time
RXHTOLdly
2
Min.
RXLTOH
RXHTOL
RX Output Transition Time
Load RX with 50pF to Ground
See Figure 5
170
70
ns
ns
RXLTOH
RXHTOL
RX Output Transition Time During
Sleep State
Load RX with 50pF to Ground
See Figure 5, Sleep* = 0VDC
170
70
ns
ns
BUS TIMING DIAGRAM
Figure 1. BUS Rise and Fall Times
5V
TX
64µsec
0V
6.25V
6.25V
BUS
1.5V
trise
tfall
1.5V
D99AU993
Figure 2. BUS Pulse Width Distortion
5V
TX
64µsec
0V
6.25V
BUS 3.875V
1.5V
>35µsec
64µsec
<93µsec
D99AU994
9/13
L5951
Figure 3. BUS Output Voltage
D99AU995
V
8
BUS
7
6
5
4
0
20
40
60
80
100
time(µs)
Figure 4. BUS to RX Delay Times
thtol
tltoh
90%
90%
RX
10%
10%
D99AU997
3
TYPICAL APPLICATION CURCUIT
Figure 5. Application Circui
BAT
VBATT
C10
470µF
R1
47K
LOAD/BUS IN
LVS
10V
C9
R2
10.7K 470pF
EN
EN
C1
0.1µF
BUS/BUS OUT
3.3VSB
REG1
REG2
C8
0.1µF
SLEEP
REG3
5VSB
7.8VSW
C7
10µF
4X
FROM
LOGIC
LOOP
REXT
TX
R3
68K
RX
TO
LOGIC
RESET
C5
10µF
GND
D99AU998mod
Note: ESR of output capacitors should be between 0.2Ω and 5.0Ω.
10/13
C3
10µF
L5951
4
TYPICAL RESET CIRCUIT
Figure 6. Reset Circuit
5VSB
R
RESET
to micro
C
D99AU999
1) 10kΩ is the minimum resistance for R.
2) The value of C depends on timing needed
External Components Parts List for Standard Application
Quantity
Application Description
Part Description
Note Number
5
C1, C8
CAP - 0.1µF, 25V
1
3
C3, C5, C7
CAP - Tant 10µF, 10V
2
1
R1
RES-47k, 1/16W 5%
3
1
R2
RES - 10.7k, 1/16W, 1%
4
1
R3
RES - 68k, 1/16W, 1%
5
1
C9
CAP - 25V, 470pF
6
1
C10
CAP - 50V, 470pF
1
Notes: (Reasons for This Component Choice)
1. Noise Suppression
2. Output Compensation
3. Pull Down Resistor
4. Bus Resistor
5. Bus Slew Rate Control
6. Proper Bus Capacitance
11/13
L5951
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
A2
2.55
0.100
B
0.33
0.51
0.013
0.0200
C
0.23
0.32
0.009
0.013
D
15.20
15.60
0.598
0.614
E
7.40
7.60
0.291
0.299
e
1.27
0,050
H
10.0
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
k
OUTLINE AND
MECHANICAL DATA
0° (min.), 8° (max.)
SO24
L
0.40
1.27
0.016
0.050
0.10mm
B
e
A
A2
h x 45˚
A1
K
A1
L
.004
H
Seating Plane
D
13
1
12
E
24
SO24
12/13
C
L5951
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