L6226 DMOS DUAL FULL BRIDGE DRIVER ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ OPERATING SUPPLY VOLTAGE FROM 8 TO 52V 2.8A OUTPUT PEAK CURRENT (1.4A DC) RDS(ON) 0.73Ω TYP. VALUE @ Tj = 25 °C OPERATING FREQUENCY UP TO 100KHz PROGRAMMABLE HIGH SIDE OVERCURRENT DETECTION AND PROTECTION DIAGNOSTIC OUTPUT PARALLELED OPERATION CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN UNDER VOLTAGE LOCKOUT INTEGRATED FAST FREE WHEELING DIODES TYPICAL APPLICATIONS ■ BIPOLAR STEPPER MOTOR ■ DUAL OR QUAD DC MOTOR DESCRIPTION The L6226 is a DMOS Dual Full Bridge designed for motor control applications, realized in MultiPower- PowerDIP24 (20+2+2) PowerSO36 SO24 (20+2+2) ORDERING NUMBERS: L6226N (PowerDIP24) L6226PD (PowerSO36) L6226D (SO24) BCD technology, which combines isolated DMOS Power Transistors with CMOS and bipolar circuits on the same chip. Available in PowerDIP24 (20+2+2), PowerSO36 and SO24 (20+2+2) packages, the L6226 features thermal shutdown and a non-dissipative overcurrent detection on the high side Power MOSFETs plus a diagnostic output that can be easily used to implement the overcurrent protection. BLOCK DIAGRAM VBOOT VBOOT VBOOT VCP VSA VBOOT CHARGE PUMP PROGCLA OCDA OCDA OVER CURRENT DETECTION 10V THERMAL PROTECTION ENA OUT1A OUT2A 10V GATE LOGIC IN1A SENSEA IN2A VOLTAGE REGULATOR 10V 5V BRIDGE A OCDB OCDB OVER CURRENT DETECTION VSB PROGCLB ENB OUT1B OUT2B GATE LOGIC SENSEB IN1B IN2B BRIDGE B D99IN1088A September 2003 1/22 L6226 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Test conditions Value Unit Supply Voltage VSA = VSB = VS 60 V Differential Voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB VSA = VSB = VS = 60V; VSENSEA = VSENSEB = GND 60 V OCDA,OCDB OCD pins Voltage Range -0.3 to +10 V PROGCLA, PROGCLB -0.3 to +7 V VS + 10 V VS VOD VBOOT PROGCL pins Voltage Range Bootstrap Peak Voltage VSA = VSB = VS VIN,VEN Input and Enable Voltage Range -0.3 to +7 V VSENSEA, VSENSEB Voltage Range at pins SENSEA and SENSEB -1 to +4 V IS(peak) Pulsed Supply Current (for each VS pin), internally limited by the overcurrent protection VSA = VSB = VS; tPULSE < 1ms 3.55 A RMS Supply Current (for each VS pin) VSA = VSB = VS 2.8 A -40 to 150 °C IS Tstg, TOP Storage and Operating Temperature Range RECOMMENDED OPERATING CONDITIONS Symbol Parameter Test Conditions Supply Voltage VSA = VSB = VS VOD Differential Voltage Between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB VSA = VSB = VS; VSENSEA = VSENSEB VSENSEA, VSENSEB Voltage Range at pins SENSEA and SENSEB (pulsed tW < trr) (DC) VS IOUT 2/22 MIN MAX Unit 8 52 V 52 V 6 1 V V 1.4 A +125 °C 100 KHz -6 -1 RMS Output Current Tj Operating Junction Temperature fsw Switching Frequency -25 L6226 THERMAL DATA Symbol Description Rth-j-pins MaximumThermal Resistance Junction-Pins Rth-j-case Maximum Thermal Resistance Junction-Case PowerDIP24 SO24 PowerSO36 Unit 19 15 - °C/W - - 2 °C/W 44 52 - °C/W Rth-j-amb1 MaximumThermal Resistance Junction-Ambient Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient 2 - - 36 °C/W Rth-j-amb1 MaximumThermal Resistance Junction-Ambient 3 - - 16 °C/W Rth-j-amb2 Maximum Thermal Resistance Junction-Ambient 4 59 78 63 °C/W (1) (2) (3) (4) 1 Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of 35 µm). Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm). Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm), 16 via holes and a ground layer. Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board. PIN CONNECTIONS (Top View) IN1A 1 24 GND 1 36 GND N.C. 2 35 N.C. N.C. 3 34 N.C. VSA 4 33 VSB OUT2A 5 32 OUT2B N.C. 6 31 N.C. VCP 7 30 VBOOT ENA 8 29 ENB PROGCLA 9 28 PROGCLB PROGCLA IN2A 2 23 ENA SENSEA 3 22 VCP OCDA 4 21 OUT2A OUT1A 5 20 VSA GND 6 19 GND GND 7 18 GND OUT1B 8 17 VSB OCDB 9 16 OUT2B SENSEB 10 15 VBOOT IN1B 11 14 IN2B 12 13 IN1A 10 27 IN2B IN2A 11 26 IN1B SENSEA 12 25 SENSEB OCDA 13 24 OCDB N.C. 14 23 N.C. OUT1A 15 22 OUT1B ENB N.C. 16 21 N.C. PROGCLB N.C. 17 20 N.C. GND 18 19 GND D99IN1089A D99IN1090A PowerDIP24/SO24 PowerSO36(5) (5) The slug is internally connected to pins 1,18,19 and 36 (GND pins). 3/22 L6226 PIN DESCRIPTION PACKAGE SO24/ PowerDIP24 PowerSO36 PIN # PIN # 1 Name Type 10 IN1A Logic input Bridge A Logic Input 1. 2 11 IN2A Logic input Bridge A Logic Input 2. 3 12 SENSEA Power Supply Bridge A Source Pin. This pin must be connected to Power Ground directly or through a sensing power resistor. 4 13 OCDA Open Drain Output Bridge A Overcurrent Detection and thermal protection pin. An internal open drain transistor pulls to GND when overcurrent on bridge A is detected or in case of thermal protection. 5 15 OUT1A Power Output 6, 7, 18, 19 1, 18, 19, 36 GND GND 8 22 OUT1B Power Output 9 24 OCDB Open Drain Output Bridge B Overcurrent Detection and thermal protection pin. An internal open drain transistor pulls to GND when overcurrent on bridge B is detected or in case of thermal protection. 10 25 SENSEB Power Supply Bridge B Source Pin. This pin must be connected to Power Ground directly or through a sensing power resistor. 11 26 IN1B Logic Input Bridge B Input 1 12 27 IN2B Logic Input Bridge B Input 2 13 28 PROGCLB R Pin Bridge B Overcurrent Level Programming. A resistor connected between this pin and Ground sets the programmable current limiting value for the bridge B. By connecting this pin to Ground the maximum current is set. This pin cannot be left non-connected. 14 29 ENB Logic Input Bridge B Enable. LOW logic level switches OFF all Power MOSFETs of Bridge B. If not used, it has to be connected to +5V. 15 30 VBOOT Supply Voltage 16 32 OUT2B Power Output Bridge B Output 2. 17 33 VSB Power Supply Bridge B Power Supply Voltage. It must be connected to the supply voltage together with pin VSA. 20 4 VSA Power Supply Bridge A Power Supply Voltage. It must be connected to the supply voltage together with pin VSB. 21 5 OUT2A Power Output Bridge A Output 2. 4/22 Function Bridge A Output 1. Signal Ground terminals. In Power DIP and SO packages, these pins are also used for heat dissipation toward the PCB. Bridge B Output 1. Bootstrap Voltage needed for driving the upper Power MOSFETs of both Bridge A and Bridge B. L6226 PIN DESCRIPTION (continued) PACKAGE SO24/ PowerDIP24 PowerSO36 PIN # PIN # 22 Name Type Function 7 VCP Output 23 8 ENA Logic Input Bridge A Enable. LOW logic level switches OFF all Power MOSFETs of Bridge A. If not used, it has to be connected to +5V. 24 9 PROGCLA R Pin Bridge A Overcurrent Level Programming. A resistor connected between this pin and Ground sets the programmable current limiting value for the bridge A. By connecting this pin to Ground the maximum current is set. This pin cannot be left non-connected. Charge Pump Oscillator Output. ELECTRICAL CHARACTERISTICS (Tamb = 25 °C, Vs = 48V, unless otherwise specified) Symbol Min Typ Max Unit VSth(ON) Turn-on Threshold 5.8 6.3 6.8 V VSth(OFF) Turn-off Threshold 5 5.5 6 V 5 10 mA IS Tj(OFF) Parameter Quiescent Supply Current Test Conditions All Bridges OFF; Tj = -25°C to 125°C (6) Thermal Shutdown Temperature °C 165 Output DMOS Transistors RDS(ON) IDSS High-Side + Low-Side Switch ON Tj = 25 °C Resistance Tj =125 °C (6) Leakage Current 1.47 1.69 Ω 2.35 2.70 Ω 2 mA EN = Low; OUT = VS EN = Low; OUT = GND -0.3 mA Source Drain Diodes Forward ON Voltage ISD = 2.8A, EN = LOW 1.15 trr Reverse Recovery Time If = 1.4A 300 ns tfr Forward Recovery Time 200 ns VSD 1.3 V Logic Input VIL Low level logic input voltage -0.3 0.8 V VIH High level logic input voltage 2 7 V IIL Low Level Logic Input Current GND Logic Input Voltage IIH High Level Logic Input Current 7V Logic Input Voltage Vth(ON) Turn-on Input Threshold -10 µA 1.8 10 µA 2.0 V 5/22 L6226 ELECTRICAL CHARACTERISTICS (continued) (Tamb = 25 °C, Vs = 48V, unless otherwise specified) Symbol Parameter Vth(OFF) Turn-off Input Threshold Vth(HYS) Input Threshold Hysteresis Test Conditions Min Typ Max Unit 0.8 1.3 V 0.25 0.5 V Switching Characteristics tD(on)EN Enable to out turn ON delay time (8) ILOAD =1.4A, Resistive Load tD(on)IN Input to out turn ON delay time ILOAD =1.4A, Resistive Load (dead time included) Output rise time(8) ILOAD =1.4A, Resistive Load 40 tD(off)EN Enable to out turn OFF delay time (8) ILOAD =1.4A, Resistive Load 500 tD(off)IN Input to out turn OFF delay time ILOAD =1.4A, Resistive Load 500 Output Fall Time (8) ILOAD =1.4A, Resistive Load 40 tRISE tFALL tdt Dead Time Protection fCP Charge pump frequency 500 800 1.9 0.5 -25°C<Tj <125°C ns µs 250 ns 800 1000 ns 800 1000 ns 250 ns 1 µs 0.6 1 MHz 0.29 2.21 2.8 +10% +10% +30% A A A 60 Ω Over Current Detection Is over Input Supply Over Current DetectionThreshold -25°C<Tj <125 °C; RCL= 39 kΩ -25°C<Tj <125 °C; RCL= 5 kΩ -25°C<Tj <125 °C; RCL= GND ROPDR Open Drain ON Resistance I = 4mA 40 tOCD(ON) OCD Turn-on Delay Time (8) I = 4mA; CEN < 100pF 200 ns tOCD(OFF) OCD Turn-off Delay Time (8) I = 4mA; CEN < 100pF 100 ns (6) (7) (8) 6/22 Tested at 25°C in a restricted range and guaranteed by characterization. See Fig. 1. See Fig. 2. -10% -10% -30% L6226 Figure 1. Switching Characteristic Definition EN Vth(ON) Vth(OFF) t IOUT 90% 10% t D01IN1316 tFALL tD(OFF)EN tRISE tD(ON)EN Figure 2. Overcurrent Detection Timing Definition IOUT OCD Threshold t VOCD 90% 10% tOCD(ON) tOCD(OFF) D01IN1222 t 7/22 L6226 CIRCUIT DESCRIPTION POWER STAGES and CHARGE PUMP The L6226 integrates two independent Power MOS Full Bridges. Each Power MOS has an Rdson=0.73ohm (typical value @ 25°C), with intrinsic fast freewheeling diode. Cross conduction protection is achieved using a dead time (td = 1µs typical) between the switch off and switch on of two Power MOS in one leg of a bridge. Using N Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The Bootstrapped (Vboot) supply is obtained through an internal Oscillator and few external components to realize a charge pump circuit as shown in Figure 3. The oscillator output (VCP) is a square wave at 600kHz (typical) with 10V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table1. Table 1. Charge Pump External Components Values CBOOT 220nF CP 10nF RP 100Ω D1 1N4148 D2 1N4148 these pins. Two configurations are shown in Fig. 5 and Fig. 6. If driven by an open drain (collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Fig. 5. If the driver is a standard Push-Pull structure the resistor REN and the capacitor CEN are connected as shown in Fig. 6. The resistor REN should be chosen in the range from 2.2kΩ to 180KΩ. Recommended values for REN and CEN are respectively 100KΩ and 5.6nF. More information on selecting the values is found in the Overcurrent Protection section. Figure 4. Logic Inputs Internal Structure 5V ESD PROTECTION D01IN1329 Figure 5. ENA and ENB Pins Open Collector Driving OCDA or OCDB 5V 5V REN OPEN COLLECTOR OUTPUT CEN ENA or ENB D02IN1355 Figure 3. Charge Pump Circuit VS D1 Figure 6. ENA and ENB Pins Push-Pull Driving OCDA or OCDB CBOOT D2 5V RP PUSH-PULL OUTPUT CP REN ENA or ENB CEN VCP VBOOT VSA VSB D01IN1328 LOGIC INPUTS Pins IN1A, IN2A, IN1B, IN2B, ENA and ENB are TTL/ CMOS and uC compatible logic inputs. The internal structure is shown in Fig. 4. Typical value for turn-on and turn-off thresholds are respectively Vthon=1.8V and Vthoff = 1.3V. Pins ENA and ENB are commonly used to implement Overcurrent and Thermal protection by connecting them respectively to the outputs OCDA and OCDB, which are open-drain outputs. If that type of connection is chosen, some care needs to be taken in driving 8/22 D02IN1356 TRUTH TABLE INPUTS OUTPUTS EN IN1 IN2 OUT1 OUT2 L X X High Z High Z H L L GND GND H H L Vs GND H L H GND Vs H H H Vs Vs X High Z = Don't care = High Impedance Output L6226 NON-DISSIPATIVE OVERCURRENT DETECTION AND PROTECTION In addition to the PWM current control, an overcurrent detection circuit (OCD) is integrated. This circuit can be used to provides protection against a short circuit to ground or between two phases of the bridge as well as a roughly regulation of the load current. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Fig. 7 shows a simplified schematic of the overcurrent detection circuit for the Bridge A. Bridge B is provided of an analogous circuit. To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current reaches the detection threshold Isover the OCD comparator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down capability of 4mA connected to OCD pin is turned on. Fig. 8 shows the OCD operation. This signal can be used to regulate the output current simply by connecting the OCD pin to EN pin and adding an external R-C as shown in Fig.7. The off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. IREF and, therefore, the output current detection threshold are selectable by RCL value, following the equations: – Isover = 2.8A ±30% at -25°C < T j < 125°C if RCL = 0Ω (PROGCL connected to GND) 11050 – Isover = ---------------- ±10% at -25°C < T j < 125°C if 5KΩ < RC < 40kΩ R CL Fig. 9 shows the output current protection threshold versus RCL value in the range 5kΩ to 40kΩ. The Disable Time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN values and its magnitude is reported in Figure 10. The Delay Time tDELAY before turning off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 11. CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable Delay Time and the REN value should be chosen according to the desired Disable Time. The resistor REN should be chosen in the range from 2.2KΩ to 180KΩ. Recommended values for REN and CEN are respectively 100KΩ and 5.6nF that allow obtaining 200µs Disable Time. 9/22 L6226 Figure 7. Overcurrent Protection Simplified Schematic OUT1A VSA OUT2A POWER SENSE 1 cell HIGH SIDE DMOSs OF THE BRIDGE A I1A µC or LOGIC POWER DMOS n cells TO GATE LOGIC +5V RENA POWER DMOS n cells I1A / n I2A / n (I1A+I2A) / n IREF INTERNAL OPEN-DRAIN CENA OCDA POWER SENSE 1 cell + OCD COMPARATOR ENA I2A RDS(ON) 40Ω TYP. - 1.2V + OVER TEMPERATURE IREF PROGCLA, D02IN1354 RCLA. Figure 8. Overcurrent Protection Waveforms IOUT ISOVER VEN VDD Vth(ON) Vth(OFF) VEN(LOW) ON OCD OFF ON tDELAY BRIDGE tDISABLE OFF tOCD(ON) tEN(FALL) tOCD(OFF) tD(OFF)EN 10/22 tEN(RISE) tD(ON)EN D02IN1400 L6226 Figure 9. Output Current Protection Threshold versus RCL Value 2 .5 2 .2 5 2 1 .7 5 1 .5 1 .2 5 I SO V E R [A ] 1 0 .7 5 0 .5 0 .2 5 0 5k 10k 15k 20 k 2 5k R C L [Ω ] 30k 3 5k 40k Figure 10. tDISABLE versus C EN and REN (VDD = 5V). 1 . 10 R EN = 220 k Ω 3 R EN = 100 k Ω R EN = 47 k Ω R EN = 33 k Ω tDISABLE [µs] R EN = 10 k Ω 100 10 1 1 10 100 C E N [nF] 11/22 L6226 Figure 11. tDELAY versus CEN (VDD = 5V). tdelay [µs] 10 1 0.1 1 10 Cen [nF] 100 THERMAL PROTECTION In addition to the Ovecurrent Detection, the L6226 integrates a Thermal Protection for preventing the device destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switch-off when the junction temperature reaches 165°C (typ. value) with 15°C hysteresis (typ. value). 12/22 L6226 APPLICATION INFORMATION A typical application using L6226 is shown in Fig. 12. Typical component values for the application are shown in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near the L6226 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the ENA/OCDA and ENB/OCDB nodes to ground set the shut down time for the Brgidge A and Bridge B respectively when an over current is detected (see Overcurrent Protection). The two current sources (SENSEA and SENSEB) should be connected to Power Ground with a trace length as short as possible in the layout. To increase noise immunity, unused logic pins are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and Signal Ground separated on PCB. Table 2. Component Values for Typical Application C1 100uF D1 1N4148 C2 100nF D2 1N4148 CBOOT 220nF RCLA 5KΩ CP 10nF RCLB 5KΩ CENA 5.6nF RENA 100kΩ CENB 5.6nF RENB 100kΩ CREF 68nF RP 100Ω Figure 12. Typical Application + VS 8-52VDC VSA C1 POWER GROUND - SIGNAL GROUND VSB C2 17 4 23 OCDA ENA RENA ENA CENA D1 CBOOT 20 RP D2 VCP VBOOT SENSEA SENSEB LOADA OUT1A OUT2A LOADB 22 CP OUT1B OUT2B GND GND GND GND 9 14 OCDB ENB 15 RENB ENB CENB 3 10 5 21 8 11 12 1 2 IN1B IN1B IN2B IN2B IN1A IN1A IN2A IN2A 16 18 24 RCLA 19 6 PROGCLA 13 PROGCLB RCLB 7 D02IN1344 13/22 L6226 PARALLELED OPERATION The outputs of the L6226 can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges. When the two halves of one full bridge (for example OUT1A and OUT2A) are connected in parallel, the peak current rating is not increased since the total current must still flow through one bond wire on the power supply or sense pin. In addition the over current detection senses the sum of the current in the upper devices of each bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detection threshold. For most applications the recommended configuration is Half Bridge 1 of Bridge A paralleled with the Half Bridge 1 of the Bridge B, and the same for the Half Bridges 2 as shown in Figure 13. The current in the two devices connected in parallel will share very well since the RDS(ON) of the devices on the same die is well matched. When connected in this configuration the over current detection circuit, which senses the current in each bridge (A and B), will sense the current in upper devices connected in parallel independently and the sense circuit with the lowest threshold will trip first. With the enables connected in parallel, the first detection of an over current in either upper DMOS device will turn of both bridges. Assuming that the two DMOS devices share the current equally, the resulting over current detection threshold will be twice the minimum threshold set by the resistors RCLA or RCLB in figure 13. It is recommended to use RCLA = RCLB. In this configuration the resulting Bridge has the following characteristics. - Equivalent Device: FULL BRIDGE - RDS(ON) 0.37Ω Typ. Value @ TJ = 25°C - 2.8A max RMS Load Current - 5.6A max OCD Threshold Figure 13. Parallel connection for higher current + VS 8-52VDC VSA C1 POWER GROUND - SIGNAL GROUND VSB C2 17 9 14 D1 CBOOT RP D2 VCP 22 CP VBOOT SENSEA SENSEB OUT1A OUT2A LOAD 20 OUT1B OUT2B GND GND GND GND 4 23 OCDB ENB OCDA ENA 10 1 2 IN1A IN1 IN2A 5 21 11 8 12 16 18 24 IN2B IN2 PROGCLA RCLA 19 6 IN1B 13 PROGCLB RCLB 7 D02IN1364 14/22 EN CEN 15 3 REN L6226 To operate the device in parallel and maintain a lower over current threshold, Half Bridge 1 and the Half Bridge 2 of the Bridge A can be connected in parallel and the same done for the Bridge B as shown in Figure 14. In this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense pins so the dissipation in the device will be reduced, but the peak current rating is not increased. When connected in this configuration the over current detection circuit, senses the sum of the current in upper devices connected in parallel. With the enables connected in parallel, an over current will turn of both bridges. Since the circuit senses the total current in the upper devices, the over current threshold is equal to the threshold set the resistor RCLA or RCLB in figure 14. RCLA sets the threshold when outputs OUT1A and OUT2A are high and resistor RCLB sets the threshold when outputs OUT1B and OUT2B are high. It is recommended to use RCLA = RCLB. In this configuration, the resulting bridge has the following characteristics. - Equivalent Device: FULL BRIDGE - RDS(ON) 0.37Ω Typ. Value @ TJ = 25°C - 1.4A max RMS Load Current - 2.8A max OCD Threshold Figure 14. Parallel connection with lower Overcurrent Threshold + VS 8-52VDC VSA C1 POWER GROUND - SIGNAL GROUND VSB C2 RP D2 VCP 22 CP VBOOT SENSEA SENSEB OUT1A OUT2A LOAD 17 4 23 D1 CBOOT 20 OUT1B OUT2B GND GND GND GND 9 14 OCDA ENA OCDB ENB 15 REN EN CEN 3 10 1 5 2 21 8 11 12 16 18 24 INA IN2A IN1B INB IN2B PROGCLA RCLA 19 6 IN1A 13 PROGCLB RCLB 7 D02IN1361 15/22 L6226 It is also possible to parallel the four Half Bridges to obtain a simple Half Bridge as shown in Fig. 15. In this configuration the, the over current threshold is equal to twice the minimum threshold set by the resistors RCLA or RCLB in Figure 15. It is recommended to use RCLA = RCLB. The resulting half bridge has the following characteristics. - Equivalent Device: HALF BRIDGE - RDS(ON) 0.18Ω Typ. Value @ TJ = 25°C - 2.8A max RMS Load Current - 5.6A max OCD Threshold Figure 15. Paralleling the four Half Bridges + VS 8-52VDC VSA C1 VSB C2 POWER GROUND - SIGNAL GROUND D1 CBOOT RP D2 VCP 17 22 CP VBOOT SENSEA SENSEB OUT1A OUT2A LOAD OUT1B OUT2B GND GND GND GND 16/22 20 4 23 9 14 OCDA ENA OCDB ENB 15 REN EN CEN 3 10 1 5 2 21 8 16 18 11 12 24 IN2A IN IN1B IN2B PROGCLA RCLA 19 6 IN1A 13 PROGCLB RCLB 7 D02IN1365 L6226 OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION In Fig. 16 and Fig. 17 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving two loads, for two different driving types: – One Full Bridge ON at a time (Fig.16) in which only one load at a time is energized. – Two Full Bridges ON at the same time (Fig.17) in which two loads at the same time are energized. For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125°C maximum). Figure 16. IC Power Dissipation versus Output Current with One Full Bridge ON at a time. ONE FULL BRIDGE ON AT A TIME 10 IA I OUT 8 IB 6 PD [W] I OUT 4 Test Conditions: Supply Voltage = 24V 2 0 0 0.25 0.5 0.75 1 No PW M fSW = 3 0 kHz (slow decay) 1.25 1.5 I OUT [A] Figure 17. IC Power Dissipation versus Output Current with Two Full Bridges ON at the same time. TWO FULL BRIDGES ON AT THE SAME TIME IA 10 8 I OUT IB 6 I OUT PD [W ] 4 Test Conditions: Supply Volt age =24 V 2 0 0 0.25 0.5 0.75 1 I OUT [A ] 1.25 1.5 No PWM f SW = 30 kHz (slow decay) THERMAL MANAGEMENT In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be deliver by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. Figures 19, 20 and 21 show the Junction-toAmbient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packages. For instance, using a PowerSO package with copper slug soldered on a 1.5 mm copper thickness FR4 board with 6cm2 dissipating footprint (copper thickness of 35µm), the Rth j-amb is about 35°C/W. Fig. 18 shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15°C/W. 17/22 L6226 Figure 18. Mounting the PowerSO package. Slug soldered to PCB with dissipating area Slug soldered to PCB with dissipating area plus ground layer Slug soldered to PCB with dissipating area plus ground layer contacted through via holes Figure 19. PowerSO36 Junction-Ambient thermal resistance versus on-board copper area. ºC / W 43 38 33 W ith o ut G ro u nd La yer 28 W ith Gro un d La yer W ith Gro un d La yer+ 16 via H o le s 23 On-Board Copper Area 18 13 1 2 3 4 5 6 7 8 9 10 11 12 13 s q. cm Figure 20. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area. ºC / W On-Board Copper Area 49 48 C o p pe r Are a is o n Bo tto m S id e 47 C o p pe r Are a is o n To p S i de 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12 s q . cm Figure 21. SO24 Junction-Ambient thermal resistance versus on-board copper area. On-Board Copper Area ºC / W 68 66 64 62 60 C o pp er A re a is o n T op S id e 58 56 54 52 50 48 1 2 3 4 5 6 7 s q. cm 18/22 8 9 10 11 12 L6226 DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S MIN. mm TYP. 0.10 0 0.22 0.23 15.80 9.40 13.90 MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50 inch TYP. MIN. 0.004 0 0.008 0.009 0.622 0.370 0.547 0.65 11.05 10.90 0.0256 0.435 11.10 0.429 2.90 6.20 0.228 3.20 0.114 0.10 0 15.90 0.610 1.10 1.10 0.031 10°(max.) 8 °(max.) 5.80 2.90 0 15.50 0.80 OUTLINE AND MECHANICAL DATA MAX. 0.141 0.012 0.130 0.004 0.015 0.012 0.630 0.385 0.570 0.437 0.114 0.244 0.126 0.004 0.626 0.043 0.043 PowerSO36 (1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G". N N a2 e A DETAIL A A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 36 BOTTOM VIEW 19 E3 B E1 E2 D1 DETAIL B 0.35 Gage Plane 1 1 -C- 8 S h x 45˚ b ⊕ 0.12 L SEATING PLANE G M AB PSO36MEC C (COPLANARITY) 19/22 L6226 mm DIM. MIN. TYP. A A1 inch MAX. MIN. TYP. 4.320 0.380 A2 0.170 0.015 3.300 0.130 B 0.410 0.460 0.510 0.016 0.018 0.020 B1 1.400 1.520 1.650 0.055 0.060 0.065 c 0.200 0.250 0.300 0.008 0.010 0.012 D 31.62 31.75 31.88 1.245 1.250 1.255 E 7.620 8.260 0.300 e 2.54 E1 6.350 e1 L 6.600 M 0.325 0.100 6.860 0.250 0.260 0.270 0.300 7.620 3.180 OUTLINE AND MECHANICAL DATA MAX. 3.430 0.125 0.135 Powerdip 24 0˚ min, 15˚ max. E1 A2 A A1 L B B1 e e1 D 24 13 c 1 12 M SDIP24L 20/22 L6226 mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 15.20 15.60 0.598 0.614 E 7.40 7.60 0.291 0.299 e 1.27 10.0 10.65 0.394 0.419 h 0.25 0;75 0.010 0.030 L 0.40 1.27 0.016 0.050 ddd Weight: 0.60gr 0.050 H k OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO24 0070769 C 21/22 L6226 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. 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