L6246 12V VOICE COIL MOTOR DRIVER 12V (±10%) OPERATION 3A MAXIMUM CURRENT CAPABILITY 0.3Ω MAXIMUM ON RESISTANCE OF EACH POWER DMOS AT A JUNCTION TEMPERATAURE OF 25°C CLASS AB POWER AMPLIFIERS LOGIC AND POWER SUPPLY MONITOR POWER ON RESET PARKING FUNCTION WITH SELECTABLE RETRACT VOLTAGE AND DYNAMIC BRAKE BEFORE PARKING ENABLE FUNCTION GATE DRIVER FOR EXTERNAL BLOCKING N-MOSFET OVERTEMPERATURE PROTECTION OVERTEMPERATURE WARNING OUTPUT PQFP44 PACKAGE DESCRIPTION The voice coil driver L6246 is a linear power amplifier designed to drive single phase bipolar DC motors for hard disk drive applications. The device contains a selectable transconductance loop, which allows high precision for head positioning. The power stage is composed of 2 power amplifiers, in AB class, with 4 DMOSs, with Rdson of 0.5Ω (Sink+Source) maximum, in a H-bridge con- February 1998 MULTIPOWER BCD TECHNOLOGY PQFP44 (10x10) figuration. Drive voltage for the upper DMOS FETs is provided by a charge pump circuit to ensure low Rdson. Automatic brake and parking of the head actuator is performed by logic or when a failure condition is detected by power supply monitors. An external resistor programs the parking voltage that enables the head retract. In addition, a 5V stable output is provided for the external usage, and a gate driver circuit enables an external power supply isolation N-MOSFET. This device is built in BCD II technology allowing dense digital circuitry to be combined with high power bipolar power devices and is assembled in PQFP44. 1/12 L6246 CPGND GND OUT+ VCC C1 C2 VCC VCP OUT- GND GATE DRIVE PIN CONNECTION (Top view) 44 43 42 41 40 39 38 37 36 35 34 N.C. 1 33 N.C. FILTER_CAP 2 32 ENABLE BRAKE DELAY 3 31 -SPINDLE START -THERMAL SD 4 30 VCM PARK SENSE-IN+ 5 29 -W_GATE SENSE-IN- 6 28 RPARK GND 7 27 VBEMF ERR-OUT 8 26 +12SETPT ERR- 9 25 +5SETPT SENSE-OUT 10 24 +5V REF_GND N.C. 11 23 N.C. T_CAP +5V REF -POR VCC VDD -AE_W_GATE MOTOR START VCC/2 VIN+ VIN- VIN_OUT 12 13 14 15 16 17 18 19 20 21 22 D95IN241B BLOCK DIAGRAM CP_GND GATE DRIVE -SPINDLE START MOTOR -AE START -W_GATE W_GATE VCM PARK INPUT AMPLIFIER C1 CHARGE PUMP C2 VCP VIN_OUT -POR VCC +5 +12 FILTER CAP 30K 4µA + THERMAL -THERMAL SD 25K 10K - 10K BRAKE CIRCUIT + - REF1 VDD - 10K BRAKE DELAY POWER AMPLIFIERS VCC 20K + +5 FILTER CAP + OUT+ - T_CAP REF1 PARKING RPARK VCC/2 VPARK + GND ERR_OUT VCC/2 ERR- VINVIN+ GATE DRIVER + ERROR AMPL. VCC + SENSE AMPLIFIER + - OUT- - REF1 +5V REF +5V REF_GND REF. VOLT. GENERATOR GND V CC/2 2/12 SENSE _IN+ SENSE _IN- SENSE_ OUT VBEMF D95IN242B L6246 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vpow. max. Maximum supply voltage Vdigital max. Maximum supply voltage Value Unit 15 V 7 V Vin max. Maximum input voltage Vdigital ±0.3 V Vin min. Minimum input voltage GND - 0.3 V 3 A Peak sink/source output current Ipeak Idc DC sink/source output current 1.7 A Ptot Maximum total power dissipation ≅1.7 W Top Operative temperature range 0 to 80 °C THERMAL DATA Symbol Value Unit Rth j-case Thermal resistance junction to case Parameter ≅20 °C/W Rth j-amb Thermal resistance junction to ambient mounted on standard PCB (*) ≅66 °C/W Rth j-amb Thermal resistance junction to ambient mounted on PCB (**) ≅35 °C/W (*) Standard board construction: single layer (1S 0P); size 100mm long by 100mm wide. (**) The board construction includes: a 6 layer board (2S 4P, with power planes ≅80%); size 136mm long by 99mm wide; package location near middle point of lenght and one third of width. PIN FUNCTIONS Pin Name Description 1 N.C. 2 Filter_cap Not Connected. 3 Brake Delay 4 -Thermal SD 5 Sense_in+ 6 Sense_in- 7 Gnd 8 Err_out 9 Err- 10 Sense_out 11 N.C. 12 Vin_out 13 Vin- Inverting Input of Input Amplifier. 14 Vin+ Non inverting Input of Input Amplifier. 15 +Vcc/2 Filter capacitor for 10V internal regulator. The capacitor is optional. Voice Coil Motor brake delay capacitor. Pre Thermal Shut Down indication Output. Non inverting Input of Sense Amplifier. Inverting Input of Sense Amplifier. Ground. Error Amplifier Output. Inverting Input of Error Amplifier. Output of Sense Amplifier. Not Connected. Output of Input Amplifier. Half Supply Voltage reference. 16 +Motor start 17 -AE_W_Gate 18 +Vdd +5V Supply. 19 +Vcc +12V Supply. 20 -POR 21 +5V Ref 22 T_cap 23 N.C. 24 +5V Ref Gnd 25 +5Setpt Motor start Output to Spindle Controller. Write Gate Output to AE. Power On Reset. Low will signal the failure of the logic supply or 12V supply +5V Reference Output from the Voltage Reference Regulator. Power On Reset Timing Capacitor. The capacitor sets the POR delay. Not Connected. Ground for Voltage Reference Generator. +5V Monitor Set Point and filtering 3/12 L6246 PIN FUNCTIONS (continued) Pin Name Description 26 +12Setpt 27 Vbemf Input BEMF from spindle motor for parking circuit. 28 Rpark Resistor for setting the park voltage. 29 -W_Gate +12V Monitor Set Point and filtering Write Gate Input. 30 +VCM park 31 -Spindle_start External input for parking. High will activate the park procedure. 32 +Enable 33 N.C. 34 Cpgnd 35 Gnd Ground. 36 Out+ Power Amplifier Output. 37 Vcc +12V Power Supply. 38 C1 Charge Pump Oscillator Output. 39 C2 Input for external Charge Pump Capacitor. 40 Vcp Output for Charge Pump Storage Capacitor. 41 Vcc +12V Power Supply. 42 Out- Power Amplifier Output. 43 Gnd Ground. 44 Gate Drive Spindle Start input. Input. logic low will disable only the IC. Not Connected. Charge Pump Ground. Gate Drive for External Isolation N-MOSFETS. ELECTRICAL CHARACTERISTICS (Tj = 25°C, Vdd = 5V, Vcc = 12V; unless otherwise specified.) Symbol Vcc Parameter Test Condition Analog/Power supply voltage range Vdd Digital supply voltage range Idd Digital supply quiescent current Output ENABLED Idd Digital supply quiescent current Icc Power supply quiescent current Icc Power supply quiescent current Min. Typ. Max. Unit 10.8 12 13.2 V 5 5.5 4.5 V 5 mA Output DISABLED 5 mA Output ENABLED 20 mA Output DISABLED 10 mA 160 °C 25 °C 140 °C 15 °C THERMAL SHUT DOWN DATA Th_SD Shut down Temperature Th_SD_H Shut down hysteresys Th_Warn Pre Shut down alarm 135 115 Pre Shut down alarm hysteresys EXTERNAL N-MOSFET GATE DRIVER Vll Low level voltage Vhl High level voltage Isink Current sinking capability Isource Current source capability 500 mV Vcc+4 V 4 mA 0.5 mA POWER ON RESET AND GATE SPECIFICATION Vdd_und_th Digital undervoltage threshold 3.8 4.1 4.45 Vcc_und_th Power undervoltage threshold 8.5 9.25 10.0 V 375 500 625 ms 1 µs KΩ POR_to POR _delay Vdd_POR_T_R 4/12 POR timeout Cpor = 1µF Time delay for POR Active Power supply POR thereshold Resistance 10 V L6246 ELECTRICAL CHARACTERISTICS (continued) Symbol VCC_POR_T_R I_POR_O Parameter Test Condition Min. Typ. Max. Unit Logic supply POR thereshold Resistance 10 KΩ POR output current drive 4 mA LOGIC INTERFACE VOLTAGE LEVEL (All digital inputs are CMOS compatible) Voh CMOS high level output voltage Iout = 1.0mA Vol CMOS low level output voltage Iout = 1.0mA Vih TTL high level input voltage Vil TTL low level input voltage 4.10 V 0.40 2 V V 0.80 V 5V REFERENCE GENERATOR Vref Voltage reference at Power On Drift Drift from Power On 4.75 -2 loref Current output 10 5.00 5.25 V +2 % mA INPUT AMPLIFIER Vi Input voltage range Vref (-) Vref (+) V 0 5.00 V Vcm Input common mode voltage range Vds Input differential voltage swing -5 +5 V Vos Input offset voltage -5 +5 mV Ib Input Bias current -500 +500 nA Gv Open Loop voltage Gain 80 dB SR Output slew rate 0.6 V/µs Gain bandwidth product 1 MHz Power supply rejection ratio 80 dB Output voltage swing 9 V GBW PSRR Vo ERROR AMPLIFIER Vi VCC/2 -0.5 Input voltage range VCC/2 +0.5 V mV Vos Input offset voltage -5 +5 Ib Input Bias current -500 +500 Gv Open Loop voltage Gain 80 Output slew rate SR nA dB 0.6 V/µs GBW Gain bandwidth product 1 MHz PSRR Power supply rejection ratio 80 dB Vo Output voltage swing VCC/2 -2Vbe VCC/2 +2Vbe V Gnd Vcc V SENSE AMPLIFIER Vi Input voltage range Vos Input offset voltage -6 +6 mV Input sink and source current -1.5 +1.5 mA Power supply rejection ratio 50 Gv Vloltage gain 9.9 10.1 V/V Rin Differential input resistance 3 KΩ Gain bandwidth product 1 MHz Ii PSRR GBW Vli Linear differential input voltage range CMRR Common mode rejection ratio Gv = 10(V/V) -0.35 56 dB 10 +0.55 V dB 5/12 L6246 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit POWER AMPLIFIER Rdson DMOS on resistance Gdv Differential voltage gain Iol Output current leakage SR Output slew rate Tsr Saturation recovery time GBW Gain bandwidth product at 25°C Ω 0.3 32 V/V µA 500 0.4 V/µs µs 5 100 KHz RETRACT Vr Max. retract voltage Vcc shorted to GND Vr Max. retract voltage Vcc Normal 300 mV 1 V 1 µF 0.2 µF CHARGE PUMP Cs Storage capacitor Vs Storage voltage Cp Pump capacitor Vcc +4 V RETRACT TRUTH TABLE Input Input Output Output -Retract +Enable Bridge Enable +Retract Brake and Retract 0 X 0 1 Run 1 1 1 0 Disable 1 0 0 0 BLOCK DESCRIPTION POWER AMPLIFIERS The two power amplifiers are connected in bridge configuration working in AB class. SENSE AMPLIFIER This stage senses the voltage drop across the Rsense. The input stage is supplied by the charge pump voltage to have an high dynamic, while the other sections of the amplifier are supplied by the voltage of 10.5V internally regulated to have an high power supply rejection (this voltage, supplies also the error amplifier, the input amplifier and the operational amplifier which generates the Vcc/2 voltage). The open loop gain is around 80dB and the bandwith is more than 1MHz. The voltage gain is fixed internally at 10 V/V. ERROR AMPLIFIER This is the stage which compares the input voltage and the sense voltage, generating the control voltage for the power section. 6/12 The open loop gain and bandwith of this amplifier are similar to the sense amplifier. The negative input and the output of the error amplifier are accessible externally in order to have the current loop compensation user configurable. The dynamic of the output is limited at +/- 2Vbe to have a faster response of the output voltage. INPUT AMPLIFIER The inputs and the output pins are externally accessible to have the possibility to configure the transconductance gain of the current control loop selecting the voltage gain of this amplifier. The open loop gain and bandwith of this amplifier are similar to the sense amplifier. REFERENCE VOLTAGE GENERATOR This block generates the two reference voltage Vcc/2 and +5VREF. The Vcc/2 voltage is used as reference by the current control loop. The +5VREF is a very stable voltage generator that can be used as reference voltage of an external DAC. L6246 POWER SUPPLY MONITOR This circuit monitors the logic supply (5V) and the power supply (12V) and activates the power on reset output (POR) and the VCM PARK circuit. After both logic and power supply reach their nominal value a timing capacitor (T_CAP) has to be charge before the POR output change from low to high level. POR delay= C⋅V I where: C is the capacitor value connected at pin T_CAP V is delta voltage that capacitor have to be charged (2.3V) I is the costant current charging the capacitor (4µA typ.) At the two input pins, +12 FILTER CAP and + 5 FILTER CAP, can be connected two capacitors for filtering the noise on the power supply, avoiding in this case undesired commutations of the POR signal because of some fast negative spikes on the line. BRAKE AND PARKING CIRCUITS The voice coil driver is switched into the parking condition through the VCM PARK input or when the POR signal is low. In such condition immediately the output stage turns on the two lower DMOS of the power bridge to activate the BRAKE of the voice coil motor. After a delay generated by the capacitor at the BRAKE DELAY pin, only one of the two lower DMOS stays on while the opposite half bridge is tristated. BRAKE delay = C⋅V I where: C is the capacitor value connected at pin BRAKE DELAY V is delta voltage that capacitor have to be charged (3V) I is the costant current charging the capacitor (5µA typ.) The parking voltage is then supplied by the PARKING circuit connected to the output that has been tristated. The value of such a voltage is set by connecting an external resistor between the RPARK pin and ground. Vr = where: Vbandgap⋅ 104 Rpark Vr is the retract voltage for parking the heads Vbandgap is the internal bandgap reference voltage of 1.4V Rpark is value of the resistor connected at RPARK pin The parking circuit takes the power supply from the spindle driver through the VBEMF pin, so that in case of power fail the retract of the heads is possible using the rectified BEMF voltage coming from the spindle motor. CHARGE PUMP The charge pump circuit is used as a means of almost doubling the power supply voltage (12V) in order to drive the upper DMOS of the power bridge. The energy stored in the in the capacitor connected at VCP pin is also used to drive the gate of the external N-MOSFET. GATE DRIVER This circuit provide the voltage driving the gate of the external isolation N-MOSFET, and it is controlled by the POR signal. THERMAL The thermal protection circuit has two threshold, the first if the pre shut down alarm that activates the THERMAL SD signal and the second is the shut down temperature that tristates the output stage when the junction temperature increases over this level. APPLICATION INFORMATION Example of calculation of the error amplifier compansation for the stability of the current control loop. As can be seen from the draw of the current control loop circuit of the next page, the voltage across the load is: #1 VL = ACPW ⋅ ACERR ⋅ (ACINP ⋅ VIN - ACENSE ⋅ Vsense) Vsense = Rs ⋅ IL VL = ( ZL + Rs)⋅ IL where AC... is the closed loop gain of Power, Error, Sense and Input Amplifier. Changing in the #1 the transfer function between the load current and the VIN is: #2 ACPW ⋅ ACERR ⋅ ACINP IL = VIN ZL + RS + ACPW ⋅ ACERR ⋅ ACSENSE ⋅ RS 7/12 L6246 Typical Application Circuit VDD VOICE COIL MOTOR LL RL 100nF Rs 0.2 OUT_ SENSE_OUT ERR_OUT 1K 1M 10nF SENSE_IN42 6 SENSE_IN+ VDD OUT+ 5 C1 C2 38 18 36 19 39 10 41 8 37 V CC 1K 22µF 100nF ERR- 1K 44 9 27 VIN_OUT 12 40 10K 10K VIN- 10K VIN+ VCTL 28 13 VREF 21 L6246 14 24 PQFP44 10K VCC/2 VCC/2 CPGND GND 25 34 7,35,43 AE W GATE 17 16 THERMAL SHTD 4 POR 20 FILTER_CAP 26 15 MOTOR START 10.5V INT.REG. VCC V CC V CC 22 100nF GATE DRV G S D V BEMF 1µF V CP P322 FROM SPINDLE DRIVER 100nF 51K R PARK 5VREF 5VREF 5VREF GND GND (*) 12SEPT (*) 5SSEPT 1µF 12SEPT 1µF 3 2 (*) 5SSEPT 32 ENABLE 30 VCM PARK 31 SPINDLE START 29 W GATE D95IN268 FILTER CAPACITORS TO BE SET IN APPLICATION Current Control Loop Circuit VCC/2 + 10VSENSE VCC/2 + (RA/RB) (ZC/RC) VIN-10 (ZC/R1) VSENSE 20K 2K - V SENSE R2 C VCC/2 R3 - RS + POWER AMPL. LL - LOAD VL RL - + + POWER AMPL. + RB RA VCC/2 1.1K VCC/2 INPUT AMPL. VL=32 ( (ZC/RC) VIN - 10 (ZC/R1) VSENSE ) VCC/2 - (RA-RB) VIN = ACPW * ACERR ( ACIMP * VIN - ACSENSE * VSENSE ) D95IN269B 8/12 1.1K VCC/2 RC (=R1) RB 16.5K 17.5K ZC RA VIN TO SENSE - AMPLIFIER + R1 SENSE AMPL. 20K ERROR AMPL. - + 2K + V CC/2 L6246 and its pole is at frequency If Now We Define: #3 Aloop = ACPW ⋅ ACERR ⋅ ACSENSE ⋅ RS RS + ZL so around 1KHz if L = 1.2mH. So considering: we obtain: Ax | dB = Aloop | #4 1 2π L (RS + RL) ACINP 1 Aloop ⋅ ⋅ ACSENSE RS IL = VIN 1 + Aloop dB+ ACSENSE | dB + ACERR | dB ACPW | RS dB RS + RL we have these Bode diagrams: Atlowfrequencyis: Aloop = 32 ⋅ dB R2 R1 ⋅ 10 ⋅ RS (RS + ZL) ACPW if R2 = 1M, R1 = 1K, RS = 0.2, RL = 7 then Aloop = 8889 = 80dB. Being Aloop very high we can simplify the #4 in this way: 30dB 130KHz ACSENSE IL ACINP 1 1 1 = ⋅ = = VIN ACSENSE RS 10 ⋅ 0.2 2 210KHz 20dB For the stability we have to study the stability of Aloop, that as we can see from the #3 is a multiplication, so in dB is a sum: -31dB Aloop | dB + dB = ACPW | dB+ACERR | dB+ACSENSE | LOAD RS dB RS + ZL So we can take in consideration the BODE diagrams of the each operational amplifier, with particular attention to the Error amplifier. 1)The Power amplifier is actually composed by two operational amplifiers in the way to have a gain of +16 and -16 (in voltage) respectevely, for a total of 32 = 30dB. The point at -3dB is around 130KHz. 2)The Sense amplifier has a gain of 20dB with the point at -3dB around 210KHz. 3)The load introduce an attenuationof: 20log RS = -31dB with RS = 0.2 and RL = 7 RS + RL AX 19dB 1K 10K 100K D95IN270A As can be easily see the bandwith is narrow and the gain is low. It is possible to increase both choosing an appropriate compensation of the Error amplifier. The total bandwith should be, of course, at least a decade lower of the 130KHz to avoid instability problem. The bandwith guaranteed by the Error amplifier has a Gmax of 80dB and a gain of 0dB at 1MHz approximately, the real is some dB more with a larger bandwith. 9/12 L6246 As can be seen the choice of the pole influence overall in fixing the gain at high frequency. The gain at high frequency must be choosen in order to not create instability problem, because more higher is this gain and lower is the second pole that we have at high frequency. If this pole is taken close to the other that we have already seen at 130KHz and 210KHz, instability problems can arise. Adding together AX | dB and ACERR | dB we obtaine the Aloop: ERROR AMPL. GAIN (dB) OPEN LOOP GAIN 120 100 80 60 ACERR (dB) 40 20 COMPENSATION AT 3Hz 1 D95IN271 10 1K 100 10K 100K 1M 10M 60 COMPENSATION AT 100Hz 40 20 Using the compensation network of the draw of pag.8, we have a error amplifier transfer function of: 1 + scR3 VO ZC R2 =− =− ⋅ VI R1 R1 1 + sc (R3 + R2) AX(dB) 19 ALOOP (dB) so: R2 Gmax (DC) = = 1000 = 60dB R1 with R1 = 1MΩ and R2 = 1KΩ 79 IS STABLE 60 IS NOT STABLE 40 20 1 2 π R3C 1 pole = 2 π (R3 + R2) C zero = D95IN273 10 100 1K 10K 100K 1M 10M So the choice of the compensation network must be done in order to fix at the beginning the Gmax Note: Fpole is lower than Fzero of the error amplifier depending on the ratio The best choice is to cancel the pole of the load (at around 1KHz) with the zero of the compensation. R2 . R1 To calculate the R3 and C values satisfying the following system: 1 2πL 1 = 2 π R3C RL + Rsense ACERR (dB) Error amplifier zero equal to load pole 120 100 X DIFFERENTS POLES EXAMPLES 80 1 Admissible Bandwith = = Gloop 2 π (R3 + R2)C X 60 130KHz 10 = = 1.5Hz 8912 40 20 D95IN272 CLOSED LOOP ACERR 1 10 X 100 1K 10K 100K 1M 10M This example is for crossing the 0dB one decade before the first pole of the Power Amplifier (130KHz), starting with a Gloop max of 79dB. 10/12 L6246 PQFP44 (10x10) PACKAGE MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. MAX. 2.45 A1 0.25 A2 1.95 B 0.096 0.010 2.00 2.10 0.077 0.079 0.30 0.45 0.012 0.018 c 0.13 0.23 0.005 0.009 D 12.95 13.20 13.45 0.51 0.52 0.53 D1 9.90 10.00 10.10 0.390 0.394 0.398 D3 8.00 0.315 e 0.80 0.031 0.083 E 12.95 13.20 13.45 0.510 0.520 0.530 E1 9.90 10.00 10.10 0.390 0.394 0.398 E3 8.00 L 0.65 0.315 0.80 L1 0.95 0.026 0.031 1.60 0.037 0.063 K 0°(min.), 7°(max.) D D1 A A2 D3 A1 23 33 22 34 0.10mm .004 44 B E E1 B E3 Seating Plane 12 11 1 C L L1 e K PQFP44 11/12 L6246 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1998 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 12/12