L6285 3 CHANNELS MULTIPOWER SYSTEM ADVANCE DATA CHANNEL-A AND CHANNEL-B FOR UNIPOLAR STEPPER MOTORS – LOW SIDE: RDSON = 1.2Ω – HIGH SIDE ; R DSON = 1.2Ω CHANNEL-C FOR DC MOTORS – LOW SIDE: RDSON = 1.7Ω – HIGH SIDE: RDSON = 1.2Ω CHOPPING MODE DRIVING FOR C.L. CURRENT CONTROL ON CHA AND CHB AND O.L. VOLTAGE CONTROL ON CHC. INTERNAL FOUR DRIVING LATCHES 16 BIT INTERNAL SHIFT REGISTER DIRECT INTERFACE TO µP SERIAL DRIVING SEQUENCE LOADING CMOS COMPATIBLE INPUTS PRE-ALARM OUTPUT SIGNAL THERMAL SHUTDOWN DESCRIPTION This Combo Motor Driver uses large scale integration to incorporate several functions into the same chip. 1) Two unipolar stepper motor driver 2) A full bridge DC motor driver MULTIPOWER BCD TECHNOLOGY PLCC44 SDIP42 ORDERING NUMBERS: L6285 L6285S 3) Serial microprocesor interface The power output stages are DMOS and the input can be interfaced to a CMOS Microprocessor logic. The phase current in the unipolar stepper motor windings is controlled by two external sensing resistors in fixed frequency chopping mode. The oscillator block provides clocks each other 180° out of phase to the two stepper motor driver in order to avoid symultaneous current peaks. For the DC motor driver is used a bridge; the RMS voltage to supply this motor is fixed by a BLOCK DIAGRAM May 1994 1/16 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L6285 simple PWM open loop. The 3 motors are controlled by the micro through 4 latches of 4 bit each. The loading of these registers is in serial mode. The I.C. operates at 5V supply for the logic and at 24V supply for the power stages. The packages are SDIP42 and PLCC44 with 6 pins devoted to ground and to sink out the heat produced by power dissipation. 6 5 4 3 2 PWGND COM3,4B VP COM1,2B OUT1C S1,2C OUT2C COM1,2A VP COM3,4A PWGND PIN CONNECTION (Top view) 1 44 43 42 41 40 PWGND 7 39 PWGND OUT1A 8 38 OUT1B S1,2A 9 37 S1,2B OUT2A 10 36 OUT2B CLAMPA 11 35 CLAMPB OUT3A 12 34 OUT3B S3,4A 13 33 S3,4B OUT4A 14 32 BOOT1 15 BOOT3 16 GND PLCC44 17 OUT2C 1 42 S1,2C COM1,2A 2 41 OUT1C VP 3 40 COM1,2B COM3,4A 4 39 VP N.C. 5 38 COM3,4B PWGND 6 37 PWGND OUT1A 7 36 OUT1B S1,2A 8 35 S1,2B OUT2A 9 34 OUT2B 33 CLAMPB 10 OUT3A 11 32 OUT3B S3,4A 12 31 S3,4B OUT4B OUT4A 13 30 OUT4B 31 VLOW BOOT1 14 29 VLOW 30 COSC BOOT3 15 28 COSC GND 16 27 GND N.C. 17 26 V2 BOOT2 18 25 OSC RESET SID 19 24 A1TH SCK 20 23 A0TH STB 21 22 VS 29 GND V2 OSC RESET A1TH A0TH N.C. VS N.C. STB SCK SID 18 19 20 21 22 23 24 25 26 27 28 BOOT2 SDIP42 CLAMPA D94IN067 D94IN060A ABSOLUTE MAXIMUM RATINGS Symbol Parameter VP Power Supply Voltage VS Logic Supply Voltage Vin Logic Input Voltage Value Unit 30 V 7 V -0.3 to VS + 0.3 V ILOW Low Side DMOS max DC Current 1 A IHIGH High Side DMOS max DC Current 1 A A IpLOW Low Side DMOS max Peak Current (1µs On; 50µs OFF) 2 IpHIGH High Side DMOS max Peak Current (1µs On; 50µs OFF) 2 A Vbou t Max Output Voltage of Stepper Motor Driver (transient rcirculation) 60 V Vsense 1;2 Vsense 3 Max Voltage ON Vsense (CHA/CHB) -1 to 2 V Max Voltage ON Vsense (CHC) -1 to 2 V ΙfdDC Max DC Current of Forward Diode (DMOS Source Drain Diode) 1 A Ιfdpk Max Peak Current of Forward Diode (DMOS Source Drain Diode) (1µs On; 50µs OFF) 2 A Ptot Total Power Dissipation (Tpins = 90°C) With minimized dissipating copper area (Tamb = 70°C) 5 1.6 W W Top Operating Temperature Range 0 to 150 °C Tstg Storage Temperature Range -40 to 150 °C THERMAL DATA (PLCC44) Symbol Description R th j-pins R th j-amb Thermal Resistance Junction-pins Thermal Resistance Junction-ambient 2/16 Max. Max. SDIP42 PLCC44 Unit 15 48 12 50 °C/W °C/W L6285 PIN DESCRIPTION SDIP42 No PLCC44 No Name Functions 42 1 S1,2C Full bridge common source output to separate between power GND and logic GND. 1,41 2,44 OUT 1C, OUT 2C 2 3 COM 1,2A 3,39 4,42 Vp 4 5 COM 3,4A 6,37 6,7,39,40 GND 7,9, 11,14 8,10 12,14 OUT 1A, OUT 2A OUT 3A, OUT 4A 8 9 S1,2A 10,33 11,35 CLAMP A, CLAMP B 12 13 S3,4A Channel A sources of the DMOS OUT 3A, OUT 4A. A sensing resistor has to be connected from this pin and ground, for current control of phase 3,4 A. 14 15 BOOT 1 A capacitor between this pin and Vp stores the overvoltage for each high side DMOS driver gate. 15 16 BOOT 3 A capacitor between this pin and internal diodes allows the change pump to transfer energy to the capacitor at the pin BOOT 1. 16,27 17,29 GND 18 18 BOOT 2 19 19 SID Serial data input. 20 20 SCK Serial clock for serial data input. 21 21 STB Strobe to transfer the 16 bit shift register contents to the latch registers. Output of the channel C bridge. High side DMOS channel A for current chopping in the windings connected pins to OUT 1A, OUT 2A. Power Supply Voltage. High side DMOS channel A for current chopping in the windings connected to pins OUT 3A, OUT 4A. PowerGround and heatsink pins. Low side DMOS outputs of channel A stepper motor driver. Channel A sources of the DMOS OUT 1A, OUT 2A. A sensing resistor has to be connected from this pin and ground, for current control of phase 1,2 A. These pins have to be connected to an external zener diode to clamp the output voltage spikes of channel A/B. Logic Ground and Heatsink pins. Charge pump oscillator output. 5,17 22,24 NC Not connected. 22,39 23 Vs Logic Supply Voltage. 23,24 25,26 A0TH / A1TH Open collector outputs for thermal informations to the µP. 25 27 OSC/ RESET An RC network connected to this pin defines the oscillator frequency for stepper drivers. When OSC/RES is <1V, a reset signal is internally generated. 26 28 V2 A voltage to this pin defines the output duty cycle of Channel C. 28 30 Cosc A capacitor connected to this pin defines the chopping frequency of channel C. 29 31 Vlow This pin is low when the chopping low voltage (V2 low level) is selected; it is in high impedance when the chopping high voltage (V2 high level) is selected. Only for CHC operation. 30,32, 34,36 32,34 36,38 OUT4B, OUT3B OUT2B ,OUT1B 31 33 S 3, 4B Same as S 3, 4A, but for channel B. 35 37 S 1, 2B Same as S 1, 2A, but for channel B. 38 41 COM 3, 4B Same as COM 3, 4A, but for channel B. 40 43 COM 1, 2B Same as COM 1, 2A, but for channel B. Low side DMOS outputs of channel B stepper motor driver. 3/16 L6285 ELECTRICAL CHARACTERISTICS (Tj = 25 °C, Vs = 5V, Vp = 24V unless othewise specified) Symbol Parameter Vp Power Supply Voltage Ip Quiescent Power Supply Current Vs Logic Supply Voltage Is Quiescent Logic Supply Current Test Conditions Min. Typ. 9 (note 1) 4.5 (note 1) Max. Unit 26.5 V 7 mA 5.5 V 20 mA LOGIC LEVEL Symbol Parameter Test Conditions VinL Input Low Voltage VinH Input High Voltage IinL Input Low Current Vin = VinL IinH Input High Current Vin = VinH Min. Max. Unit -0.3 Typ. 1.35 V 3.15 VS+0.3 V µA -10 10 µA CHANNEL A AND CHANNEL B (UNIPOLAR MOTORS) Symbol Max. Unit RDSONL Low Side DMOS ON Res. IDS = 0.7A 1.2 Ω R DSONH High Side DMOS ON Res. IDS = 0.7A 1.2 Ω IDSSL Low Side DMOS Leakage Current VDS = 60V; output OFF 2 mA IDSSH High Side DMOS Leakage Current VP = 30V; VO= 0V -1.5 VREF Voltage reference to the Comparator LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4 100 220 340 465 Td fmax Parameter Turn OFF Delay on HIGH Side DMOS after the Sensing Current Reach the Threshold Value Test Conditions Min. Typ. mA 125 250 375 500 (note 2) Max Chopping Frequency 150 280 410 535 mV mV mV mV 1 µs 40 KHz CHANNEL C (DC MOTORS) (see Fig. 5) Symbol fosc Parameter Test Conditions Min. Typ. Max. Unit Oscillator Frequency Cosc = 3.3nF; V1 = 2/3VS 17 22 28 KHz 75 81 DC Duty Cycle V2 = 1/2VS 72 Ib2 Comparator Input Bias V2 = 200mV -1 Open Drain Output I = 5mA R DSONH High Side DMOS ON Res. IDS = 0.7A RDSONL Vlow 4/16 Low Side DMOS ON Res. IDS = 0.7A ILH HSD MOS Leakage Current VP = 30V; VO = 0V ILL LSD MOS Leakage Current VO = 30V; Vsense = 0V Vfddc Forward Diode DC Voltage (DMOS Diode) Ifdcc = 0.7A fmax Max Chopping Frequency Vboot Voltage on pin Boot1 IL bo ot Leakage Current on pin Boot1 Vbo tt = Vp +12V; Vp = 26.5V % µA 0.2 0.4 V 1.2 Ω 1.7 Ω -1 mA -1.5 mA 1.4 2 V 40 KHz 200 µA Vp +7 V L6285 ELECTRICAL CHARACTERISTICS (continued) OSCILLATOR (see Fig. 6) Symbol Min. Typ. Max. Unit fosc Oscillator Frequency Pin OSC/RESET Parameter COSC = 3.3nF; ROSC = 10KΩ Test Conditions 27 41 46 KHz Tdsc Capacitor Discharge Time (protect dead time) COSC = 3.3nF; ROSC = 10KΩ (see Fig. 1) 0.8 1.4 2 µs Vreset Reset Threshold Voltage 1 V INTERFACE TIMING Symbol Parameter Test Conditions t1 SCK Data Clock Cycle t2 t3 Min. (see Fig. 2) Typ. Max. Unit 200 ns SCK Data Set-upTime 30 ns SCK Data Hold Time 20 ns t4 SCK-STB Interval Time 30 ns t5 STB Pulse Width 100 ns Note 1: No output loaded; all register to low condition; no reset applied; V P = 26.5V; V S = 5.5V Note 2: The effect of the internal filter (RC Network) is not considered. Figure 1: Discharge time tdsc or Protection Time Figure 2: Interface Timing (Serial loading Mode) Serial Input Data b15 D15 D3 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 D2 D1 Register 4 D0 D3 D2 D1 Register 3 D0 D3 D2 D1 Register 2 D0 D3 D2 D1 Register 1 b0 D0 D0 5/16 L6285 BLOCK DIAGRAM DESCRIPTION (see Block Diagram) Inside the I.C. there are two unipolar stepper motor drivers, one bridge driver for DC motor, 4x4 bit latch registers, one shift register. the input logic, the charge pump, and the thermal protection. The following conditions are valid for all the 3 driver sections: 1)When the osc/res pin is tied to GND, an internal reset signal is generated which switches off all the outputs and resets the internal registers. 2)The conditions 1 is valid also during power on and power off transitions. 3)During power on and power off, the I.C. is safe for any conditions of V S and Vp 3)If Vp is present and VS desappears, the outputs are switched off. Input Logic The input CMOS logic interfaces the microprocessor logic to the 4 registers. An integrated Schmitttrigger circuit is used to improve noise immunity at each logic input. The data is introduced in the 16bit shift register by the SID pin. The first bit b 15 after 16 clock applied to SCK pin will be the D15 of the shift register. On the falling edge of STB the 16 bits of the shift register are transferred to the outputs of the 4 latch registers. Fig 2 shows the timing. CHA and CHB Stepper Motor Drivers Registers The Combo Motor Driver controls the 3 channels using 4 latch registers of 4 bit each: REGISTER 1 D0 D1 D2 D3 = = = = PHASE 1A NPHASE 2A PHASE 3A NPHASE 4A CHANNEL A CHANNEL A CHANNEL A CHANNEL A REGISTER 2 D0 D1 D2 D3 = = = = PHASE 1B NPHASE2B PHASE 3B NPHASE4B CHANNEL B CHANNEL B CHANNEL B CHANNEL B REGISTER 3 D0 D1 D2 D3 = = = = D/A D/A D/A D/A REGISTER 4 D0 D1 D2 D3 = = = = INPUT 1 INPUT 2 V2 VOLTAGE V2 VOLTAGE CHANNEL CHANNEL CHANNEL CHANNEL LEAST MOST LEAST MOST A A B B CHANNEL C CHANNEL C CHANNEL C CHANNEL C Register 1/2 Output Status (CHA and CHB) . See note 1 D0 D1 D2 D3 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 1 0 1 0 1 0 0 0 0 ALL THE OTHERS 0 1 1 0 0 0 0 0 1 OUT1 A/B OFF ON ON OFF OFF OFF OFF OFF ON OUT2 A/B OFF OFF OFF OFF ON ON ON OFF OFF OUT3 A/B OFF OFF ON ON ON OFF OFF OFF OFF OUT4 A/B OFF OFF OFF OFF OFF OFF ON ON ON OFF OFF OFF OFF Register 3 Current Reference (D/A OUTPUT) DO D1 0 0 1 1 0 1 0 1 6/16 REFER. VOLTAGE CHANNEL A 0.125 0.250 0.375 0.500 V V V V D2 D3 0 0 1 1 0 1 0 1 REFER. VOLTAGE CHANNEL B 0.125 0.250 0.375 0.500 V V V V L6285 REGISTER 4 (CHC). See note 2 D0 D1 D2 D3 X 0 1 0 1 1 0 1 0 0 1 0 1 X 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 0 0 1 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 OUT1 C OFF OFF VP GND GND VP CHOPPING; V2 LOW LEVEL VP CHOPPING; V2 HIGH LEVEL OFF VP OFF VP OUT2 C OFF OFF GND VP GND CHOPPING; V2 LOW LEVEL VP CHOPPING; V2 HIGH LEVEL VP OFF VP OFF VP Note 1: Low side DMOS status (DM1/2 in Fig. 4) Note 2: Bridge status (see Fig. 3): OFF = tristate; V P =, DM3/4ON; GND = DM1/2 ON Figure 3: CHC Chopping Characteristics 7/16 L6285 These two channels drive two unipolar stepper motors in chopping mode. The basic channel configuration is shown in Fig 4. by considering well known the PWM Current Control Loop behaviour here below only particular trick are underlined. During DM3 off period the low side DMOS DM1 and DM2 are switched on to reduce the power dissipation. Figure.4: Unipolar motor driver CHA (or CHB) 8/16 The drain overvoltages generated because of the stray inductance of the motor windings are limited by connecting the DZ1 external zener diode to the clamp pin.. The diodes CL1 and CL2 are integrated as far as the CL3 diode which limits the negative voltage at pin COM1.2. An internal RC network (1µs) is realized to filter the sensing resistor signal. L6285 CHC DC Motor Driver The DC motor driver is a DMOS full bridge with a PWM Open Loop Voltage Control. Fig.5 shows the theory of operation. The Cosc Capacitor is charged by a constant current source. The oscillating voltage value is from 0V to the V1 level internally fixed at V1 = 2/3 VS. The output duty cy- cle is controlled by the V2 voltage. The operational range of V2 is from 200mV to V1. Fig.3 shows the DMOS status during PWM: tON and tOFF bridge configurations. While the PWM Duty Cycle defines the motor speed (not controlled since the loop is open),the logic level of IN1 and IN2 can choose the direction of the motor. Figure.5: DC Motor Driver CHC 9/16 L6285 Oscillator For Clock and Reset Generation The oscillator block provides for two functions: 1)Generate an internal reset signal when the voltage at pin osc/res is below 1V. The reset signal switches off all the outputs and resets the logic registers. 2)Generate, when the pin osc/res is left free two syncro signals p1 and p2 for the clock of the PWM Current Control of the two stepper driver blocks The oscillator operates like the 555 concept in Figure 6: Oscillator Concept 10/16 which the capacitor voltage oscillates between 1/3VS 2/3VS (Fig. 6). The oscillator frequency is 2 times the chopping frequency in order to generate the two syncro signals at operative 20KHz PWM. The tCH = charge time of Cosc is defined by Rosc, VTH1 and VTH2 ( threshold voltages)and Cosc. The discharge time Tdsc is practically only defined by Cosc and the internal discarge resistor Rdsc. The tdsc is also the time lockout during which the RS FF cannot read the Comparator output (see Fig. 4) L6285 Charge Pump The charge pump circuitry generates the overvoltage needed to drive the gate of the high side output DMOS power transistors.It is realized by using two external capacitors (C1 and C2) and two integrated diodes that operate as a full wave recti- fier (see Fig. 7). The oscillator peak to peak output voltage is stored by C2 and summed to the Power Supply Voltage Vp.. The voltage present at the pin BOOT1, is then the overvoltage needed to supply the gate of the high side DMOS drivers. Figure 7: Charge Pump Circuit THERMAL PROTECTION The thermal protection shuts down the chip beA0TH A1TH 0 1 1 0 0 0 1 1 fore it can reach a dangerous temperature. Additional informations to the microprocessor are available at the A0TH, A1TH pins. THERMAL PROTECTION OK PREALARM ALARM NOT POSSIBLE APPLICATION INFORMATION A typical application circuit is shown in Fig.8. By this application it is possible to drive two unipolar stepper motors (M1,M2) and one DC motor (M3). As it can be seen, only two external Zener diodes (D1,D2) are needed to clamp the voltage transients generated by the stray inductance of the motor windings. This is recommended when the peak current is not more than three to four hundred mAmps. For a power supply voltage of VP=24V ±10%, D1=D2 must be 30V ±5%-1W (1N4751A or equivalent). Both the VP and the VS pins need bypass capacitors (C1,C2,C3); to supply the high-side DMOS (Source Transistors) at pin.15 ,only two external capacitors (C4,C5) complete the charge pump circuitry. The oscillator frequency, that is twice the chopping frequency for M1 and M2, is mainly defined by the network R6C6: fosc = [0.69 (Rch + Rdsc) Cosc ]-1 , where Rch = R6 ; R dsc = 600 ohm typ. CIRCUIT STATUS OPERATING OPERATING THERMAL SHUTDOWN At the same time, the lockout duration (or protection window) needed for a correct chopping behavior, is given by : Tlockout = 0.69 Rdsc Cosc The shown values (fig.8) give a nominal frequency a little bit more than 41KHz and a protection window of 1.4 µs roughly. The Schottky diode D3 and the pull-up resistor R5 driven via an opencollector transistor can generate the Reset function. The chopping current is sensed across R1 A/B; R2 A/B that must be of a not inductive type. The DC motor PWM Open Loop Voltage Control operates at a frequency defined by C7, charged with a typical constant current source (I = 240 µA), up to V1 = 0.67 VS. Since the discharge time is very short, it can be written : fosc = I / Cosc V1, where Cosc = C7. Tha values indicated in figure give a typical frequency of about 22 KHz. 11/16 L6285 Figure 8: Typical Application Circuit The duty cycle DC can be chosen between two possibilities (High and Low ) than can be defined externally by the resistors R7, R8 and R9: Fig.5 let well understand how to calculate the dividers that fix V2 H (wider ton ) and V2 L (wider toff ). It may be needed to drive stepper motors that require a higher peak current than told above. In this case each motor phase requires a particular application arrangement (see Fig.9b). In Fig.9a all the protection components are integrated with the exception of Z1. In Fig.9b the clamp of the voltage spikes generated by the stray inductance Ls is achieved using Transil protection T1 and T2 that works also as additional diodes during current recirculation at the phase change. The diode D1, externally connected, is recommended at the highest working current levels and/or when the supplied voltage (plus Back EMF) at the end of the motor winding is too much unbalanced. Figure 9a: Output Configuration as it is obtained by the Application Circuit Figure 9b: Output Configuration at Higher Operating Currents 12/16 L6285 THERMAL CHARACTERISTICS The cooling of the device is obtained by soldering its ground pins on a proper p.c.b copper side , acting as a true heatsink. By considering four squared side as in Fig.10, the junction to ambient thermal resistance has been measured (see Fig.11). The typical transient thermal resistance versus values of single pulse width of power is shown in Fig.12. In general these thermal characteristics are very important to the designer to optimize the L6285 applications. Figure 10: Four ”on board” Square Heatsink Figure 11: Typical Rth j-amb vs. lenght ”l” (Fig. 10) Figure 12: Typical Transient Thermal Resistance vs. Time or Pulse Width 13/16 L6285 SDIP42 PACKAGE MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. MAX. 5.08 0.20 A1 0.51 0.020 A2 3.05 3.81 4.57 0.120 0.150 0.180 B 0.36 0.46 0.56 0.0142 0.0181 0.0220 B1 0.76 1.02 1.14 0.030 0.040 0.045 c 0.23 0.25 0.38 0.0090 0.0098 0.0150 D 37.85 38.10 38.35 1.490 1.50 1.510 E 15.24 16.00 0.60 E1 12.70 14.48 0.50 13.72 0.629 0.540 e 1.778 0.070 e1 15.24 ‘0.60 0.570 e2 18.54 0.730 e3 1.52 0.060 L 2.54 3.30 3.56 0.10 0.130 0.140 E A2 A L A1 E1 B B1 e e1 e2 D c E 22 F 42 .015 0,38 Gage Plane 1 e3 21 e2 SDIP42 14/16 L6285 PLCC44 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 17.4 17.65 0.685 0.695 B 16.51 16.65 0.650 0.656 C 3.65 3.7 0.144 0.146 D 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 E 0.68 14.99 0.027 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 F 0.46 0.018 F1 0.71 0.028 G 0.101 0.004 M 1.16 0.046 M1 1.14 0.045 15/16 L6285 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 16/16