L7203 ® SMOOTH DRIVE SPINDLE MOTOR FOR OPTICAL DRIVE APPLICATION WITH POWER INTEGRATED SMOOTH DRIVE SYSTEM 1.8A DRIVE PEAK CAPABILITY SLEW RATE CONTROL INDUCTIVE SENSE START-UP ROUTINE THERMAL SHUTDOWN SUITABLE FOR 5V AND 12V APPLICATION ONLY ONE HALL SENSOR IS REQUIRED DESCRIPTION The L7203 SPINDLE MOTOR IC includes a three phase brushless spindle motor controller and the power stage in switching mode. The device is designed for both 5V and 12V OPTICAL DRIVE application requiring up to 1.8A peak of current. The device is realized in BCD5, a 0.7 µm Mixed technology. The spindle motor position detection is carried out by means of a single comparator with hysteresis. In the start-up phase the "inductive sense SO20 SSO24 ORDERING NUMBERS: L7203 (SO20) L7203S (SSO24) start up method" is used to detect the rotor position, determining the direction of starting rotation. This procedure is implemented by a logic circuit on chip. The device applies three sinusoidal voltages to the motor coils. This is obtained through the application of the BLOCK DIAGRAM PRS LOW VOLTAGE DETECTOR SRC AGND DGND April 2001 1/13 L7203 DESCRIPTION (continued) SMOOTH DRIVING concept. It is based on the idea of driving the motor winding through 3 sinusoidal voltages dephased of 120 degrees. The motor is controlled in voltage mode, so no current control compensation network is required. Each profile is digitally described by 36 bytes stored in a ROM memory. These sinusoidal signals are modulated by multiplying each sample by a value stored in the KVAL register. Using this kind of profiles it is possible to obtain great advantages such as torque ripple and acoustic noise reduction and lower EMI. An easier track following is ensured, since vibration are reduced. The clock signal on the chip can be synchronized to the external application clock signal. An internal circuit can limit the current. The threshold is fixed with a internal 0.2 V reference. The device generates: - a current generator to define output voltage slew rate - a 3.3 V reference to bias hall sensor. - the HFG open drain output signal for speed regulation. The device includes : - a circuit for thermal shutdown with hysteresis. - a low voltage detector In the STANDBY state the main functions of the device are turned off, in order to minimize the power consumption. The STANDBY state of the device is imposed by: - Thermal shutdown - stand by signal from µP PIN CONNECTIONS SSO24 SO20 STB 1 20 FSYS PRS 2 19 HFG VM 3 18 SRC U 4 17 DGND V 5 16 AGND W 6 15 VCC RF 7 14 ISR RF1 8 13 HBIAS H+ 9 12 PHS H- 10 11 PWMIN D98IN928A PRS 1 24 STB N.C. 2 23 FSYS N.C. 3 22 HFG VM 4 21 SRC U 5 20 DGND V 6 19 AGND N.C. 7 18 VCC W 8 17 ISR RF 9 16 H BIAS N.C. 10 15 PHS RF1 11 14 PWMIN H+ 12 13 H- D01IN1174 2/13 L7203 PIN DESCRIPTION PIN DESCRIPTION TYPE POWER AND GROUND VM Supply voltage for power stages +12/5V P12 Supply for 5V core P5 DGND Logic ground G AGND Analog ground G VCC DIGITAL PIN PWMIN PWM input signal to calculate kval IC5 Fsys System frequency IC5 PHS Phase Shift Pin IC5 PRS Prescaler Pin IC5 STB Start and Stop signal ZD5 HFG Open Drain F-Generator signal from Spindle Motor OD5 HALL SENSOR BIAS H+, H- 3.3V reference to bias Hall sensor OA5 Hall sensor differential input IA5 INDUCTIVE SENSE REFERENCE ISR Inductive sense reference IA5 MOTOR CONTROL OUTV Winding output U OA12 OUTV Winding output V OA12 OUTW Winding output W OA12 RF Current sense resistor (force) OA12 RF1 Current sense resistor (sense) IA5 SLEW RATE CONTROL SRC Slew Rate Control OA5 INPUT DEFINITION IC5 Input CMOS, 3.3-5V capability with hysteresis ZD5 Bidirectional, open drain, 3.3-5V capability OD5 Output, open drain, 3.3-5V capability IA5 Input, Analog, 5V OA5 Output, Analog, 5V OA12 Output, Analog, 12V P12 Power 12V / 5V P5 Power 5V G Ground 3/13 L7203 THERMAL DATA Symbol Rth j-pins Parameter Thermal Resistance Junction to Pins Max. Value 16 Unit °C/W Rth j-amb Thermal Resistance Junction to Ambient Max. 90 °C/W Value -20 to 80 0 to 150 Unit °C °C ABSOLUTE MAXIMUM RATINGS Symbol Parameter Tamb Top Ambient Temperature Operating Temperature Tsmin VM Minimum Thermal Circuit Threshold 140 °C -0.3 to 15 -0.3 to 7 Vdc Vdc -0.3 to 17 -0.3 to VCC+0.3 Vdc Vdc 1 W VCC U, V, W, (low side drive =off) PD1 ESD TSTG IOLHFG IPeak PWMIN, PHS, FSYS, TEST, STB, HFG, BIAS, H+, H-, RF1, RF, ISR, PORPin Power dissipation at sustained operation with a package Rthj-amb at 90°C Susceptibility Storage Temperature HFG open drain current Motor Peak Current 2000 Vac -55 to 150 10 °C mA 1.8 A DC ELECTRICAL CHARACTERISTICS ( VCC = 5V; VM = 12V; Tamb = 25°C unless otherwise specified) Symbol SUPPLY VCC VM VM IVcc VVM Parameter Supply 5V operating range Supply 12V operating range Supply 5V operating range VCC Supply Current VM Supply Current PWMIN, PHS, PRS, Fsys ViL Input Low Voltage ViH Input High Voltage ViHYS Input Hysteresis Iz Leakage Current STB ViL Input Low Voltage ViH Input High Voltage VOL Open Drain Output ViHYS Input Hysteresis Iz Leakage Current HFG Open Drain Output VOL Iz Leakage Current 4/13 Test Condition (note 1) Min. Typ. 4.25 10.2 4.25 VCC = 5.75; fsys = 20MHz STB = 0 (bias pin open) STB =1 VM = 13.8 STB = 0 STB =1 Max. Unit 5.75 13.8 5.75 1.3 20 1 7 V V V mA mA mA mA 1 V V mV µA 2.2 100 VCC = 5.75 -10 +10 1 VCC = 5.75, Therm off -10 +10 V V V mV µA IOL = 2mA VCC = 5V VCC = 5.75, HFG hiz -10 0.4 +10 V µA 2.2 IOL = 2mA VCC = 4.25V 0.4 100 L7203 DC ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter BIAS VBIAS BIAS Output Voltage IBmax Max Output Current H+, HVH± H+ H- Input Voltage Range IH± Input Leakage Current VOFFISR Comparator Offset VHy Comparator Hysteresys MOTOR POWER STAGE RDSON High and Low side FET on Resistance IU/V/W Spindle Output Leakage Current CURRENT LIMITER Internal Reference Voltage for VLim current limitation Comparator Offset VOFFLim THERMAL PROTECTION TS Shutdown temperature UNDERVOLTAGE Vccth (fall) Undervoltage threshold (fall) Vccth (rise) Undervoltage threshold (rise) Vccth (hys) Undervoltage threshold (hys) SYSTEM FREQUENCY System frequency fsys Test Condition VCC = 5V; 5mA < I < 15mA Vin = 0, +VCC Min. Typ. Max. Unit 3.25 3.75 15 V mA 0 -10 -15 4 2.5 +10 +15 15 V µA mV mV 2 Ω 100 µA 260 mV -15 +15 mV 130 170 °C 3.4 - V V V 20 34 MHz MHz 500 V µA KΩ 2 V Tj = 125; VM = 4.25V I = 1.2A VM = 15V 220 2.9 PRS = 0 PRS = 1 240 0.1 10 20 SLEW RATE CONTROL VSRC SRC Output Voltage ISRC Output Current RSRC External Resistor on pin SRC ISR VISR Input Range 1.25 10 0 Note 1: An SMBJIZAVCL-TR is recommended to clamp VM in case of high impedance on power supply line. FUNCTIONAL DESCRIPTION STB-Thermal protection Controller drive STB pin by open drain. When Thermal Shutdown is excited, the device force this pin LOW. Controller will manage STB to do a re-start. When STB is LOW all the drivers are shut off. Hall Sensor Bias A regulator on chip supply a 3.3V+-10% refer- ence on pin Bias. This regulator can supply an output current up-to 15 mA. Figure 1. R PULL UP STB OVER TEMP D98IN880 5/13 L7203 Figure 2. The start up is a procedure allowing to start the motor avoiding any backrotation. This procedure is realized by a customized logic on chip (no modification required in the external microprocessor software). For the Motor Connection please refer to the Fig. 4. Current Limiter BIAS R1 ISR R2 - TIMER + RF1 Figure 4. Motor Connections. D98IN881 Figure 3. MOTOR + CURRENT LIMIT INTERNAL REFERENCE R TO THE POWER STAGE SET EVERY 255 CLOCK CYCLE MOTOR COIL B W MOTOR COIL C Bemf coil A Hall sensor L7203 S 0.2V V ˚ RF1 MOTOR COIL A 30 U D98IN882 H+ H+ H- H- Bemf coil B Bemf coil C D01IN1175 The current limiter aim is to avoid that the current in the motor winding overides a fixed threshold value. The voltage input at the pin RF1 is compared with an internal 0.2V reference. When the current exceeds the Ilimit value a flipflop is reset masking (through a combinational logic) the signal to the power windings. Rotor Position Detector This block is connected to the Hall Sensor Output. A comparator with hysteresis receives the sinusoidal hall-sensor signal and generates a squared signal HOUT. The Zero-Cross signal is generated starting from the HOUT signal as in fig. 5. The HOUT signal can be read from the microprocessor on the output open drain pin HFG. Frequency multiplier The Frequency Multiplier generates the memory scan frequency (Fscan) starting from the ZeroCross (ZC) signal from the Rotor Position Detector block. The scan frequency relates to the rate of the samples of the input signals. The number of wave samples in a period T is 36, so this circuit generates 36 pulses between 2 Zero Crossing. Inductive Sense Start Up Block The inductive sense method allows to determine the position and the direction of the starting rotation of the motor. With the rotor at rest, a voltage Vn is applied subsequently to two motor phases, according to this sequence: UW, VW, VU, WU, WV, UV. A timer measures the rise time dT to reach the reference current ISR in each phase. This reference is fixed on the pin ISR with a resistor divider between the pin BIAS and GND. Through a comparator is possible to determine the phase which has the minimum rise time and so the rotor position is univocally determinated. Figure 5. H+ + H- HOUT COMPARATOR WITH HYSTERESIS HOUT ZC D98IN883A Figure 6. T ZC Fscan 1 6/13 2 3 4 5 6 7 8 35 36 D98IN879 L7203 Fscan has a frequency 36 times of (1/T). The Fscan is generated from the Zero-cross frequency measured at the previous cycle. So, if the motor speed changes, the zero-cross is not constant, the Frequency Multiplier adjusts the scan clock, ensuring the synchronization between the Zero-Cross signal and the sinusoidal output voltage. Memory and Memory Scan The memory stores 3x36 samples describing 3 signals. As each sample is represented in a byte, it may have a value in the range 0 to 255. The shape of these three signals are designed in order to generate three sinusoidal voltages across the Motor coils ensuring the highest performances in term of power losses and motor speed. The shape of the signals are reported in fig. 7. In Fig 8 is swown the "differential" voltage across the motor coil U and the motor coil V. Obviously, the voltage shape across the motor coil U and W and the voltage across the motor coil V and W are also sinusoidal and dephased of 120 and 240 degrees respect the voltage shown in fig. 8. The Memory and Memory scan block receives the scan clock, and at each clock provides the sample addressed by an internal address register. Figure 7. D98IN930 V U W Figure 8. D98IN931 This register is initialized with the memory address of the wave sample synchronized with the Zero-Cross signal. The maximum efficiency (i.e. the maximum motor speed for a particular value of current) for the motor driving may be reached ensuring a particular value PH of dephase between the Zero-Cross signal and the voltage output signal. This value is written by the external controller using PHS pin (see Phase Shift Block section). Kval Block and PWM interface This unit contains a register storing the Kval value. The Kval value represents a multiplying factor to modulate the 3 profile signals amplitude and it is generated starting from the PWMIN signal coming from the external system controller. The Kval block receives the PWMIN signals and calculates the Kval value through the reference triangular signal. This signal is generated by a 10 bit counter that starts counting from 1023 to 0 at Fsys rate, and then restart up to 1023. The resolution is ±1LSB. Internal triangular wave is synchronized with the PWMIN falling edge. The PWMIN signal contains information regarding both the amplitude and to the sign of the control variable. If the duty cycle is less than 50% the Kval is in the range (-1023, -1), while if the duty cycle is equal or greater than 50% the kval is in the range (0, 1023). A negative Kval value (i.e. PWM duty cycle from 0 to 50%) indicates an active brake and generates a 180 degree shift in the voltage profile scan. The rising edge of the PWMIN signal determines the kval on the reference triangular waveform. If the PWMIN signal is stable during the entire cycle, the Kval is evaluated according to the following rule: - PWMIN signal stable to 1 -> Kval = +1023 - PWMIN signal stable to 0 -> Kval = -1023 In order to ensure the synchronization between Figure 9. 1023 U-W INTERNAL REFERENCE SIGNAL 0 PWMIN KVAL < 0 KVAL > 0 KVAL < 0 D98IN884 7/13 L7203 the PWMIN signal and the internal signals, the PWMIN signal rate must be calculated by the external microcontroller using the same frequency signal provided to the chip through the pin fsys. Digital Multiplier This unit contains a multiplier executing the multiplication of each sample provided by the memory by the value stored in kval register. The output value is a 10-bit word, plus the sign bit. Figure 10. PWM Converter The PWM converter receives from the digital multiplier three 10 bit digital number and converts it into three PWM signals. A counter counts up (from 0 to 255) and down (from 255 to 0) at the Fsys rate in continuos mode. Three 8-bit input registers are written with the 8 most significant bit of the word to be converted and compared to the counter value. The comparator output is: 510 Tsys 255 COUNTER 0 OUTPUT COMPARATOR D98IN885A Figure 11. 8 MSB OUTPUT MULTIPLIER OUTPUT COMPARATOR OUTPUT PWM: LSB 00 01 10 11 WHERE: A HALF FSYS PERIOD A FSYS PERIOD 8/13 D98IN886 L7203 - 0, if the input value is smaller than the counter output - 1, if the input value is equal or greater than the counter output The comparator output is "adjusted" with a combinational logic with the 2 low significant bit of the word to be converted in order to reach a 10 bit precision. The comparator output duty cycle is extended with a half fsys period for every low bit step how is showed in the figure 11. Phase Shift Block This block regulates the phase of the driving sig- nal to control the dephasing between the ZeroCross signal and the voltage sinusoidal output signal. It is possible to demonstrate that the maximum efficiency for the motor driving may be reached ensuring a particular value PH of dephase between the Zero-Cross signal and the voltage output signal. The Phase Shift BLock, starting from the PHS input signal synchronize the wave output with the Zero-Cross signal to ensure the optimum dephase. The PHS signal expresses the phase shift through the duration of its value according to the following rule: Table 1. PHS on time µs (Tsys = 50ns) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 16.0 16.2 16.4 16.6 16.8 17.0 17.2 17.4 NPhase decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 . . . . 80 81 82 83 84 85 86 87 . . . . Phase Shift (degree) bit 00000 000 00000 001 00000 010 00000 011 00000 100 00000 101 00000 110 00000 111 00001 000 00001 001 00001 010 00001 011 00001 100 00001 101 00001 110 00001 111 000010 000 000010 001 000010 010 000010 011 000010 100 000010 101 000010 110 000010 111 . . . . 001010 000 001010 001 001010 010 001010 011 001010 100 001010 101 001010 110 001010 111 . . . . LATCH 1.25 2.50 3.75 5.00 6.25 7.50 8.75 10 11.25 12.50 13.75 15.00 16.25 17.50 18.75 20 21.25 22.50 23.75 25.00 26.25 27.50 28.75 . . . . 100 101.25 102.50 103.75 105.00 106.25 107.50 108.75 . . . . 9/13 L7203 Table 1. (continued) PHS on time µs 56.0 56.2 56.4 56.6 56.8 57.0 57.2 57.4 > 57.6 NPhase decimal 280 281 282 283 284 285 286 287 288 PHS on = tsys * 4 * Nphase where: tsys = 50ns if fsys = 20MHz The resulting PHASE SHIFT value is: PHASE SHIFT = Nphase(8:3) x 10 + Nphase(2:0) x 1.25 For istance if Nphase = 00011 110 PHASE SHIFT = 3 x 10 + 6 x 1.25 = 37.5 Phase Shift (degree) bit 100011 000 100011 001 100011 010 100011 011 100011 100 100011 101 100011 110 100011 111 100100 000 350 351.25 352.50 353.75 355.00 356.25 357.50 358.75 0 Figure 13. Phase relation between OUTPUT sinusoidal voltage (PWM_IN > 50%) and Hall sensor signal writin Phase shift = 0° (default value) Hall sensor OUT U OUT W Low Voltage Detector This circuit detects if VCC is lower than a fixed threshold. If this event happens the internal logic is resetted and the output FETS are forced in High impedance. Slew Rate Control Circuit This circuit fixes the slew rate for the output stage in order to reduce EMI. A reference current is generated by means of an internal reference voltage and an external resistor. The ISRC is used to fix slew rate with a linear law: OUT V Figure 14. Phase relation between OUTPUT sinusoidal voltage (PWM_IN > 50%) and Hall sensor signal writing Phase shift = 30° Hall sensor OUT W OUT U 30° Figure 12. ISRC = VREF / R ext VREF + SRC R ext SLEW RATE = RSLR/ISRC ⋅ VREF REXT Rext recommended value >10KΩ Prescaler Pin The PRS Pin should be forced to ground when the FSYS frequency is lower (or equal) than 20MHz and should be forced to VCC when FSYS frequency is higher than 20MHz, in order to set the correct timing during the inductive sense, start up and resynchronization phases. Example of different phase shift settings are shown in the following pictures. 10/13 OUT V Figure 15. Phase relation between OUTPUT sinusoidal voltage (PWM_IN > 50%) and Hall sensor signal writing Phase shift = 330° OUT U Hall sensor 30° OUT V OUT W L7203 mm inch OUTLINE AND MECHANICAL DATA DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 SO20 K 0˚ (min.)8˚ (max.) L h x 45˚ A B e A1 K C H D 20 11 E 1 0 1 SO20MEC 11/13 L7203 mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 2.00 A1 0.05 A2 1.65 B (2) 0.079 0.002 1.85 0.060 0.079 0.22 0.38 0.009 0.015 C 0.09 0.25 0.003 0.01 D (1) 7.9 8.2 8.5 0.31 0.32 0.33 E 7.4 7.8 8.2 0.29 0.30 0.32 E1 (1) 5.0 5.3 5.6 0.20 0.21 0.22 e L 1.75 0.65 0.55 L1 0.75 0.025 0.95 0.022 1.25 k OUTLINE AND MECHANICAL DATA MAX. 0.029 0.004 0.05 0˚ (min), 4˚ (typ), 8˚ (max) ddd 0.1 0.004 (1) “D and E1” dimensions do not include mold flash or protusions, but do include mold mismatch and are mesaured at datum plane “H”. Mold flash or protusions shall not exceed 0.20mm in total (both side). (2) “B” dimension does not include dambar protusion/intrusion. SSO24 Shrink Small Outline Package DATUM PLANE H 0.25mm SEATING PLANE C GAGE PLANE A2 A K B e A1 ddd C C L E1 L1 D 24 13 E 1 1 2 SSO24ME 0053237 12/13 L7203 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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