STMICROELECTRONICS L9346PD

L9346

QUAD INTELLIGENT POWER LOW SIDE SWITCH
QUAD POWER LOWSIDE DRIVER WITH 2 x 5A
AND 2 x 3A OUTPUT CURRENT CAPABILITY
LOW RDSON TYPICALLY 200mΩ AND 300mΩ
@ Tj = 25°C
INTERNAL OUTPUT CLAMPING STRUCTURES WITH VFB = 50V FOR FAST INDUCTIVE LOAD CURRENT RECIRCULATION
LIMITED OUTPUT VOLTAGE SLEW RATE
FOR LOW EMI
PROTECTED µP COMPATIBLE ENABLE
AND INPUT
WIDE OPERATING SUPPLY VOLTAGE
RANGE 4.5V TO 32V
REAL TIME DIAGNOSTIC FUNCTIONS:
- OUTPUT SHORTED TO GND
- OUTPUT SHORTED TO VSS
- OPEN LOAD MEASURED IN ON AND OFF
CONDITION
- LOAD BYPASS DETECTION
- OVERTEMPERATURE
DEVICE PROTECTION FUNCTIONS:
Power SO20
Chip
ORDERING NUMBERS: L9346PD (power SO20)
L9346DIE (chip)
- OVERLOAD DISABLE
- REVERSE SUPPLY VOLTAGE
PROTECTED VS UP TO -2V
- SELECTIVE THERMAL SHUTDOWN
DESCRIPTION
The L9346 is a monolithic integrated quad low
side driver realized in an advanced Multipow-
BLOCK DIAGRAM
IN1
Channel1
OUT1
D1
VS
EN
Output
OUT4
52V
Control
R IO
Overtemp
IN4
Delay
R
Q
S
Timer
Overload
D4
Diagnostic
Openload
Control
Channel4
IN2
Channel2
OUT2
D2
IN3
Channel3
OUT3
D3
G ND
May 2000
1/13
L9346
DESCRIPTION (continued)
erBCD mixed technology. The device is intended
to drive valves in automotive environment.
The inputs are µP compatible. Particular care has
been taken to protect the device against failures,
to avoid electromagnetic interferences and to offer extensive real time diagnostic.
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
VS
DC Supply Voltage
Parameter
Conditions
-2 to 32
V
VSP
Supply Voltage Pulse (duration <200ms)
-2 to 45
V
10
V/µs
 dVS 
 dt 


Supply Voltage Slope
VIN, EN
Input Voltage
 I  10mA
-2 to 16
V
Diagnostic DC Output Voltage
 I  50mA
-0.3 to 16
V
VD
VODC
DC Output Voltage
-0.3 to 45
V
IO1, 2
DC Output Current Out 1, 2
5
A
IO3, 4
DC Output Current Out 3, 4
3
A
IOR1, 2
Reverse Output Current
-5
A
IOR3, 4
Reverse Output Current
EO1, 2
Switch-off Energy for Inductive Loads
tEO = 250µs,1)
TjEO
GND Potential Difference
A
mJ
T = 5ms
30
mJ
Tj = -40 to 150°C
±0.3
V
∑t ≤ 30 min
175
°C
∑t ≤ 15 min
190
°C
EO3, 4
∆VGND
-3
50
Juntion Temperature During Switch-off
Tj
Juntion Temperature
-40 to TjDIS
°C
Tstg
Storage Temperature
-55 to 150
°C
TjDIS
Thermal Disable Junction Temp. Threshold
180 to 210
°C
The device is ESD protected, tested according to MIL883C with ±2KV.
1)
Note : t EO is the clamping time (see fig.1)
PIN CONNECTION
H e at s in k c o n ne c te d to pin s 1, 1 0, 1 1 , 2 0
2/13
PG N D
PG N D
OUT1
O U T4
D1
D4
IN 4
IN 1
VS
EN
NC
GND
IN 3
IN 2
D2
D3
OUT2
O U T3
PG N D
PG N D
L9346
THERMAL DATA
Symbol
Parameter
Thermal Resistance junction to case
R th j-c
Value
Unit
3
K/W
PIN FUNCTIONS
N.
Name
1
GND
Function
2
Out 1
Output 1 (5A)
3
D1
Diagnostic 1
4
IN 4
Input 4
Power Grounded
5
VS
Supply Voltage
6
NC
Not Connected
7
IN 3
Input 3
8
D2
Diagnostic 2
9
Out 2
Output 2 (5A)
10
GND
Power Ground
11
GND
Power Ground
12
Out 3
Output 3 (3A)
13
D3
Diagnostic 3
14
IN 2
Input 2
15
GND
16
EN
17
IN 1
Input 1
18
D4
Diagnostic 4
19
Out 4
Output 4 (3A)
20
GND
Power Ground
Signal Ground
Common Enable
Figure 1: tEO Clamping Time
VO 1 - 4
VOC L
VS
t
t EO
T
3/13
L9346
Figure 2: Pad Position (Chipsize 4.95 x 3.88)
ESD
4/13
L9346
Pad Coordinates (Reference point X = 0, Y = 0: Center of die)
Pat opening center position
Pad Nr.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Pad Name
Size in (µm)
PG3
PG3
PG2
PG2
OUT2
OUT2
D2
IN3
VS
IN4
D1
OUT1
OUT1
PG1
PG1
PG4
PG4
OUT4
OUT4
D4
IN1
EN
GND
IN2
D3
OUT3
OUT3
Test pad
178 x 280
178 x 280
178 x 280
178 x 280
280 x 178
280 x 178
178 x 178
178 x 178
178 x 178
178 x 178
178 x 178
280 x 178
280 x 178
178 x 178
178 x 178
178 x 178
178 x 178
280 x 178
280 x 178
178 x 178
178 x 178
178 x 178
178 x 178
178 x 178
178 x 178
280 x 178
280 x 178
Size
Gate 2
VTERM2
IOLRED
ESD
VTERM1
GATE1
GATE4
VTERM4
VTERM3
GATE3
d = 102
d = 102
d = 102
178 x 178
d = 102
d = 102
d = 102
d = 102
d = 102
d = 102
Description
Power Ground 3
Power Ground 3
Power Ground 2
Power Ground 2
Output 2 5A
Output 2 5A
Diagnostic 2
Input 3
Supply Voltage
Input 4
Diagnostic 1
Output 1 5A
Output 1 5A
Power Ground 1
Power Ground 1
Power Ground 4
Power Ground 4
Output 4 3A
Output 4 3A
Diagnostic 4
Input 1
Common Enable
Signal Ground
Input 2
Diagnostic 3
Output 3 3A
Output 3 3A
Coordinates in (µm)
X
Y
2286.5
2286.5
2286.5
2286.5
1472.5
1722.5
1036
648
-260
-648
-1036
-1722.5
-1472.5
-2286
-2286
-2286
-2286
-1448
-1656
-970
-582
-194
194
582
970
1656.5
1448.5
X
1175
506
98
-842
-844
-1644
-1644
-1644
-1644
-1644
-1644
-1644
-844
-842
98
506
1175
865
1644
1644
1644
1644
1644
1644
1644
1644
865
Y
1447
1260
449.5
260
-1260
-1447
-1381
-1194.5
1194.5
1381
-1612
-1600
-1455.5
-1644
-1600
-1612
1600
1600
1600
1600
5/13
L9346
ELECTRICAL CHARACTERISTICS (Operating Range)
The electrical characteristics are valid within the below defined operating range, unless otherwise specified.)
Symbol
VS
Tj1
Tj2
Parameter
Test Condition
Board Supply Voltage
Junction Temperature
Junction Temperature
Σt ≤ 15min
2)
over life time
Min.
Typ.
Max.
Unit
4.5
-40
150
12
32
150
TjDIS
V
°C
°C
NOTE:
2)
Parameters guaranteed by correlation
ELECTRICAL CHARACTERISTICS (VS = 4.5 to 32V; -40°C ≤ Τj1 ≤ 150°C < Tj2 ≤ ΤjDIS, unless otherwise specified.)
Symbol
Parameter
Test Condition
DC Supply Current Off
DC Supply Current On
EN = 1.0V
VS ≤ 14V; VIN, VEN = 2V
Min.
Value Tj1
Typ.
Max.
Value Tj2
Min.
Max.
Unit
Supply
IVS OFF
IVS ON
5
8
10
mA
mA
ID ≤ 3mA
0.65
1.0
1.5
V
VD = 14V3)
0.1
2
20
µA
Diagnostic Outputs D 1 - D 4
VDL
IDLE
Diagnostic Output Low
Voltage
Diagnostic Output
Leakage Current
Outputs Out 1 - Out 4
VOUV 1-4
Open Load Voltage
Threshold
Hysteresis
VIN = 1V
2-3, 4-1, 3-2
Open Load Difference
Voltage Threshold
VIN1,4/2,3 = 1V,
4.5V ≤ VOc ≤ 16V,
4.5V ≤ VS ≤ 16V,
VOc = output voltage of
other channel
VOUV hys 1-4,
Open Load Hysteresis
VOUV hys 1-4
∆VOUV 1-4,
0.525 x
VS
VOC 1.0V
0.55 x 0.575 x 0.5 x VS 0.65 x
VS
VS
VS
0.003 x
VS
VOC VOC VO C VOC 1.25V
1.5V
0.8V
1.7V
40
V
V
V
mV
2-3, 4-1, 3-2
IOUC 1, 2, 3, 4
IOOC 1, 2
IOOC 3, 4
VOCL
SON,OFF
R IO
RDSON 1, 2
RDSON 3, 4
Open Load Current
Threshold
Over Load Current
Threshold
VEN = VIN = 2V;
VS = 6.5 to 16V
VS > 6.5V;
VOUT = 32V
Output Voltage During
Clamping
Output (fall, rise) slew
rate
Internal Output Pull
Down Resistor
Output On Resistance
IOCL ≥ 200mA
4)
IOUC ≤ IO ≤ IOOC
VEN = 1V
Tj = 25°C
Tj = 150°C
VS > 9.5V, IO1,2 = 2A
Tj = 25°C
Tj = 150°C; IO3,4 = 1.3A
NOTE:
2)
Parameters guaranteed by correlation
3)
The diagnostic output is short circuit protected up to VD = 16V
4)
VS = 9 to 16V
6/13
160
320
480
580
5
3
45
10
6
52
60
400
1500
2850
10
20
40
200
300
500
mΩ
300
450
750
mΩ
4
2.4
200
mA
A
A
V
3500
V/ms
50
KΩ
L9346
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Value Tj1
Typ.
Max.
Value Tj2
Min.
Max.
Unit
Inputs IN1-4, EN
VIN,EN L
Logic Input/Enable Low
Voltage
Logic Input/Enable High
Voltage
Logic Input Hysteresis
Input Sink Current
Enable Sink Current
VIN,EN H
VEN,IN hys
IIN
IEN
-0.3
1
0.8
IN, EN
2.0
16
VIN = 2 to 12V5)
0.2
10
10
0.4
30
20
0.8
60
40
4
15
25
30
65
V
V
240
240
V
µA
µA
90
µs
µs
µs
Timing
tD ON
tD OFF
Output Delay ON Time
Output Delay OFF Time
Diag. Delay Output
OFF Time
Diagnostic Open Load
Delay Time
Diagnostic Overload
Delay Switch-OFF Time
Enable ON Time
Enable OFF Time
tDH-L, Diag
tD IOU
tDOL
tD EN ON
tD EN OFF
6)
Fig. 7
Fig. 7
6)
Fig. 6
6)
5
8
VS = 9 to 16V, Fig 8
IO ≤ IOUC
VS = 9 to 16V, Fig 8
IO > IOOC
6)
Fig. 7
6)
Fig. 7
50
8
50
µs
160
300
µs
4
4
25
25
µs
µs
NOTE:
5)
6)
Open pins (EN, IN) are detected as low
VS = 9 to 16V ∧ IOUC ≤ IO ≤ IOOC
DIAGNOSTIC TABLE
CONDITIONS
EN
IN
OUT
Normal Function
L
X
off
DIAG.
L
H
L
off
L
H
H
on7)
H
GND short
VOtyp < 0.55VS
L
X
off
H
Load bypass
∆VO1-4/2-3 ≥ 1.25V
H
L
off
H
Open Load
IO1,2,3,4typ < 320mA
H
H
on7)
L
X
X
off
L
H
H
off
L
DC don’t care
DC don’t care
Tjtyp ≥ 190°C Overtemperature
Over Load
8)
IOmin 1,3 > 5A
IOmin 2,4 > 3A
Reset and Overtemperature Latch
X
NOTE:
7)
For VS = 4.5 to 6.5V, IO ≤ 2A, the diag. table is valid
If one diag. status shows the overtemperature, recognition, in parallel this output will be switched OFF internally.
The corresponding channel should be switched OFF additionally by its input signal, otherwise the overload latch will be set aftert DOL is passed.
This behaviour is related to the overdrop sensing which is used as over load recognition.
The overtemperature is latched (DIAG = L) until the level of the IN signal changes to low.
8)
7/13
L9346
CIRCUIT DESCRIPTION
The L9346 is a quad low side driver for inductive
loads like valves in automotive environment. The
internal pull down current sources at the ENABLE and INPUT pins assure in case of open input conditions that the device is switched off. An
output voltage slope limitation for du/dt is implemented to reduce the EMI. An integrated active
flyback voltage limitation clamps the output voltage during the flyback phase to 50 V.
Each driver is protected against short circuit at
VOUT < 32V and thermal overload. In short circuit
condition the output will be disabled after a short
delay time tDOL. The thermal disable for TJ >
180°C of the output will be reseted if the junction
temperature decreases about 20°C below the disable threshold temperature.
The overtemperatureinformation is stored until IN = L.
For the real time error diagnosis the voltage and
the current of the outputs are compared with internal fixed values VOUV for OFF and I OUC for ON
conditions to recognize open load (RL ≥ 20 KΩ,
RL > 38Ω) in OFF and ON conditions.
Also the output voltages VO1 - 4 are compared to
each other output in OFF condition with a fixed
offset of ∆VOUV to recognize load bypasses. To
suppress the ∆VOUV diagnoses during the flyback
phases of the compared output, the ∆VOUV diagnostic includes a latch function.
Reaching the flyback clamping voltage VOCL the
diagnostic signal is reseted by a latch. To activate
again this kind of diagnostic a low signal at the
correspondent INPUT or the ENABLE pin must
be applied (see also Fig.3). The outputs 1 and 4
are compared for ∆VOUV and also outputs 2 and 3
are compared.
The diagnostic output level in connection with different ENABLE and INPUT conditions allows to
recognize different fail states, like overtemp, short
to VSS, short to GND, bypass to GND and disconnected load (see diagnostic table).
The diagnostic output is protected against short
circuit. Exceeding the over load current threshold
IOOC, the output current will be limited internally
during the diagnostic overload delay switch-off
time tDOL.
The device complies the ISO pulses imposed to
the supply voltage of the valves without any failures of the functionality.
Figure 3. Diagnostic Overload Delay Time
V IN
5V
t
IO
I OOL
5A
3A
I OUC
t
t DOL
VD
5V
t
8/13
L9346
Figure 4. OUTPUT SLOPE (Resistive load for testing)
V
IN
5V
V
(EN)H
V (EN)L
t
t D ON
V
t D OFF
tD E N O F F
tD E N O N
OUT
VS
0.85VS
0.85 VS
S ON
VO U V
S OFF
0.15 VS
t
V
DIAG
V
0.5 V
D
D
t
t
D H -L
D ia g
Figure 5. TIMING (tDENON, tDON, tDENOFF, tDOFF)
E N , IN
VO N
0.85 x VO UT
0.15 x V O U T
t D EN ON , t D O N
t DE N OFF , t DO FF
9/13
L9346
Figure 6. TIMING (tDOL, tDIOU)
IN
VON
I OOC
I OUC
VD
t DIOU
t DOL
Open load current
Figure 7. BLOCK DIAGRAM - Open Load Voltage Detection
V
Batt.
L1 (L2)
OUT1
( OU T2)
L4 (L3)
OUT4
(OU T3)
IN 1
IN 4
R IO
R IO
VS
55%
&
&
R
Latch
S
R
Q
S
Latch
Q
10/13
&
&
V O UV 1
V O U V4
-
+
+
-
Enable
L9346
Figure 8. Logic Diagram
V
V
EN
IN
VO u
IO o
IO u
c urrent
nor ma l
ope ration
ON
op en lo ad v o lt ag e
latched o ve r.
load di agno stic
o p en l oa d
op e n lo ad cu rren t
nor ma l
opera tion
ON
la tc h re se t
D
op e n lo ad c u rren t
V
nor ma l
operation
O FF
o p e n lo a d
v o lta g e
Figure 9. Application Circuit Diagram
+5V
IN 1
VCC
Z VALVE
I/O
C ha nne l 1
OUT1
I/O
D1
KL 15
I/O
VS
EN
O ut pu t
C o ntr ol
Z VALVE
V Batt
R IO
Ov er tem p
+5V
KL 30
OUT4
52 V
I/O
+45V
IN 4
R
Q
S
D e la y
T im e r
O v erlo a d
I/O
D4
µP
D iagn o s tic
C o ntr ol
O p enloa d
Controller
C ha nne l 4
+5V
IN 2
Z VALVE
I/O
C ha nne l 2
OUT2
I/O
D2
+5V
IN 3
Z VALVE
I/O
C ha nne l 3
OUT3
I/O
D3
GND
GND
11/13
L9346
DIM.
A
a1
a2
a3
b
c
D (1)
D1
E
e
e3
E1 (1)
E2
E3
G
H
h
L
N
S
T
MIN.
mm
TYP.
0.1
0
0.4
0.23
15.8
9.4
13.9
MAX.
3.6
0.3
3.3
0.1
0.53
0.32
16
9.8
14.5
MIN.
0.004
0.000
0.016
0.009
0.622
0.370
0.547
1.27
11.43
10.9
inch
TYP.
0.050
0.450
11.1 0.429
2.9
6.2
0.228
0.1
0.000
15.9 0.610
1.1
1.1
0.031
10° (max.)
8° (max.)
5.8
0
15.5
0.8
OUTLINE AND
MECHANICAL DATA
MAX.
0.142
0.012
0.130
0.004
0.021
0.013
0.630
0.386
0.570
10
0.437
0.114
0.244
0.004
0.626
0.043
0.043
JEDEC MO-166
0.394
PowerSO20
(1) ”D and F” do not include mold flash or protrusions.
- Mold flash or protrusions shall not exceed 0.15 mm (0.006”).
- Critical dimensions: ”E”, ”G” and ”a3”
N
R
N
a2
b
A
e
DETAIL A
c
a1
DETAIL B
E
e3
H
DETAIL A
lead
D
slug
a3
DETAIL B
20
11
0.35
Gage Plane
-C-
S
SEATING PLANE
L
G C
E2
E1
BOTTOM VIEW
(COPLANARITY)
T
E3
1
h x 45
12/13
10
PSO20MEC
D1
L9346
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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