L9347 INTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCH ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Quad low-side switch 2 x 5A designed as conventional switch 2 x 2.5A designed as switched current-regulator Low ON-resistance 2 x 0.2Ω, 2 x 0.35Ω (typ.) Power SO-36 - package with integrated cooling area Integrated free-wheeling and clamping Z-diodes Output slope control Short circuit protection Selective overtemperature shutdown Open load detection Ground and supply loss detection External clock control Recirculation control Regulator drift detection Regulator error control Regulator resolution 5mA Status monitoring Status push-pull stages Electrostatic discharge (ESD) protection PowerSO-36 BARE DIE ORDERING NUMBERS: L9347PD L9347DIE1 DESCRIPTION The L9347 is an integrated quad low-side power switch to drive inductive loads like valves used in ABS systems. Two of the four channels are current regulators with current range from 250mA to 2.25A and an accuracy of 10%. All channels are protected against fail functions. They are monitored by a status output. Figure 1. Pin Connection GND PGND3 PGND3 Q3 Q3 D3 D3 Q1 Q1 Q2 Q2 D4 D4 Q4 Q4 PGND4 PGND4 N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 CLK ST3 IN1 IN3 ST1 PGND1 PGND1 VS PGND2 PGND2 TEST EN ST2 IN4 IN2 ST4 VDD VCC 99AT0060 June 2002 1/21 L9347 Figure 2. Block Diagram VS VCC VDD Internal Supply EN Overtemperature Channel 4 Overtemperature Channel 1 CLK Open Load Overload IN1 Q1 LOGIC ST1 IPD GND-det. Open Load D4 IN4 LOGIC & DA Overload Q4 ST4 IPD GND-det. Overtemperature Channel 3 Overtemperature Channel 2 Open Load Overload IN2 Q2 LOGIC ST2 IPD GND-det. Open Load D3 IN3 LOGIC & DA Overload Q3 ST3 IPD GND-det. drift-det. TEST 99AT0059 2/21 GND L9347 PIN DESCRIPTION N° Pin Function 1 GND 2, 3 PGND 3 Power Ground Channel 3 4, 5 Q3 Power Output Channel 3 6, 7 D3 Free-Wheeling Diode Channel 3 8, 9 Q1 Power Output Channel 1 10, 11 Q2 Power Output Channel 2 12, 13 D4 Free-Wheeling Diode Channel 4 14, 15 Q4 Power Output Channel 4 16, 17 PGND 4 Power Ground Channel 4 18 NC 19 VCC 5V Supply 20 VDD 5V Supply 21 ST 4 Status Output Channel 4 22 IN 2 Control Input Channel 2 23 IN 4 Control Input Channel 4 24 ST 2 Status Output Channel 2 25 EN 26 TEST 27, 28 PGND 2 29 VS 30, 31 PGND 1 Power Ground Channel 1 32 ST 1 Status Output Channel 1 33 IN 3 Control Input Channel 3 34 IN 1 Control Input Channel 1 35 ST 3 Status Output Channel 3 36 CLK Clock Input Logic Ground Not Connected Enable Input for all four Channels Enable Input for Drift detection Power Ground Channel 2 Supply Voltage 3/21 L9347 ABSOLUTE MAXIMUM RATINGS The absolute maximum ratings are the limiting values for this device. Damage may occur if this device is subjected to conditions which are beyond these values. Symbol EQ Parameter Test Conditions Min Typ Switch off energy for inductive loads Max Unit 50 mJ Voltages VS Supply voltage -0.3 40 V VCC, VDD Supply voltage -0.3 6 V VQ Output voltage static VQ Output voltage during clamping t < 1ms Input voltage IN1 to IN4, EN II < |10|mA VIN, VEN 40 V 60 V -1.5 6 V VCLK Input Voltage CLK -1.5 6 V VST Output voltage status -0.3 6 V VD Recirculation circuits D3, D4 40 V max. reverse breakdown voltage of free wheeling diodes D3, D4 55 V VDRmax Currents IQ1/2 Output current for Q1 and Q2 >5 internal limited A IQ3/4 Output current for Q3 and Q4 >3 internal limited A IQ1/2, IPGND1/2 Output current at reversal supply for Q1 and Q2 -4 A IQ3/4, IPGND3/4 Output current at reversal supply for Q3 and Q4 -2 A Output current status pin -5 IST 5 mA ESD Protection ESD Electrostatical Discharging MIL883C ±2 kV ESD Output Pins (Qx, Dx) vs. Common GND (PGND1-4 + GND) ±4 kV THERMAL DATA Symbol Parameter Junction temperature Tj Tjc Junction temperature during clamping (life time) Σt = 30min Σt = 15min Tstg Storage temperature Tstg Tth Overtemperature shutdown threshold (1) Thy Overtemperature shutdown hysteresis (1) Thermal resistance junction to case RthJC RthJC (1) This parameter will not be tested but assured by design. 4/21 Test Conditions Tj Min Typ Max Unit 150 °C 175 190 °C -55 150 °C 175 200 °C -40 10 °C 2 K/W L9347 OPERATING RANGE Symbol Max. Unit VS Supply voltage 4.8 18 V VCC, VDD Supply voltage 4.5 5.5 V Supply voltage transient time -1 1 V/µs -0.3 40 V 60 V 6 V dVS/dt Parameter Test Conditions Min. Typ. VQ Output voltage static VQ Output voltage induced by inductive switching VST Output voltage status IST Output current status -1 1 mA Tj Junction temperature -40 150 °C Tjc Junction temperature during clamping 175 190 °C Max. Unit Voltage will be limited by internal Z-diode clamping -0.3 Σ = 30min Σ = 15min . ELECTRICAL CHARACTERISTCS: (Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Power Supply ISON Supply current VS ≤ 18V (outputs ON) 5 mA ISOFF Quiescent current VS ≤ 18V (outputs OFF) 5 mA Icc Supply current VCC (analog supply) VCC =5V 5 mA Idd Supply current VDD (digital supply) VDD =5V fCLK=0Hz 5 uA Idd Supply current VDD (digital supply) VDD =5V fCLK=250kHz 5 mA 0.36 x VQ 1 V 3.5 V 100 kHz 45 % General Diagnostic Functions Open load voltage VS ≥ 6.5V (outputs OFF) 0.3 VthGND Signal-GND-loss threshold VCC= 5V 0.1 VthPGL Power-GND-loss threshold VCC= 5V 1.5 fCLK,min Clock frequency error VQU DCCLKe_l Clock duty cycle error detection low 0.33 2.5 10 fCLK= 250 kHz 33,3 ow DCCLKe_ Clock duty cycle error detection high fCLK= 250 kHz 55 VCC = VDD = 5V 2 66,6 % high VSloss Supply detection 4.5 V 140 mA 9 A Additional Diagnostic Functions channel 1 and channel 2 (non regulated channels) IQU1,2 Open-load current channel 1, 2 VS ≥ 6.5V 50 IQO1,2 Over-load current channel 1, 2 VS ≥ 6.5V 5 7.5 5/21 L9347 ELECTRICAL CHARACTERISTCS: (continued) (Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 90 % Additional Diagnostic Functions channel 3 and channel 4 (regulated channels) DCOUT Output duty cycle range filtered with 10ms 10 IQO3,4 Overload current channel 3,4 VS ≥ 6.5V 2.5 5 8 A Recirculation error shutdown threshold (open D3/D4) Iout > 50mA 45 50 60 V +14.3 % Vrerr PWMdOU Output PWM ratio during drift T comparison VIN3 = VIN4 = PWMIN VTEST = H -14.3 Digital Inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90% VIL Input low voltage -0.3 1 V VIH Input high voltage 2 6 V VIHy Input voltage hysteresis (1) 20 500 mV 40 µA II Input pull down current VIN = 5V, VS ≥ 6.5V 8 20 Digital Outputs (ST1 to ST4) VSTL Status output voltage in low state (2) IST ≤ 40µA 0 0.4 V VSTH Status output voltage in high state 2) IST ≥ -40µA 2.5 3.45 V IST ≥ -120µA 2 3.45 V RDIAGL ROUT + RDSON in low state 0.3 0.64 1.5 kΩ RDIAGH ROUT + RDSON in high state 1.5 3.2 7.0 kΩ 0.5 0.5 Ω Ω Ω Power Outputs (Q1 to Q4) RDSON1,2 Static drain-source ON-resistance Q1 and Q2 (non-reg. channels) IQ = 1A; VS ≥ 9.5V 0.2 Tj = 25°C Tj = 125°C(3) Tj = 150°C(4) RDSON3,4 Static drain-source ON-resistance Q3 and Q4 (reg. channels) IQ = 1A; VS ≥ 9.5V 0.75 0.75 Ω Ω Ω 0.35 Tj = 25°C Tj = 125°C 3) Tj = 150°C 4) VF_250mA Forward voltage of free wheeling path D3, D4 @250mA ID3/4 = -250mA 0.5 1.5 V VF_2.25A Forward voltage of free wheeling path D3, D4 @2.25A ID3/4 = -2.25A 2.0 4.5 V Rsens 6/21 Sense resistor = (VF_2.25A-VF_250mA)/ 2A 1 Ω L9347 ELECTRICAL CHARACTERISTCS: (continued) (Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit VZ Z-diode clamping voltage IQ ≥ 100mA 45 60 V IPD Output pull down current VEN = H, VIN = L 10 150 µA IQlk Output leakage current VEN = L; VQ = 20V 5 µA tON Output ON delay time IQ = 1A 0 5 20 µs tOFF Output OFF delay time channel IQ = 1A 0 10 30 µs Timing tOFFREG Output OFF delay time regulator µs 528 (5) tr Output rise time IQ = 1A 0.5 1.5 8 µs tf Output fall time IQ = 1A 0.5 1.5 8 µs tsf Short error detection filter time fCLK = 250kHz DC = 50%(5) 4 8 µs tlf Long error detection filter time fCLK = 250kHz DC = 50%(5) 16 32 µs Short circuit switch-OFF delay time (5) 4 30 µs tD Status delay time (5) 896 1024 us tRE Regulation error status delay time (5) tSCP tDreg 10 ms 528 µs (reg. channels only) Output off status delay time (5) (reg. channels only Reg. Current Accuracy (reg. channels only) IQ3/Q4 Minimum current DC = 10% 200 250 300 mA IQ3/Q4 Maximum current DC = 90% 2 2.25 2.5 A Max. regulation deviation @ DC 10% - 90% 250mA < IQ3/Q4 < 400mA 400mA ≤ IQ3/Q4 ≤ 800mA 800mA < IQ3/Q4 < 2.25A ±10 ±6 ±10 % % % IREG ∆IQ3/Q4 Min. quant. step 5 mA 250 kHz 2 kHz Frequencies (1) (2) (3) (4) (5) CLK frequency crystal-controlled Input PWM frequency (reg. channels only) This parameter will not be tested but assured by design Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW" Measured chip, bond wires not included Measured on Power SO-36 devices Digital filtered with external clock, only functional test 7/21 L9347 1.0 Functional Description 1.1 Overview The L9347 is designed to drive inductive loads (relays, electromagnetic valves) in low side configuration. Integrated active Zener-clamp (for channel1 and 2) or free wheeling diodes (for channel 3 and 4) allow the recirculation of the inductive loads. All four channels are monitored with a status output. All wiring to the loads and supply pins of the device are controlled. The device is self-protected against short circuit at the outputs and overtemperature. For each channel one independent push-pull status output is used for a parallel diagnostic function. Channel 3 and 4 work as current regulator. A PWM signal on the input defines the target output current. The output current is controlled through the output PWM of the power stage. The regulator limits of 10% or 90% are detected and monitored with the status signal. The current is measured during recirculation phase of the load. A test mode compares the differences between the two regulators. This “drift” test compares the output PWM of the regulators. By this feature a drift of the load during lifetime can be detected. 1.2 Input Circuits The INput, CLK, TEST and ENable inputs, are active high, consist of Schmidt triggers with hysteresis. All inputs are connected to pull-down current sources. 1.3 Output Stages (not regulated) Channel 1 and 2 The two power outputs (5A) consist of DMOS-power transistors with open drain output. The output stages are protected against short circuit. Via integrated Zener-clamp-diodes the overvoltage of the inductive loads due to recirculation are clamped to typ. 52V for fast shut off of the valves. Parallel to the DMOS transistors there are internal pull-down current sources. They are provided to assure an open load condition in the OFF-state. With EN=low this current source is switched off, but the open load comparator is still active. 1.4 Current-Regulator-Stages Channel 3 and 4 The current-regulator channels are designed to drive inductive loads. The target value of the current is given by the duty cycle (DC) of the 2kHz PWM input signal. The following figure shows the relation between the input PWM and the output current and the specified accuracy. Figure 3. Input PWM to output current range Cu rr e nt p re c isi on OUTPUT Current [mA] 2250 +-10% 800 +- 6% 400 ±10% 250 10 8/21 INPUT PWM[%] 90 L9347 The ON period of the input signal is measured with a 1MHz clock, synchronized with the external 250kHz clock. For requested precision of the output current the ratio between the frequencies of the input signal and the external 250kHz clock has to be fixed according to the graph shown in Fig. current accuracy Figure 4. Current accuracy according to the input and clock frequency ratio 5.6% 112.5 Regulator 125 132 fCLK / fIN 0% switched off -10% The theoretical error is zero for fCLK / fIN = 125. If the period of the input signal is longer than 132 times the period of the clock the regulator is switched off. For a clock frequency lower than 100kHz the clock control will also disable the regulator. For high precision applications the clock frequency and the input frequency have to be correlated. The output current is measured during the recirculation of the load. The current sense resistor is in series to the free wheeling diode. If this recirculation path is interrupted the regulator stops immediately and the status output remains low for the rest of the input cycle. The output period is 64 times the clock period. With a clock frequency of 250kHz the output PWM frequency is 3.9kHz. The output PWM is synchronized with the first negative edge of the input signal. After that the output and the input are asynchronous. The first period is used to measure the current. This means the first turn-on of the power is 256µs after the first negative edge of the input signal. As regulator a digital PI-regulator with the Transfer function for: KI: 0.126 --------------z–1 and KP: 0.96 for a sampling time of 256us is realised. To speed up the current settling time the regulator output is locked to 90% output PWM untill the target current value is reached. This happens alsowhen the target current value changes and the output PWM reaches 90% during the regulation. The status output gets low if the target current value is not reached within the regulation error delay time of tRE=10ms. The output PWM is than out of the regulation range from 10% to 90%. 1.5 Protective Circuits The outputs are protected against current overload, overtemperature, and power-GND-loss. The external clock is monitored by a clock watchdog. This clock watchdog detects a minimal frequency fCLK,min and wrong clock duty cycles. The allowed clock duty cycle range is 45% to 55%. The current-regulator stages are protected 9/21 L9347 against recirculation errors, when D3 or D4 is not connected. All these error conditions shut off the power stage and invert the status output information. 1.6 Error Detection The status outputs indicate the switching state under normal conditions (status LOW = OFF; status HIGH = ON). If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table below. All external errors, for example open load, are filtered internally. The following table shows the detected errors, the filter times and the detection mode (on/off). Short circuit of the load ON State EN &IN = HIGH X OFF State EN &IN = LOW Filter time Reset done by tsf EN & IN = “LOW” for TD or TDreg tlf timer T D Open load (under voltage detection) Open load (under current detection) Overtemperature X tsf timer T D X tsf EN & IN = “LOW” for TD or TDreg Power-GND-loss X X tlf in on: EN & IN = “LOW” for TD or TDreg in off: timer TD tlf timer T D X Signal-GND-loss X X Supply-VS-loss X X tlf timer T D Clock control X X no in on: EN & IN = “LOW” for TD or TDreg in off: timer TD no in on: EN & IN = “LOW” for TD or TDreg in off: timer TD Output voltage clamp active X (regulated channels) EN&IN=low means that at least one between enable and input is low. For the inputs IN=low means also no input PWM. For the regulator input period longer than TDreg and for the standard channel input period longer thanTD. A detected error is stored in an error register. The reset of this register is made with a timer TD. With this approach all errors are present at the status output at least for the time T D. All protection functions like short circuit of the output, overtemperature, clock failure or power-GND-loss in ON condition are stored into an internal “fail” register. The output is then shut off. The register must be reset with a low signal at the input. A “low signal” means that the input is low for a time longer than TD or TDReg for the reulated channel, otherwise it is interpreted as a PWM input signal and the register is left in set mode. Signal-GND-loss and VS-loss are detected in the active on mode, but they do not set the fail register. This type of error is only delayed with the standard timer tlf function. Open load is detected for all four channels in on- and off-state. Open load in off condition detects the voltage on the output pin. If this voltage is below 0.33 * VS the error register is set and delayed with TD. A sink current stage pull the output down to ground, with EN high. With EN low the output is floating in case of openload and the detection is not assured. In the ON state the load current is monitored by the non-regulated channels. If it drops below the specified threshold value IQU an open load is detected and the error register is set and delayed with T D. A regulated channel detects the open load in the on state with the current regulator error detection. If the output PWM reaches 90% for a time longer than t RE than an error occurs. This could happen when no load is connected, the resistivity of the load is too high or the supply voltage too low. The same error is shown if the regulator is not able to reduce the current in the load in the time tRE, so the output PWM falls below 10%. A clock failure (clock loss) is detected when the frequency becomes lower than fCLK,min. All status outputs are 10/21 L9347 set on error and all power outputs are shut off. The status signals remain in their state until the clock signal is present again. A clock failure during power on of VCC is detected only on the regulated channels. The status outputs of the channel 1 and 2 are low in this case. 1.7 Drift Detection (regulated channels only) The drift detection is used to compare the two regulated channels during regulation. This “Drift” test compares the output PWM of the regulators. The resistivity of the load influences the output PWM. The approximated formula for the output current below shows the dependency of the load resistor to the output PWM. In this formula the energy reduction during the recirculation is not taken into account. The real output PWM is higher. The testmode is enabled with IN,EN and TEST high. With an identical 2kHz PWM-Signal connected to the IN-inputs the output PWM must be in a range of +-14.3%. If the difference between the two on-times is more than ±14.3% of the expected value an error is detected and monitored by the status outputs, in the same way as described above, but a drift error will not be registered and also not delayed with T D as other errors VBAT IOUT = ---------------------------- ⋅ PWM RL + RON Drift Definition: Drift = PWM(1+E) - PWM (1-E) = 2PWM E Drift * 4 < PWM (1+E) with E >14.3% a drift is detected E.. not correlated Error of the channels %PWM ... Corresponding ideal output PWM to a given input PWM A 7bit output-PWM-register is used for the comparison. The register with the lower value is subtracted from the higher one. This result is multiplied by four and compared with the higher value. 1.8 Other Test modes The test pin is also used to test the regulated channels in the production. With a special sequence on this pin the power stages of the regulated channels can be controlled direct from the input. No status feedback of the regulated channels is given. The status output is clocked by the regulator logic. The output sequence is a indication of a proper logic functionality. The following table shows the functionality of this special test mode EN IN TEST OUT STATUS Note 1 X X X X disable test mode 1 1 1 on 1 Drift mode 0 X off test pattern test condition one 0 X off test pattern test condition two 0 X off test pattern test condition three 0 0 off test pattern test condition four 0 1 on test pattern test condition four For more details about the test condition four see timing diagram. 11/21 L9347 Diagnostic Table The status follows the input signal in normal operating conditions. If any error is detected the status is inverted. Operating Condition Test Input TEST Enable Input ENA Control Input non-reg./reg. IN Power Output/ Current reg. Q Status Output ST Normal function L L L L L L H H L H/PWM L H/PWM OFF OFF OFF ON L L L H Open load or short to ground L L L L L L H H L H/PWM L H/PWM OFF OFF OFF ON X X H L Overload or short to supply Latched overload Reset latch Reset latch L L L L H H H –> L H H/PWM H/PWM X H/PWM –> L OFF OFF OFF OFF L L L L Overtemperature Latched overtemperature Reset latch Reset latch L L L L H H H –> L H H/PWM H/PWM X H/PWM –> L OFF OFF OFF OFF L L L L Recirculation error (reg.chn.) Latched error Reset latch Reset latch L L L L H H H –> L H PWM PWM X PWM –> L OFF OFF OFF OFF L L L L Clock failure (clock loss) (1) L L L L L L H H L H/PWM L H/PWM OFF OFF OFF OFF H H H L Drift (2) H H H H L L H H L H/PWM H/PWM H/PWM OFF OFF ON ON X X L H Failure No failure (1) during power on sequence only detected on channel 3 and 4 (see description). (2) This input combination is also used for an internal chip-test and must not be used. 12/21 L9347 2.0 Timing Diagrams 2.1 Non Regulated Channels Figure 5. Output Slope, Resistive Load VI VIH VIL t VQ tON tOFF tf tr VS 85% V S 15% V S t 99AT0061 Figure 6. Overload Switch-OFF Delay IQ IQO IQU t tD tSCP VST tsf t 00RS0001 13/21 L9347 Figure 7. Normal Condition, Resistive Load, Pulsed Input Signal VIN VQ IQ IQU tD tD VST 99AT0063 Figure 8. Current Overload tD Reset Fail register VIN VQ Set Fail register IQO IQ tD VST 99AT0064 14/21 L9347 Figure 9. Diagnostic Status Output at Different OPEN Load Current Conditions Under current condition followed by normal operation tD VIN VQ IQ IQU tD VST 99AT0065 Open load condition in the case of pulsed input signal followed by normal operation tD VIN VQ IQU IQ tD VST 99AT0066 15/21 L9347 Figure 10. Pulsed Open Load Conditions (regulated and non-regulated channels) VIN VQ 0.33 x VS IQ tD tlf tlf VST 99AT0067 2.2 Regulated Channels (timing diagrams of diagnostic with 2kHz PWM input signal) Figure 11. Normal Condition, Inductive Load tDREG 500µs VIN VQ Target Current IQ VST 99AT0068 16/21 256µs 256µs L9347 Figure 12. Current Overload tDREG 500µs Reset Fail register VIN VQ Set fail registor IQO IQ tsf VST 99AT0069 Figure 13. Recirculation Error 500µs tDREG Reset Fail register VIN VQ IQ Set Fail register target current VST 99AT0070 17/21 L9347 Figure 14. Current Regulation Error (e.g. as a result of voltage reduction) 500µs VIN VQ PWM ratio = 90% target current IQ tRE VST 99AT0071 Figure 15. Overtemperature Overtemperature Condition 500µs tDREG VIN VQ IQ VST 99AT0072 18/21 Set Fail register target current Reset Fail register L9347 Figure 16. Test mode 4 VEN low VTEST VIN3/4 VQ3/4 99AT0073 19/21 L9347 DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S MIN. mm TYP. 0.10 0 0.22 0.23 15.80 9.40 13.90 MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50 inch TYP. MIN. 0.004 0 0.008 0.009 0.622 0.370 0.547 0.65 11.05 10.90 0.0256 0.435 11.10 0.429 2.90 6.20 0.228 3.20 0.114 0.10 0 15.90 0.610 1.10 1.10 0.031 10°(max.) 8 °(max.) 5.80 2.90 0 15.50 0.80 OUTLINE AND MECHANICAL DATA MAX. 0.141 0.012 0.130 0.004 0.015 0.012 0.630 0.385 0.570 0.437 0.114 0.244 0.126 0.004 0.626 0.043 0.043 PowerSO36 (1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G". N N a2 e A DETAIL A A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 36 BOTTOM VIEW 19 E3 B E1 E2 D1 DETAIL B 0.35 Gage Plane 1 1 -C- 8 S h x 45˚ 20/21 b ⊕ 0.12 L SEATING PLANE G M AB PSO36MEC C (COPLANARITY) L9347 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 21/21