L9823 Octal Low-Side Driver for bulb, resistive and inductive loads with serial input control, output protection and diagnostic ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ OUTPUTS CURRENT CAPABILITY UP TO 0.5A CASCADABLE SPI CONTROL FOR OUTPUTS RESET FUNCTION WITH RESET SIGNAL OR UNDERVOLTAGE AT VDD PROGRAMMABLE INTRINSIC OUTPUT VOLTAGE CLAMPING AT TYP. 50V FOR INDUCTIVE SWITCHING OVERCURRENT SHUTDOWN WITH LATCHOFF FOR EVERY WRITE CYCLE (SFPD = LOW) INDEPENDENT THERMAL SHUTDOWN OF OUTPUTS (SOA PROTECTION) OUTPUT STATUS DATA AVAILABLE ON THE SPI USING 8-BIT I/O PROTOCOL UP TO 3.0MHZ LOW STANDBY CURRENT WITH RESET = LOW (TYP 35µA @ VDD) OPEN LOAD DETECTION (OUTPUTS OFF) SINGLE VDD LOGIC SUPPLY HIGH EMS IMMUNITY AND LOW EME (CONTROLLED OUTPUT SLOPES) FULL FUNCTIONALITY OF THE REMAINING DEVICE AT NEGATIVE VOLTAGE DROP ON SO24 (20+2+2) ORDERING NUMBER: L9823 ■ OUTPUTS (-1,5V OR -3,0A) OUTPUT MODE PROGRAMMABLE FOR SUSTAINED CURRENT LIMIT OR SHUTDOWN DESCRIPTION L9823 is a Octal Low-Side Driver Circuit, dedicated for automotive applications. Output voltage clamping is provided for flyback current recirculation, when inductive loads are driven. Chip Select and cascadable Serial 8-bit Interface for outputs control and diagnostic data transfer. BLOCK DIAGRAM 16 VDD SFPD 15 OUT0 - OL0 24 VDG + IOL SCLK 3 SI 4 Output Latch 10 Shift Register CSB SPI Interface = SO Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Gate Control + ISCB 0 OT0 Diag0 Diag0 Q1 Diag1 Diag1 Diag2 Q2 Diag3 Diag2 Diag4 Diag5 Q3 Diag6 Diag3 Diag7 Q4 Diag4 - Over Temperature Detect + = CH0 CH1 CH2 CH3 CH4 9 Q5 Diag5 CH5 Reset Q6 Diag6 CH7 Q7 Diag7 CH7 22 Reset Undervoltage RESET Reset OUT1 23 OUT2 14 OUT3 13 OUT4 12 OUT5 11 OUT6 2 OUT7 1 GND 5 -8 17 - 20 April 2003 1/12 L9823 PIN FUNCTION N° Pin 1 Out 7 Output 7 2 Out 6 Output 6 3 SCLK SCLK. The system clock pin (SCLK) clocks the internal shift registers of the L9823. The serial input pin (SI) accepts data into the input shift register on the falling edge of the SCLK signal while the serial output pin (SO) shifts data information out of the shift register on the rising edge of the SCLK signal. False clocking of the shift register must be avoided to guarantee validity of data. It is essential that the SCLK pin be in a logic low state whenever chip select bar pin (CSB) makes any transition. For this reason, it is recommended though not necessary, that the SCLK pin be kept in a low logic state as long as the device is not accessed (CSB in logic high state). When CSB is in a logic high state, any signal at the SCLK and SI pin is ignored and SO is tri-stated (high-impedance). 4 SI SI. This pin is for the input of serial instruction data. SI information is read in on the falling edge of SCLK. A logic high state present on this pin when the SCLK signal rises will program a specific output OFF, and in turn, turns OFF the specific output on the rising edge of the CSB signal. Conversely, a logic low state present on the SI pin will program the output ON, and in turn, turns ON the specific output on the rising edge of the CSB signal. To program the eight outputs of the L9823 ON or OFF, an eight bit serial stream of data is required to be entered into the SI pin starting with Output 7, followed by Output 6, Output 5, etc., to Output 0. For each rise of the SCLK signal, with CSB held in a logic low state, a databit instruction (ON or OFF) is loaded into the shift register per the databit SI state. The shift register is full after eight bits of information have been entered. To preserve data integrity, care should be taken to not transition SI as SCLK transitions from a low-to-high logic state. 5 GND GND 6 GND GND 7 GND GND 8 GND GND 9 SO SO. The serial output (SO) pin is the tri-stateable output from the shift register. The SO pin remains in a high impedance state until the CSB pin goes to a logic low state. The SO data reports the drain status, either high or low. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. When an output is OFF and not faulted, the corresponding SO databit is a high state. When SO an output is ON, and there is no fault, the corresponding databit on the SO pin will be a low logic state. The SI / SO shifting of data follows a first-in-first-out protocol with both input and output words transferring the Most Significant Bit (MSB) first. The SO pin is not affected by the status of the Reset pin. 10 CSB CSB. The system MCU selects the L9823 to be communicated with through the use of the CSB pin. Whenever the pin is in a logic low state, data can be transferred from the MCU to the L9823 and vise versa. Clocked-in data from the MCU is transferred from the L9823 shift register and latched into the power outputs on the rising edge of the CSB signal. On the falling edge of the CSB signal, drain status information is transferred from the power outputs and loaded into the device's shift register. The CSB pin also controls the output driver of the serial output pin. Whenever the CSB pin goes to a logic low state, the SO pin output driver is enabled allowing information to be transferred from the L9823 to the MCU. To avoid any spurious data, it is essential that the high-to-low transition of the CSB signal occur only when SCLK is in a logic low state. 11 Out 5 Output 5 12 Out 4 Output 4 13 Out 3 Output 3 2/12 Description L9823 PIN FUNCTION (continued) N° Pin Description 14 Out 2 Output 2 15 SFPD SFPD. The Short Fault Protect Disable (SFPD) pin is used to disable the overcurrent latch-OFF. This feature allows control of incandescent loads where in-rush currents exceed the device's analog current limits. Essentially the SFPD pin determines whether the L9823 output(s) will instantly shutdown upon sensing an output short or remain ON in a current limiting mode of operation until the output short is removed or thermal shutdown is reached. If the SFPD pin is tied to VDD the L9823 output(s) will remain ON in a current limited mode of operation upon encountering a load short to supply. If the SFPD pin is grounded, a short circuit will immediately shutdown only the output affected. Other outputs not having a fault condition will operate normally. 16 VDD VDD 17 GND GND 18 GND GND 19 GND GND 20 GND GND 21 NC 22 Reset Reset. The Reset pin is active low and used to clear the SPI shift register and in doing so sets all output switches OFF. With the device in a system with an MCU; upon initial system power up, the MCU holds the Reset pin of the device in a logic low state ensuring all outputs to be OFF until the VDD pin voltages are adequate for predictable operation. After the L9823 is Reset, the MCU is ready to assert system control with all output switches initially OFF. The Reset pin is active low and has an internal pull-down incorporated to ensure operational predictability should the external pull-down of the MCU open circuit. The internal pull-up is to afford safe and easy interfacing to the MCU. The Reset pin of the L9823 should be pulled to a logic low state for a duration of at least 160ns to ensure reliable Reset. 23 Out 1 Output 1 24 Out 0 Output 0 Not Connected ABSOLUTE MAXIMUM RATINGS For voltages and currents applied externally to the device. Exceeding limits may cause damage to the device. Symbol VDD Parameter Supply voltage Value Unit -0.3 to 7 V Inputs and data lines (CSB, SCLK, SI, Reset, SFPD, SO) VIN VSDO IIN Voltage (CSB, SCLK, SI, Reset, SFPD) Voltage (SO) Protection diodes current 1) T ≤ 1ms -0.3 to 7 -0.3 to VDD+0.3 V -20 to 20 1) mA -1.5 to 45 V Outputs (Out0 ... Out7) VOUT Cont Continuous output voltage 3/12 L9823 ABSOLUTE MAXIMUM RATINGS (continued) Symbol Parameter Value Unit -3 to IOUT LIM A -10 2) to 2 A VOUT Cont Continuous output current IOUT PEAK Output current EOUTclamp Output clamp energy 3) 50 mJ IOUT LIM Output current (self limit) 2 A Note 1) All inputs are protected against ESD according to MIL 883C; tested with HBM C = 100pF, R = 1500Ω at ±2KV. It corresponds to a dissipated energy E ≤ 0.2mJ (data available upon request). 2) Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3. 3) Max. output clamp energy at Tj = 150°C, using single non-repetitive pulse of 500mA THERMAL DATA Symbol Parameter Value Unit 155 (Min.), 180 (Typ.) °C Thermal shutdown TLIM Thermal shutdown threshold Thermal resistance (junction-to-Lead) RthjL-one Single output (junction lead) 25 (Max.) °C/W RthjL-all All outputs (junction lead) 20 (Max.) °C/W Storage Temperature -55 to 150 °C Tstg ELECTRICAL CHARACTERISTCS (4.5V ≤ VDD ≤ 5.5V; -40°C ≤ TJ ≤ 150°C; unless otherwise specified Symbol Parameter Test Condition Min. Typ. Max. Unit 35 70 µA <1 10 µA 6 mA 10 mA 2.5 3.95 V Supply voltage IDDSTB IDDleak Standby current leakage current Reset = LOW and / or VDDRES>VDD > 0.5V VDD < 0.5V IDDOPM Operating mode IOUT0 ... 7 = 500mA SPI - SCLK = 3MHz CSB = LOW SO no load ∆IDD rev ∆IDD during reverse output current Iout rev = -2.5A VDD RES Undervoltage Reset Reset of all registers and disable of all outputs Inputs (CSB, SCLK, SI, Reset, SFPD) VINL Low level -0.3 0.2·VDD V VINH High level 0.7·VDD VDD+0.3 V Vhyst Hysteresis voltage 0.5·VDD V 4/12 0.5 1.2 L9823 ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter IIN Input current RIN Pullup resistance (CSB, SI) Pulldown resistance (SFPD, Reset, SCLK) CIN Input capacitance Test Condition VIN = VDD Min. Typ. Max. Unit -10 10 µA 50 250 kΩ 10 pF Serial data outputs VSOH High output level ISO = -4mA VSOL Low output level ISO = 3,2mA ISOL Tristate leakage current CSB = high; 0V ≤ VSO ≤ VDD CSO Output capacitance fSO = 300kHz, 0V ≤ VSO ≤ VDD VDD -0.4 V -10 0.4 V 10 µA 20 pF 10 µA 60 V 1.5 1.25 Ω Ω 300 pF Outputs OUT 0 ... 7 IOUTL0 - 7 Leakage current OUTx = OFF; VOUTx = 16V; VDD ≤ VDD RES and / or Reset = Low Tj ≤ 85°C -10 Output clamp voltage 2mA ≤ IOUT clamp ≤ IOUT LIM IOUT test = 20mA with correlation 45 RDSon On resistance OUT 0 ... 7 IOUT = 500mA;Tj = +150°C Tj = +25°C COUT Output capacitance VOUT = 16V; f = 1MHz VOUT clamp <1µA 1 0.8 Outputs short circuit protection ISCB Overcurrent shutoff threshold IOUT LIM Short circuit current limitation tdly SCB Short circuit shutdown delay SFPD = Low, VOUT ≥ VDG SFPD = Low, VOUT ≥ VDG CSB = 50% to IOUT ≤ 1/2 IOUT LIM 0.5 1.6 2.5 A 0.5 1.6 2.5 A 70 150 250 µs 0.5·VDD 0.55·V 0.6·VDD V Diagnostics VDG Diagnostic threshold voltage DD IOUT OL Open load detection sink current Vout = VDG Output programmed OFF 30 60 100 µA tdly SFPD Diagnostic detection filter time SFPD = Low, VOUT ≥ VDG CSB = 50% to valid data at SO 70 150 250 µs 20 µs Outputs timing tdon Turn ON delay CSB = 50% to RL = 50Ω VOUT = 0,9Vbat, Vbat = 16V 5/12 L9823 ELECTRICAL CHARACTERISTCS (continued) Symbol tdoff Parameter Test Condition Min. Typ. Max. Unit 20 µs Turn OFF delay CSB = 50% to RL = 50Ω VOUT = 0,1·Vbat, Vbat = 16V dVon/dt Turn ON voltage slew-rate 90% to 30% of Vbat; RL = 50Ω; Vbat = 16V 0.7 2.1 3.5 V/µs dVoff/dt Turn OFF voltage slew-rate 30% to 90% of Vbat; RL = 50Ω; Vbat = 16V 0.7 2.1 3.5 V/µs dVoff clamp/dt Turn OFF voltage clamp slew-rate 30% to 80% of VOUT clamp RL = 500Ω 0.7 2.1 5.5 V/µs Serial diagnostic link (Load capacitor at SO = 200pF) fsclk Clock frequency tclh tcll 50% duty cycle 3 MHz Minimum time SCLK = HIGH 160 ns Minimum time SCLK = LOW 160 ns 4.9V ≤ VDD ≤ 5.1V tpcld Propagation delay SCLK to data at SO valid tcsdv CSB = LOW to data at SO active tsclch SCLK low before CSB low Setup time SCLK to CSB change H/L 100 ns thclcl SCLK change L/H after CSB = Low Setup time CSB to SCLK change L/H 100 ns tscld SI input setup time SCLK change H/L after SI data valid 20 ns thcld SI input hold time SI data hold after SCLK change H/L tsclcl SCLK low before CSB high 150 ns thclch SCLK high after CSB high 15, ns tpchdz CSB L/H to output data float 100 ns tReset Minimum Reset time Reset = Low 160 ns Outputs Control Tables : Outputs: 6/12 SI-bit 0 1 Output on off 100 ns 100 ns 20 ns L9823 Output Control register structure : MSB Q7 LSB Q6 Q5 Q4 Q3 Q2 Q1 Q0 Control-bit output 7 Control-bit output 6 Control-bit output 5 Control-bit output 4 Control-bit output 3 Control-bit output 2 Control-bit output 1 Control-bit output 0 Power outputs characteristics for flyback current, outputs short circuit protection and diagnostics For output currents flowing into the circuit the output voltages are limited. The typical value of this voltage is 50V. This function allows that the flyback current of a inductive load recirculates into the circuit; the flyback energy is absorbed in the chip. Output short circuit protection SFPD = Low (dedicated for loads without inrush current): when the output current exceeds the short circuit threshold, the corresponding output overload latch is set after a delay time tdly SCB and the output is switched off. The delay timer is started after each rise of CSB and valid datas are transfered to the output control register. If the short takes place after the delay time has elapsed the shutdown is immediate (within 15µs). Output short circuit protection SFPD = High (dedicated for loads with inrush current, as lamps): when the load current would exceed the short circuit limit value, the corresponding output goes in a current regulation mode. The output current is determined by the output characteristics and the output voltage depends on the load resistance. In this mode high power is dissipated in the output transistor and its temperature increases rapidly. When the power transistor temperature exceeds the thermal shutdown threshold, the overload latch is set and the corresponding output switched off. For the load diagnostic in output off condition each output features a diagnostic current sink, of typ 60µA. FUNCTIONAL DESCRIPTION General The L9823 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the device using the Serial Peripheral Interface = SPI protocol. The power outputs features voltage clamping function for flyback current recirculation and are protected against short circuit to Vbat. The diagnostics recognizes two outputs fault conditions: 1) overcurrent and thermal overload in switch-ON condition and 2) open load or short to GND in switch-OFF condition for all outputs. The outputs status can be read out via the serial interface. The chip internal Reset is a OR function of the external Reset signal and internally generated undervoltage Reset signal. 7/12 L9823 Output Stages Control Each output is controlled with its latch and with a common Reset line, which enables all outputs. The control data are transmitted via the SI input, the timing of the serial interface is shown in Fig. 1. The device is selected with low CSB signal and the input data are transferred into the 8 bit shift register at every falling SCLK edge. The rising edge of the CSB latches the new data from the shift register to the drivers. Figure 1. Timing of the Serial Interface CSB tsclch thclcl tclh tcll tsclcl thclch SCLK tcsdv SO tpcld not defined tpchdz D7 D0 thcld tscld SI D7 D6 D0 The SPI register data are transferred to the output latch at rising CSB edge. The digital filter between CSB and the output latch ensures that the data are transferred only after 8 SCLK cycles or multiple of 8 SCLK cycles since the last CSB falling edge. The CSB changes only at low SCLK. Diagnostics The output voltage at all outputs is compared with the diagnostic threshold, typ 0,55 • VDD = VDG. Diagnostic Table for outputs: Output Output-voltage Status-bit Output-mode off > DG-threshold high correct operation off < DG-threshold low fault condition 2) on < DG-threshold low correct operation on > DG-threshold high fault condition 1) Fault condition 1) "output short circuit to Vbat" : For SFPD = Low the output was switched on and the voltage at the output exceeded the diagnostics threshold due to overcurrent, the output overload latch was set and the output has been switched off. The diagnostic bit is high. : For SFPD = High the output was switched on and the voltage at the output exceeds the diagnostics threshold. The output operates in current regulation mode or has been switched off due to thermal shutdown. The status bit is high. Fault condition 2) "open load" or "output short circuit to GND" : the output is switched off and the voltage at the output drops below the diagnostics threshold, because the load current is lower than the output diagnostic current source, the load is interrupted. The diagnostic bit is low. At the falling edge of CSB the output status data are transferred to the shift register. When SCB is low, data bits contained in the shift register are transferred to SO output at every rising SCLK edge. 8/12 L9823 Figure 2. Pulse Diagram to Read the Outputs Status Register CSB SCLK SI SO MSB 6 MSB 5 6 4 5 3 4 2 3 1 2 LSB 1 LSB Figure 3. Structure of the Outputs Status Register MSB LSB Diag7Diag6Diag5Diag4Diag3Diag2Diag1Diag0 Diagnostic-bit ou Diagnostic-bit ou Diagnostic-bit ou Diagnostic-bit ou Diagnostic-bit ou Diagnostic-bit ou Diagnostic-bit ou Diagnostic-bit ou 9/12 L9823 APPLICATIONS INFORMATION The typical application diagram for parallel Input SPI control is shown in Figure 4. Figure 4. Typical Application Circuit Diagram for the L9823 Circuit. VDD 16 VOLTAGE REGULATOR VDD SFPD OUT0 - OL0 15 24 VDG + IOL 3 SI 4 Output Latch SCLK Shift Register 10 SPI Interface = CSB SO Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Reset Reset Reset SCLK SI Undervoltage RESET SO µP CSB2 ... 7 22 Q0 Reset Gate Control + ISCB 0 OT0 Diag0 Diag0 Q1 Diag1 Diag1 Diag2 Q2 Diag3 Diag2 Diag4 Diag5 Q3 Diag6 Diag3 Diag7 Q4 Diag4 9 VBAT - Over Temperature Detect + = CH0 CH1 CH2 CH3 CH4 Q5 Diag5 CH5 Q6 Diag6 CH7 Q7 Diag7 CH7 U459 OUT1 23 OUT2 14 OUT3 13 OUT4 12 OUT5 11 OUT6 2 OUT7 1 R, L loads GND 5 -8 17 - 20 U459 For higher current driving capability more outputs of the same kind can be paralleled. In this case the maximum flyback energy should not exceed the limit value for single output. The immunity of the circuit with respect to the transients at the output is verified during the characterization for Test Pulses 1, 2 and 3a, 3b, DIN40839 or ISO7637 part 3. The Test Pulses are coupled to the outputs with 200pF series capacitor. The correct function of the circuit with the Test Pulses coupled to the outputs is verified during the characterization for the typical application with R = 16Ω to 200Ω, L= 0 to 600mH loads. All outputs withstand testpulses without damage. 10/12 L9823 mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 15.20 15.60 0.598 0.614 E 7.40 7.60 0.291 0.299 e 1.27 10.0 10.65 0.394 0.419 h 0.25 0;75 0.010 0.030 L 0.40 1.27 0.016 0.050 ddd Weight: 0.60gr 0.050 H k OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO24 0070769 C 11/12 L9823 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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