LCP1521 ® Application Specific Discretes A.S.D.TM PROGRAMMABLE TRANSIENT VOLTAGE SUPPRESSOR FOR SLIC PROTECTION FEATURES Dual programmable transient suppressor Wide negative firing voltage range: VMGL = -150 V max. Low dynamic switching voltages: VFP and VDGL Low gate triggering current: IGT = 2 mA max Peak pulse current: IPP = 30 A (10/1000 µs) Holding current: IH = 150 mA SO-8 DESCRIPTION This device has been especially designed to protect new high voltage, as well as classical SLICs, against transient overvoltages. Positive overvoltages are clipped with 2 diodes. Negative surges are suppressed by 2 thyristors, their breakdown voltage being referenced to -VBAT through the gate. This component presents a very low gate triggering current (IGT) in order to reduce the current consumption on printed circuit board during the firing phase. A particular attention has been given to the internal wire bonding. The Kelvin method configuration ensures reliable protection, reducing the overvoltage introduced by the parasitic inductances of the wiring L x(dI/dt), especially for very fast transients. September 1999 - Ed: 2A FUNCTIONAL DIAGRAM TIP TIP GATE GND NC GND RING RING 1/9 LCP1521 Peak Surge Voltage (V) Voltage Waveform (µs) Current Waveform (µs) Admissible Ipp (A) Necessary Resistor (Ω) VDE0433 4000 1000 2000 10/700 10/700 10/700 5/310 5/310 5/310 40 25 40 60 10 VDE0878 2000 1.2/50 1/20 50 2 IEC1000-4-5 level 3 level 4 10/700 1.2/50 5/310 8/20 40 100 10 - FCC Part 68 lightning surge type A 1500 800 10/160 10/560 10/160 10/560 50 35 22 15 FCC Part 68 lightning surge type B 1000 9/720 5/320 25 - BELLCORE: NWT-001089-CORE First level 2500 1000 2/10 10/1000 2/10 10/1000 170 30 10 24 BELLCORE: NWT-001089-CORE Second level 5000 2/10 2/10 170 20 COMPLIES WITH THE FOLLOWING STANDARDS: ITU-T K20 Note 1: the mentioned value of the series resistance is the minimum value needed to fulfill the standard requirement. ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C, unless otherwise specified). Symbol Parameter Value Unit Peak pulse current (see note1) 10/1000µs 5/310µs 2/10µs 30 40 170 A ITSM Non repetitive surge peak on-state current (F = 50Hz) tp = 10ms t = 1s 20 5 A IGSM Maximum gate current (half sine wave tp = 10ms) 2 A VMLG VMGL Maximum voltage LINE/GND Maximum voltage GATE/LINE -150 -150 V Tstg Tj Storage temperature range Maximum junction temperature - 55 to + 150 150 °C 260 °C IPP TL -40°C < Tamb < +85°C -40°C < Tamb < +85°C Maximum lead temperature for soldering during 10s Note 1: Pulse waveform 10 / 1000 µs 5 / 310 µs 2 / 10 µs tr = 10 µs tr = 5 µs tr = 2 µs tp = 1000 µs tp = 310 µs tp = 10 µs % IPP 100 50 0 2/9 tr tp t LCP1521 THERMAL RESISTANCE Symbol Rth (j-a) Parameter Junction to ambient Value Unit 170 °C/W ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol Parameter IGT Gate triggering current IH Holding current IRM Reverse leakage current LINE / GND IRG Reverse leakage current GATE / LINE VRM Reverse voltage LINE / GND VGT VF Gate triggering voltage VFP Peak forward voltage LINE / GND VDGL VR Dynamic switching voltage GATE / LINE VGATE GATE / GND voltage C VF IRM IR Forward drop voltage LINE / GND VDGL VRG VRM IH IPP Reverse voltage GATE / LINE Capacitance LINE / GND 1 - PARAMETERS RELATED TO THE DIODE LINE / GND (Tamb = 25°C) Symbol VF VFP (note 1) Test conditions Square pulse : tp = 500µs 10/700µs 1.2/50µs 2/10µs IF = 5A 1.5kV 1.5kV 2.5kV RP = 10Ω RP = 10Ω RP = 62Ω Max Unit 2 V 5 7 12 V Note 1: see test circuit for VFP; RP is the protection resistor located on the line card. 3/9 LCP1521 2 - PARAMETERS RELATED TO THE PROTECTION THYRISTOR (Tamb = 25°C) Symbol Test conditions Min Max Unit 2 mA IGT VGND / LINE = -48V 0.1 IH VGATE = -48V (see note 2) 150 VGT at IGT IRG Tc=25°C Tc=85°C VDGL VRG = -150V VRG = -150V mA 1.5 V 5 50 µA 7 10 25 V VGATE = -48V (see note 3) 10/700µs 1.2/50µs 2/10µs RP = 10Ω RP = 10Ω RP = 62Ω 1kV 1.5kV 2.5kV IPP = 30A IPP = 30A IPP = 38A Note 2: see functional holding current (IH) test circuit Note 3: see test circuit for VDGL The oscillations with a time duration lower than 50ns are not taken into account 3 - PARAMETERS RELATED TO DIODE AND PROTECTION THYRISTOR (Tamb = 25°C) Symbol IRM C 4/9 Test conditions Tc=25°C Tc=85°C VGATE / LINE = -1V VGATE / LINE = -1V VR = -3V F = 1MHz VR = -48V F = 1MHz VRM = -150V VRM = -150V Max Unit 5 50 µA 100 50 pF LCP1521 FUNCTIONAL HOLDING CURRENT (IH) TEST CIRCUIT : GO-NO GO TEST R - VP VBAT = - 100 V D.U.T. Surge generator This is a GO-NO GO test which allows to confirm the holding current (IH) level in a functional test circuit. TEST PROCEDURE : - Adjust the current level at the IH value by short circuiting the D.U.T. - Fire the D.U.T. with a surge current : IPP = 10A, 10/1000µs. - The D.U.T. will come back to the off-state within a duration of 50ms max. TEST CIRCUIT FOR VFP AND VDGL PARAMETERS R4 (V is defined in unload condition) P TIP L R2 RING R3 VP R1 C1 C2 G ND Pulse (µs) Vp C1 C2 L R1 R2 R3 R4 IPP Rp tr tp (V) (µF) (nF) (µH) (Ω) (Ω) (Ω) (Ω) (A) (Ω) 10 700 1500 20 200 0 50 15 25 25 30 10 1.2 50 1500 1 33 0 76 13 25 25 30 10 2 10 2500 10 0 1.1 1.3 0 3 3 38 62 5/9 LCP1521 TECHNICAL INFORMATION Fig. A1: LCP1521 concept behavior. Rs1 L1 TIP GND -Vbat V Tip ID1 IG T1 Th1 D1 Gate GND C Rs2 RING L2 V Ring Figure A1 shows the classical protection circuit using the LCP1521 crowbar concept. This topology has been developed to protect the new high voltage SLIC’s, it allows to program the negative firing threshold while the positive clamping value is fixed at GND. When a negative surge occurs on one wire (L1 for example) a current Ign flows through the base of the transistor T1 and then injects a current in the gate of the thyristor Th1. Th1 fires and all the surge current flows through the ground. After the surge when the current flowing through Th1 becomes less negative than the holding current IH, then Th1 switches off. When a positive surge occurs on one wire (L1 for example) the diode D1 conducts and the surge current flows through the ground. To the line side 220 nF Fig. A2: Example of PCB layout based on LCP1521 protection. GND To the SLIC side In order to minimize the remaining voltage across the SLIC inputs during the surge, the TIP and RING pins of the LCP1521 are doubled (Pins 1 and 8 for TIP / Pins 4 and 5 for RING). This fact allows the board designer to connect the track like designed in figure A2. With such a PCB design, the extra voltages caused by track stray inductance (LdI / dt) remain located on the line side of the LCP and do not affects its SLIC side. The capacitor C is used to speed up the crowbar structure firing during the fast surge edges. This allows to minimize the dynamical breakover voltage at the SLIC Tip and Ring inputs during fast strikes. Please note that this capacitor is generally present around the SLIC - Vbat pin. So to be efficient it has be as close as possible from the LCP1521 Gate pin and from the reference ground track (or plan) (see Fig. A2). The optimized value for C is 220nF. 6/9 LCP1521 The series resitors Rs1 and Rs2 designed in figure 1 represent the fuse resistors or the PTC which are mandatory to withstand the power contact or the power inductance tests imposed by the different country standards. Taking into account this fact the actual lightning surge current flowing through the LCP is equal to: I surge = V surge / (Rg + Rs) With V surge = peak surge voltage imposed by the standard. Rg = series resistor of the surge generator Rs = series resistor of the line card (e.g. PTC) e.g. For a line card with 30Ω of series resistors which has to be qualified under Bellcore 1000V 10/1000µs surge, the actual current through the LCP1521 is equal to: I surge = 1000 / (10 + 30) = 25A The LCP1521 is particularly optimized for the new telecom applications such as the fiber in the loop, the WLL, the decentralized central office for example. These short line applications need smaller operating voltages than the long line applications and then allow the use of high voltage SLIC’s operating without ring relay. The schematics of figure A3 gives the most frequent topology used for these emergent applications. Fig. A3: Protection of high voltage SLIC. -Vbat Rs (*) TIP Gate Line GND TIP GND 220nF GND RING SLIC Rs (*) RING LCP1521 Line card Rs (*) = PTC or Resitor fuse 7/9 LCP1521 Surge peak current versus overload duration. ITSM (A) 20 18 16 14 12 10 8 6 4 2 0 0.01 Relative variation of holding current versus junction temperature IH [Tj] / IH [Tj=25°C] t(s) 0.1 1 10 100 1000 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -40 Tj(°C) -20 0 20 40 60 80 100 ORDER CODE LCP LINE CARD PROTECTION 15 2 RL PACKAGE 1 : SO-8 IH = 150 mA VERSION 8/9 1 RL : Tape & Reel : Tube LCP1521 PACKAGE MECHANICAL DATA SO-8 (Plastic) DIMENSIONS REF. Millimetres Min. c1 a1 C a3 a2 A e b b1 a1 S E e3 Typ. Max. Min. A L D M Inches 0.1 a2 Typ. Max. 1.75 0.069 0.25 0.004 0.010 1.65 0.065 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 C 0.25 0.50 0.010 0.020 0.50 c1 45° (typ) 5 8 F 1 D 4.8 5.0 0.189 0.197 E 5.8 6.2 0.228 0.244 e e3 4 F L 1.27 3.81 3.8 0.4 M 0.050 0.150 4.0 0.15 1.27 0.016 0.157 0.050 0.6 0.024 S 8° (max) Order code Marking Package Weight Base qty Delivery mode LCP1521 151DHV SO-8 0.08 g 2500 Tube LCP1521RL 151DHV SO-8 0.08 g 2000 Tape & Reel Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9