STMICROELECTRONICS M14128

M14256
M14128
Memory Card IC
256/128 Kbit Serial I²C Bus EEPROM
PRELIMINARY DATA
■
Compatible with I2C Extended Addressing
■
Two Wire I2C Serial Interface
Supports 400 kHz Protocol
■
Single Supply Voltage (2.5 V to 5.5 V)
■
Hardware Write Control
■
BYTE and PAGE WRITE (up to 64 Bytes)
■
BYTE, RANDOM and SEQUENTIAL READ
Modes
■
Self-Timed Programming Cycle
■
Automatic Address Incrementing
■
Enhanced ESD/Latch-Up Behaviour
■
100,000 Erase/Write Cycles (minimum)
■
40 Year Data Retention (minimum)
■
5 ms Programming Time (typical)
DESCRIPTION
Each device is an electrically erasable programmable memory (EEPROM) fabricated with STMicroelectronics’s
High
Endurance,
Double
Polysilicon, CMOS technology. This guarantees
an endurance typically well above 100,000 Erase/
Write cycles, with a data retention of 40 years. The
memory operates with a power supply as low as
2.5 V.
The M14256 and M14128 are available in micromodule form only. For availability of the M14256 or
Table 1. Signal Names
SDA
Serial Data/Address Input/
Output
SCL
Serial Clock
WC
Write Control
VCC
Supply Voltage
GND
Ground
Micromodule (D22)
Figure 1. Logic Diagram
VCC
SCL
WC
SDA
M14xxx
GND
AI02217
October 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/12
M14256, M14128
Figure 2. D22 Contact Connections
VCC
GND
WC
SDA
SCL
AI02204
M14128 in wafer form, please contact your ST
sales office.
Each memory device is compatible with the I2C
extended memory standard. This is a two wire serial interface that uses a bi-directional data bus
and serial clock. The memory device carries a
built-in 7-bit unique Device Type Identifier code
(1010000) in accordance with the I 2C bus definition. Only one memory device can be attached to
each I2C bus.
The memory device behaves as a slave device in
the I2C protocol, with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition,
generated by the bus master. The START condition is followed by the Device Select Code which is
composed of a stream of 7 bits (1010000), plus
one read/write bit (R/W) and is terminated by an
acknowledge bit.
When writing data to the memory, the memory device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and after a NoACK for READ.
Power On Reset: V CC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is
held active until the VCC voltage has reached the
POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when VCC drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid V CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to synchronize all data
in and out of the memory. A pull up resistor can be
connected from the SCL line to VCC. (Figure 3 indicates how the value of the pull-up resistor can be
calculated).
Serial Data (SDA)
The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to VCC. (Figure 3 indicates how the value of the
pull-up resistor can be calculated).
Table 2. Absolute Maximum Ratings 1
Symbol
TA
Parameter
Ambient Operating Temperature
Value
Unit
0 to 70
°C
TSTG
Storage Temperature
-40 to 120
°C
VIO
Input or Output range
-0.6 to 6.5
V
VCC
Supply Voltage
-0.3 to 6.5
V
Electrostatic Discharge Voltage (Human Body model) 2
4000
V
Electrostatic Discharge Voltage (Machine model) 3
400
V
VESD
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
3. EIAJ IC-121 (Condition C) (200 pF, 0 Ω)
2/12
M14256, M14128
Write Control (WC)
The hardware Write Control contact (WC) is useful
for protecting the entire contents of the memory
from inadvertent erase/write. The Write Control
signal is used to enable (WC=V IL) or disable
(WC=VIH) write instructions to the entire memory
area. When unconnected, the WC input is internally read as VIL and write operations are allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowledged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the XI2C (Extended
I2C) protocol, as summarized in Figure 4. Any device that sends data on to the bus is defined to be
a transmitter, and any device that reads the data
to be a receiver. The device that controls the data
transfer is known as the master, and the other as
the slave. A data transfer can only be initiated by
the master, which will also provide the serial clock
for synchronization. The memory device is always
a slave device in all communication.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device continuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock, SCL, is stable in the high
state. A STOP condition terminates communication between the memory device and the bus master. A STOP condition at the end of a Read
command, after (and only after) a NoACK, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a successful data transfer. The bus transmitter, either
master or slave, will release the SDA bus after
sending 8 bits of data. During the 9th clock pulse
period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transition, and the data must change only when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
8 bits to the SDA bus line (with the most significant
bit first). These bits represent the Device Select
Code (7 bits) and a RW bit.
The seven most significant bits of the Device Select Code are the Device Type Identifier, according
to the I2C bus definition. For the memory device,
the seven bits are fixed at 1010000b (A0h), as
shown in Table 5.
The 8th bit is the read or write bit (RW). This bit is
set to ‘1’ for read and ‘0’ for write operations. If a
match occurs on the Device Select Code, the cor-
Figure 3. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC
Maximum RP value (kΩ)
20
16
RL
12
RL
SDA
MASTER
8
fc = 100kHz
4
fc = 400kHz
CBUS
SCL
CBUS
0
10
100
1000
CBUS (pF)
AI01665
3/12
M14256, M14128
Figure 4. I2C Bus Protocol
SCL
SDA
START
CONDITION
SDA
INPUT
SCL
1
2
SDA
MSB
SDA
CHANGE
STOP
CONDITION
3
7
8
9
ACK
START
CONDITION
SCL
1
SDA
MSB
2
3
7
8
9
ACK
STOP
CONDITION
AI00792
responding memory gives an acknowledgment on
the SDA bus during the 9th bit time. If the memory
does not match the Device Select code, it will deselect itself from the bus, and go into stand-by
mode.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Table 3) is sent first, followed by the Least significant
Byte (Table 4). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as a Don’t
Care bit on the M14256 memory. Bits b15 and b14
are treated as Don’t Care bits on the M14128
memory.
Table 3. Most Significant Byte
b15
b14
b13
b12
b11
b10
b9
b8
Note: 1. b15 is Don’t Care on the M14256 series.
b15 and b14 are Don’t Care on the M14128 series.
Table 4. Least Significant Byte
b7
b6
b5
b4
b3
b2
b1
b0
Table 5. Device Select Code 1
Device Code
Device Select
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
0
0
0
RW
Note: 1. The most significant bit, b7, is sent first.
4/12
Chip Enable
M14256, M14128
Write Operations
Following a START condition the master sends a
Device Select code with the RW bit set to ’0’, as
shown in Table 6. The memory acknowledges it
and waits for two bytes of address, which provides
access to the memory area. After receipt of each
byte address, the memory again responds with an
acknowledge and waits for the data byte. Writing
in the memory may be inhibited if the input pin WC
is taken high.
Any write command with WC=1 (during a period of
time from the START condition until the end of the
two bytes address) will not modify the memory
content and will NOT be acknowledged on data
bytes, as shown in Figure 5.
Byte Write
In the Byte Write mode, after the Device Select
code and the address, the master sends one data
byte. If the addressed location is write protected by
the WC pin, the memory replies with a NoACK,
and the location is not modified. If, instead, the WC
pin has been held at 0, as shown in Figure 6, the
memory replies with an ACK. The master terminates the transfer by generating a STOP condition.
Page Write
The Page Write mode allows up to 64 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
(b14-b6 for the M14256 and b13-b6 for the
M14128) are the same. The master sends from
one up to 64 bytes of data, each of which is acknowledged by the memory if the WC pin is low. If
the WC pin is high, each data byte is followed by a
NoACK and the location is not modified. After each
byte is transferred, the internal byte address counter (the six least significant bits only) is incremented. The transfer is terminated by the master
generating a STOP condition. Care must be taken
to avoid address counter ’roll-over’ which could result in data being overwritten. Note that, for any
Figure 5. Write Mode Sequences with WC=1
WC
ACK
BYTE ADDR
ACK
BYTE ADDR
NO ACK
DATA IN
STOP
DEV SEL
START
BYTE WRITE
ACK
R/W
WC
ACK
DEV SEL
START
PAGE WRITE
ACK
BYTE ADDR
ACK
BYTE ADDR
NO ACK
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
NO ACK
DATA IN N
STOP
PAGE WRITE
(cont'd)
NO ACK
AI01120B
5/12
M14256, M14128
Table 6. Operating Modes
RW bit
WC 1
Bytes
‘1’
X
1
‘0’
X
‘1’
X
1
Sequential Read
‘1’
X
≥1
Byte Write
‘0’
VIL
1
START, Device Select, RW = ‘0’
Page Write
‘0’
VIL
≤ 64
START, Device Select, RW = ‘0’
Mode
Current Address Read
Initial Sequence
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
Random Address Read
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Mode
Note: 1. X = VIH or VIL.
Figure 6. Write Mode Sequences with WC=0
WC
ACK
BYTE ADDR
ACK
BYTE ADDR
ACK
DATA IN
STOP
DEV SEL
START
BYTE WRITE
ACK
R/W
WC
ACK
DEV SEL
START
PAGE WRITE
ACK
BYTE ADDR
ACK
BYTE ADDR
ACK
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
ACK
DATA IN N
STOP
PAGE WRITE
(cont'd)
ACK
AI01106B
byte or page write mode, the generation by the
master of the STOP condition starts the internal
memory program cycle. This STOP condition triggers an internal memory program cycle only if the
STOP condition is internally decoded immediately
6/12
after the ACK bit; any STOP condition decoded
out of this "10th bit" time slot will not trigger the internal programming cycle. All inputs are disabled
until the completion of this cycle and the Memory
will not respond to any request.
M14256, M14128
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by M14xxx
ACK
Returned
YES
NO
Next
Operation is
Addressing the
Memory
YES
Send
Byte Address
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI02165
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory disconnects itself from the bus, and copies the data from
its internal latches to the memory cells. The maximum write time (t w) is indicated in Table 7, but the
typical time is shorter. To make use of this, an ACK
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is as follows:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a device select byte (first byte of the
new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an ACK, indicating that the memory is
ready to receive the second part of the next instruction (the first byte of this instruction having
been sent during Step 1).
Read Operations
Read operations are independent of the state of
the WC pin. On delivery, the memory content is set
at all “1’s” (FFh).
Current Address Read
The memory has an internal address counter.
Each time a byte is read, this counter is incremented. For the Current Address Read mode, following
a START condition, the master sends a device select with the RW bit set to ‘1’. The memory acknowledges this, and outputs the byte addressed
by the internal address counter. The counter is
then incremented. The master must not acknowledge the byte output, and terminates the transfer
with a STOP condition, as shown in Figure 8.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
This is followed by another START condition from
the master and the device select is repeated with
7/12
M14256, M14128
Figure 8. Read Mode Sequences
ACK
DATA OUT
STOP
START
DEV SEL
NO ACK
R/W
ACK
START
DEV SEL *
ACK
BYTE ADDR
ACK
DEV SEL *
ACK
NO ACK
DATA OUT N
R/W
ACK
ACK
BYTE ADDR
R/W
ACK
ACK
BYTE ADDR
ACK
DEV SEL *
START
START
DEV SEL *
DATA OUT
R/W
ACK
DATA OUT 1
NO ACK
STOP
START
DEV SEL
SEQUENTIAL
RANDOM
READ
BYTE ADDR
R/W
ACK
SEQUENTIAL
CURRENT
READ
ACK
START
RANDOM
ADDRESS
READ
STOP
CURRENT
ADDRESS
READ
ACK
DATA OUT 1
R/W
NO ACK
STOP
DATA OUT N
AI01105C
st
th
Note: 1. The seven most significant bits of the Device Select bytes of a Random Read (in the 1 and 4 bytes) must be identical.
the RW bit set to ‘1’. The memory acknowledges
this, and outputs the byte addressed. The master
must not acknowledge the byte output, and terminates the transfer with a STOP condition.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. However, in this case the master does acknowledge
the data byte output, and the memory continues to
output the next byte in sequence. To terminate the
stream of bytes, the master must not acknowledge
the last byte output, and must generate a STOP
condition. The output data comes from consecu-
8/12
tive addresses, with the internal address counter
automatically incremented after each byte output.
After the last memory address, the address
counter will ‘roll-over’ and the memory will continue to output data from the start of the memory
block.
Acknowledge in Read Mode
In all read modes the memory waits for an acknowledgment during the 9th bit time. If the master
does not pull the SDA line low during this time, the
memory terminates the data transfer and switches
to its standby state.
M14256, M14128
Table 7. AC Characteristics
(TA = 0 to 70 °C; VCC = 2.5 V to 5.5 V)
Symbol
Alt.
Fast I2C
400 kHz
Parameter
Min
Max
I2C
100 kHz
Min
Unit
Max
2
tR
Clock Rise Time
300
1000
ns
tCL1CL2 2
tF
Clock Fall Time
300
300
ns
2
tR
SDA Rise Time
20
300
20
1000
ns
tDL1DL2 2
tF
SDA Fall Time
20
300
20
300
ns
tCHDX 1
tSU:STA
Clock High to Input Transition
600
4700
ns
tCHCL
tHIGH
Clock Pulse Width High
600
4000
ns
tDLCL
tHD:STA
Input Low to Clock Low (START)
600
4000
ns
tCLDX
tHD:DAT
Clock Low to Input Transition
0
0
µs
tCLCH
tLOW
Clock Pulse Width Low
1.3
4.7
µs
tDXCX
tSU:DAT
Input Transition to Clock Transition
100
250
ns
tCHDH
tSU:STO
Clock High to Input High (STOP)
600
4000
ns
tDHDL
tBUF
Input High to Input Low (Bus Free)
1.3
4.7
µs
tCLQV
tAA
Clock Low to Data Out Valid
tCLQX
tDH
Data Out Hold Time After Clock Low
fC
fSCL
Clock Frequency
400
100
kHz
tW
tWR
Write Time
10
10
ms
tCH1CH2
tDH1DH2
1000
200
3500
200
ns
ns
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested
Table 8. DC Characteristics
(TA = 0 to 70 °C; VCC = 2.5 V to 5.5 V)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
0 V ≤ VIN ≤ VCC
±2
µA
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
±2
µA
VCC=5V, fc=400kHz (rise/fall time < 30ns)
2
mA
VCC =2.5V, fc=400kHz (rise/fall time < 30ns)
1
mA
VIN = VSS or VCC , VCC = 5 V
20
µA
VIN = VSS or VCC , VCC = 2.5 V
2
µA
ILI
Input Leakage Current (SCL,
SDA)
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current
(Stand-by)
VIL
Input Low Voltage (SCL, SDA)
- 0.3
0.3 VCC
V
VIH
Input High Voltage (SCL, SDA)
0.7 VCC
VCC + 1
V
VIL
Input Low Voltage (WC)
- 0.3
0.5
V
VIH
Input High Voltage (WC)
VCC - 0.5
VCC + 1
V
Output Low
Voltage
IOL = 3 mA, VCC = 5 V
0.4
V
VOL
IOL = 2.1 mA, VCC = 2.5 V
0.4
V
9/12
M14256, M14128
Figure 9. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
tDXCX
tCHDH
SDA IN
tCHDX
tCLDX
START
CONDITION
tDHDL
SDA
INPUT
SDA
CHANGE
STOP &
BUS FREE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
SCL
tW
SDA IN
tCHDH
tCHDX
STOP
CONDITION
WRITE CYCLE
START
CONDITION
AI00795B
Table 9. AC Measurement Conditions
Figure 10. AC Testing Input Output Waveforms
≤ 50 ns
Input Rise and Fall Times
0.8VCC
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing
Reference Voltages
0.3VCC to 0.7VCC
0.7VCC
0.3VCC
0.2VCC
AI00825
Table 10. Input Parameters1 (TA = 25 °C, f = 400 kHz)
Symbol
Parameter
Min.
Max.
Unit
CIN
Input Capacitance (SDA)
8
pF
CIN
Input Capacitance (other pins)
6
pF
tNS
Low Pass Filter Input Time
Constant (SCL & SDA Inputs)
400
ns
Note: 1. Sampled only, not 100% tested.
10/12
Test Condition
100
M14256, M14128
Table 11. Ordering Information Scheme
Example:
M14256
-
W
D22
Delivery Form
D22
Module on Super 35 mm
film
W
2.5 V to 5.5 V
Memory Capacity
256
256 Kbit
128
128 Kbit
Operating Voltage
ORDERING INFORMATION
Devices are shipped from the factory with the memory content set at all ‘1’s (FFh).
The notation used for the device number is as shown in Table 11. For a list of available options (speed,
package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office
nearest to you.
11/12
M14256, M14128
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
© 1999 STMicroelectronics - All Rights Reserved
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All other names are the property of their respective owners.
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