VISHAY SIHFP460LC-E3

IRFP460LC, SiHFP460LC
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
•
•
•
•
•
•
•
•
500
RDS(on) (Ω)
VGS = 10 V
0.27
Qg (Max.) (nC)
120
Qgs (nC)
32
Qgd (nC)
49
Configuration
Single
D
Ultra Low Gate Charge
Reduced Gate Drive Requirement
Enhanced 30 V VGS Rating
Reduced Ciss, Coss, Crss
Isolated Central Mounting Hole
Dynamic dV/dt Rating
Repetitive Avalanche Rated
Lead (Pb)-free Available
Available
RoHS*
COMPLIANT
DESCRIPTION
TO-247
This new series of low charge Power MOSFETs achieve
significantly lower gate charge over conventional MOSFETs.
Utilizing advanced Power MOSFETs technology the device
improvements allow for reduced gate drive requirements,
faster switching speeds and increased total system savings.
These device improvements combined with the proven
ruggedness and reliabiltity of Power MOSFETs offer the
designer a new standard in power transistors for switching
applications.
The TO-247 package is preferred for commercial-industrial
applications where higher power levels preclude the use of
TO-220 devices. The TO-247 is similar but superior to the
earlier TO-218 package because its isolated mounting hole.
G
S
D
G
S
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-247
IRFP460LCPbF
SiHFP460LC-E3
IRFP460LC
SiHFP460LC
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
SYMBOL
VDS
VGS
VGS at 10 V
TC = 25 °C
TC = 100 °C
Currenta
Pulsed Drain
Linear Derating Factor
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
Maximum Power Dissipation
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
ID
IDM
TC = 25 °C
for 10 s
6-32 or M3 screw
EAS
IAR
EAR
PD
dV/dt
TJ, Tstg
LIMIT
500
± 30
20
12
80
2.2
960
20
28
280
3.5
- 55 to + 150
300d
10
1.1
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
lbf · in
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, starting TJ = 25 °C, L = 4.3 mH, RG = 25 Ω, IAS = 20 A (see fig. 12).
c. ISD ≤ 20 A, dI/dt ≤ 160 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
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IRFP460LC, SiHFP460LC
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
-
Case-to-Sink, Flat, Greased Surface
RthCS
0.24
-
Maximum Junction-to-Case (Drain)
RthJC
-
0.45
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VDS
VGS = 0 V, ID = 250 µA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.59
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 500 V, VGS = 0 V
-
-
25
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
Gate-Source Threshold Voltage
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 12 Ab
VGS = 10 V
VDS = 50 V, ID = 12 Ab
µA
-
-
0.27
Ω
12
-
-
S
-
3600
-
-
440
-
-
39
-
-
-
120
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
-
-
32
Gate-Drain Charge
Qgd
-
-
49
Turn-On Delay Time
td(on)
-
18
-
tr
-
77
-
-
40
-
-
43
-
-
5.0
-
-
13
-
-
-
20
-
-
80
-
-
1.8
-
570
860
ns
-
6.6
9.9
µC
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
VGS = 10 V
ID = 20 A, VDS = 400 V,
see fig. 6 and 13b
VDD = 250 V, ID = 20 A
RG = 4.3 Ω, RD = 12 Ω, see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
D
pF
nC
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Currenta
Body Diode Voltage
IS
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 20 A, VGS = 0 Vb
TJ = 25 °C, IF = 20 A, dI/dt = 100 A/µsb
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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Document Number: 91235
S-81360-Rev. A, 28-Jul-08
IRFP460LC, SiHFP460LC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFP460LC, SiHFP460LC
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
IRFP460LC, SiHFP460LC
Vishay Siliconix
RD
VDS
VGS
D.U.T.
RG
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T.
RG
+
-
I AS
V DD
VDS
10 V
tp
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
IAS
Fig. 12b - Unclamped Inductive Waveforms
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IRFP460LC, SiHFP460LC
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
IRFP460LC, SiHFP460LC
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91235.
Document Number: 91235
S-81360-Rev. A, 28-Jul-08
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
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information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
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Document Number: 91000
Revision: 18-Jul-08
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