M29F512B 512 Kbit (64Kb x8, Bulk) Single Supply Flash Memory PRELIMINARY DATA ■ SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ■ ACCESS TIME: 45ns ■ PROGRAMMING TIME – 8µs per Byte typical ■ PROGRAM/ERASE CONTROLLER – Embedded Byte Program algorithm – Embedded Chip Erase algorithm – Status Register Polling and Toggle Bits ■ TSOP32 (NZ) 8 x 14mm PLCC32 (K) UNLOCK BYPASS PROGRAM COMMAND – Faster Production/Batch Programming ■ LOW POWER CONSUMPTION – Standby and Automatic Standby ■ 100,000 PROGRAM/ERASE CYCLES ■ 20 YEARS DATA RETENTION Figure 1. Logic Diagram – Defectivity below 1 ppm/year ■ ELECTRONIC SIGNATURE – Manufacturer Code: 20h VCC – Device Code: 24h 16 8 A0-A15 W DQ0-DQ7 M29F512B E G VSS AI02739 July 1999 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/16 M29F512B NC NC A15 A12 A7 A6 A5 A4 1 8 9 32 M29F512B 16 25 24 17 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 AI02741 Table 1. Signal Names A0-A15 Address Inputs DQ0-DQ7 Data Inputs/Outputs E Chip Enable G Output Enable W Write Enable VCC Supply Voltage VSS Ground NC Not Connected Internally SUMMARY DESCRIPTION The M29F512B is a 512 Kbit (64Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re2/16 1 32 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 9 M29F512B 25 A14 A13 A8 A9 A11 G A10 E DQ7 17 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 A11 A9 A8 A13 A14 NC W VCC A12 A15 NC NC VCC W NC Figure 2B. PLCC Connections Figure 2A. TSOPConnections AI02930 quired to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in TSOP32 (8 x 14mm) and PLCC32 packages. Access times of 45ns and 70ns are available. The memory is supplied with all the bits erased (set to ’1’). SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A15). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. M29F512B Table 2. Absolute Maximum Ratings (1) Symbol TA Parameter Ambient Operating Temperature Value Unit 0 to 70 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C VIO (2) Input or Output Voltage –0.6 to 6 V VCC Supply Voltage –0.6 to 6 V VID Identification Voltage –0.6 to 13.5 V Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3. Vss Ground. The VSS Ground is the reference for all voltage measurements. BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 3, Bus Operations, for a summary. Typically glitches of less than 5ns are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 7, Read Mode AC Waveforms, and Table 10, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 8 and 9, Write AC Waveforms, and Tables 11 and 12, Write AC Characteristics, for details of the timing requirements. 3/16 M29F512B Table 3. Bus Operations Operation G W Bus Read VIL VIL VIH Cell Address Bus Write VIL VIH VIL Command Address X VIH VIH X Hi-Z Standby VIH X X X Hi-Z Read Manufacturer Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH 20h Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH 24h Output Disable Address Inputs Data Inputs/Outputs E Data Output Data Input Note: X = VIL or VIH. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V IH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 9, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 3, Bus Operations. 4/16 COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The commands are summarized in Table 4, Commands. Refer to Table 4 in conjunction with the text descriptions below. Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Chip Erase operation the memory will take about 10µs to abort the Chip Erase. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Chip Erase operation will leave invalid data in the memory. Auto Select Command. The Auto Select command is used to read the Manufacturer Code and the Device Code. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued. M29F512B Command Length Table 4. Commands Bus Write Operations 1st 2nd Addr Data 1 X F0 3 555 Auto Select 3 Program 3rd 4th Addr Data Addr Data AA 2AA 55 X F0 555 AA 2AA 55 555 90 4 555 AA 2AA 55 555 A0 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 80 5th Addr Data PA PD 555 AA 6th Addr Data Addr Data 2AA 55 555 10 Read/Reset Note: X Don’t Care, PA Program Address, PD Program Data. All values in the table are in hexadecimal. The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care. Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID or Device ID. Program, Unlock Bypass Program, Chip Erase. After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = VIL. The other address bits may be set to either V IL or VIH. The Manufacturer Code for STMicroelectronics is 20h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either V IL or VIH. The Device Code for the M29F512B is 24h. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 5. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’ and attempting to do so will cause an error. The Chip Erase command must be used to set all the bits in the memory from ’0’ to ’1’. Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. 5/16 M29F512B Table 5. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70°C) Typ(1) Typical after 100k W/E Cycles(1) Chip Erase (All bits in the memory set to ‘0’) 0.4 0.4 Chip Erase 0.8 0.8 4 sec 8 8 150 µs 0.6 0.6 2.5 sec Parameter Min Program Chip Program Program/Erase Cycles 100,000 Max Unit sec cycles Note: 1. TA = 25°C, VCC = 5V. Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. The operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/ Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior. Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Chip Erase Command. The Chip Erase command can be used to erase the memory. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. Typical chip erase times are given in Table 5. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase command sets all of the bits in the memory to ’1’. All previous data is lost. 6/16 STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 6, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. Figure 3, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or any address while erasing the chip. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. Figure 4, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit. M29F512B Table 6. Status Register Bits Operation Address DQ7 DQ6 DQ5 Program Any Address DQ7 Toggle 0 Program Error Any Address DQ7 Toggle 1 Chip Erase Any Address 0 Toggle 0 Erase Error Any Address 0 Toggle 1 Note: Unspecified data bits should be ignored. Figure 3. Data Polling Flowchart Figure 4. Data Toggle Flowchart START START READ DQ5 & DQ7 at VALID ADDRESS READ DQ5 & DQ6 DQ7 = DATA DQ6 = TOGGLE YES YES NO NO NO DQ5 =1 DQ5 =1 YES YES READ DQ7 READ DQ6 DQ7 = DATA DQ6 = TOGGLE YES NO YES NO FAIL NO PASS AI01369 Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Program or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before oth- FAIL PASS AI01370 er commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set at ’0’ back to ’1’ and attempting to do so will cause an error. The Chip Erase command must be used to set all the bits the memory from ’0’ to ’1’. 7/16 M29F512B Table 7. AC Measurement Conditions Load Capacitance (CL) Figure 6. AC Testing Load Circuit 30pF Input Rise and Fall Times ≤ 10ns Input Pulse Voltages 0 to 3V Input and Output Timing Ref. Voltages 1.3V 1N914 1.5V 3.3kΩ Figure 5. AC Testing Input Output Waveform DEVICE UNDER TEST OUT CL = 30pF 3V 1.5V 0V AI01417 CL includes JIG capacitance AI02979 Table 8. Capacitance (TA = 25 °C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Note: Sampled only, not 100% tested. 8/16 Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF M29F512B Table 9. DC Characteristics (TA = 0 to 70°C) Symbol Parameter Test Condition Min Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA E = VIL, G = VIH, f = 6MHz 15 mA ILI Input Leakage Current ILO Output Leakage Current ICC1 Supply Current (Read) ICC2 Supply Current (Standby) E = VCC ± 0.2V 100 µA Supply Current (Program/Erase) Program/Erase Controller active 20 mA ICC3 (1) VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage IOL = 5.8mA 0.45 V VOH Output High Voltage IOH = –100µA VID Identification Voltage IID Identification Current VLKO (1) Program/Erase Lockout Supply Voltage VCC – 0.4 11.5 A9 = VID 3.2 V 12.5 V 100 µA 4.2 V Note: 1. Sampled only, not 100% tested. 9/16 M29F512B Table 10. Read AC Characteristics (TA = 0 to 70°C) M29F512B Symbol Alt Parameter Test Condition Unit 45 70 tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL Min 45 70 ns tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL Max 45 70 ns tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns tELQV tCE Chip Enable Low to Output Valid G = VIL Max 45 70 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns tGLQV tOE Output Enable Low to Output Valid E = VIL Max 25 30 ns tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 15 20 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 15 20 ns tEHQX tGHQX tAXQX tOH Chip Enable, Output Enable or Address Transition to Output Transition Min 0 0 ns Note: 1. Sampled only, not 100% tested. Figure 7. Read Mode AC Waveforms tAVAV A0-A15 VALID tAVQV tAXQX E tELQV tEHQX tELQX tEHQZ G tGLQX tGLQV DQ0-DQ7 tGHQX tGHQZ VALID AI02977 10/16 M29F512B Table 11. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70 °C) M29F512B Symbol Alt Parameter Unit 45 70 tAVAV tWC Address Valid to Next Address Valid Min 45 70 ns tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns tWLWH tWP Write Enable Low to Write Enable High Min 40 45 ns tDVWH tDS Input Valid to Write Enable High Min 25 30 ns tWHDX tDH Write Enable High to Input Transition Min 0 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 ns tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns tWLAX tAH Write Enable Low to Address Transition Min 40 45 ns Output Enable High to Write Enable Low Min 0 0 ns tGHWL tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs Figure 8. Write AC Waveforms, Write Enable Controlled tAVAV A0-A15 VALID tWLAX tAVWL tWHEH E tELWL tWHGL G tGHWL tWLWH W tWHWL tDVWH DQ0-DQ7 tWHDX VALID VCC tVCHEL AI02757 11/16 M29F512B Table 12. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70 °C) M29F512B Symbol Alt Unit Parameter 45 70 tAVAV tWC Address Valid to Next Address Valid Min 45 70 ns tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High Min 40 45 ns tDVEH tDS Input Valid to Chip Enable High Min 25 30 ns tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 ns tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns tELAX tAH Chip Enable Low to Address Transition Min 40 45 ns Output Enable High Chip Enable Low Min 0 0 ns tGHEL tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs Figure 9. Write AC Waveforms, Chip Enable Controlled tAVAV A0-A15 VALID tELAX tAVEL tEHWH W tWLEL tEHGL G tGHEL tELEH E tEHEL tDVEH DQ0-DQ7 tEHDX VALID VCC tVCHWL AI02758 12/16 M29F512B Table 13. Ordering Information Scheme Example: M29F512B 70 NZ 1 T Device Type M29 Operating Voltage F = VCC = 5V ± 10% Device Function 512B = 512 Kbit (64Kb x8), Bulk Speed 45 = 45 ns 70 = 70 ns Package NZ = TSOP32: 8 x 14 mm K = PLCC32 Temperature Range 1 = 0 to 70 °C Option T = Tape & Reel Packing Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are shipped from the factory with the memory content erased (to FFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 13/16 M29F512B Table 14. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Mechanical Data mm inches Symbol Typ Min Max A Typ Min 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 B 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 13.80 14.20 0.543 0.559 D1 12.30 12.50 0.484 0.492 E 7.90 8.10 0.311 0.319 – – – – L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N 32 e 0.50 0.020 32 CP 0.10 0.004 Figure 10. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C TSOP-a Drawing is not to scale. 14/16 Max A1 α L M29F512B Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data mm Symbol Typ inches Min Max A 2.54 A1 1.52 A2 Typ Min Max 3.56 0.100 0.140 2.41 0.060 0.095 0.38 0.015 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 – – – – 0.00 0.25 0.000 0.010 – – – – e 1.27 F R 0.89 0.050 0.035 N 32 32 Nd 7 7 Ne 9 9 CP 0.10 0.004 Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline D D1 A1 A2 1 N B1 E1 E Ne e D2/E2 F B 0.51 (.020) 1.14 (.045) A Nd R CP PLCC Drawing is not to scale. 15/16 M29F512B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 16/16