M40Z111 M40Z111W NVRAM CONTROLLER for up to TWO LPSRAM CONVERT LOW POWER SRAMs into NVRAMs PRECISION POWER MONITORING and POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION when VCC is OUT-OF-TOLERANCE CHOICE of SUPPLY VOLTAGES and POWER-FAIL DESELECT VOLTAGES: – M40Z111: VCC = 4.5V to 5.5V THS = VSS 4.5V ≤ VPFD ≤ 4.75V THS = VOUT 4.2V ≤ VPFD ≤ 4.5V – M40Z111W: VCC = 3.0V to 3.6V THS = VSS 2.8V ≤ VPFD ≤ 3.0V VCC = 2.7V to 3.3V THS = VOUT 2.5 ≤ VPFD ≤ 2.7V LESS THAN 15ns CHIP ENABLE ACCESS PROPAGATION DELAY (for 5.0V device) PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT® TOP (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY DESCRIPTION The M40Z111/111W NVRAM Controller is a selfcontained device which converts a standard lowpower SRAM into a non-volatile memory. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. SNAPHAT (SH) Battery 28 1 SOH28 (MH) Figure 1. Logic Diagram VCC THS VOUT M40Z111 M40Z111W E ECON Table 1. Signal Names THS Threshold Select Input E Chip Enable Input ECON Conditioned Chip Enable Output VOUT Supply Voltage Output VCC Supply Voltage VSS Ground February 1999 VSS AI02238B 1/12 M40Z111, M40Z111W Table 2. Absolute Maximum Ratings Symbol TA TSTG TSLD (2) (1) Parameter Value Unit Ambient Operating Temperature 0 to 70 °C Storage Temperature (VCC Off) SNAPHAT SOIC Lead Solder Temperature for 10 seconds –40 to 85 –55 to 125 260 °C °C VIO Input or Output Voltages –0.3 to VCC +0.3 V VCC Supply Voltage –0.3 to 7 V IO Output Current 20 mA PD Power Dissipation 1 W Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. Figure 2. SOIC Pin Connections VOUT NC NC NC NC VCC NC VCC NC NC NC NC THS VSS 1 28 27 2 26 3 25 4 24 5 23 6 7 M40Z111 22 8 M40Z111W 21 20 9 19 10 18 11 17 12 16 13 15 14 VCC E NC NC NC NC NC NC NC NC NC NC ECON NC AI02239B Warning: NC = Not Connected. DESCRIPTION (cont’d) When an invalid VCC condition occurs, the conditioned chip enable (ECON) output is forced inactive to write-protect the stored data in the SRAM. 2/12 During a power failure, the SRAM is switched from the VCC pin to the lithium cell within the SNAPHAT to provide the energy required for data retention. On a subsequent power-up, the SRAM remains write protected until a valid power condition returns. The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic antistatic tubes or in Tape & Reel form. For the 28 lead SOIC, the battery package (i.e. SNAPHAT) part number is "M4Z28-BR00SH1" or "M4Z32BR00SH1" (See Table 7). OPERATION The M40Z111/111W, as shown in Figure 4, can control up to two standard low-power SRAMs. These SRAMs must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (ECON) output pin follows the chip enable (E) input pin with timing shown in Table 6. An internal switch connects VCC to VOUT. This switch has a voltage drop of less than 0.3V (IOUT1). M40Z111, M40Z111W Figure 3. Hardware Hookup 3.3V or 5V VCC 1N5817 or MBR5120T3 VOUT 0.1µF CMOS SRAM 0.1µF M40Z111 E Thereshold VCC ECON E x8 or x16 THS VSS AI02394 When VCC degrades during a power failure,ECON is forced inactive independent of E. In this situation, the SRAM is unconditionally write protected as VCC falls below an out-of-tolerance threshold (VPFD). The power fail detection value associated with VPFD is selected by the THS pin and is shown in Table 5. (Note: THS pin must be connected to either VSS or VOUT). If chip enable access is in progress during a power fail detection, that memory cycle continues to completion before the memory is write protected. If the memory cycle is not terminated within time tWP, ECON is unconditionally driven high, write protecting the SRAM. A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the SRAM’s contents. At voltages below VPFD (min), the user can be assured the memory will be write protected provided the VCC fall time exceeds tF. As VCC continues to degrade, the internal switch disconnects VCC and connects the internal battery to VOUT. This occurs at the switchover voltage (VSO). Below the VSO, the battery provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Table 5). When VCC rises above VSO, VOUT is switched back to the supply voltage. Output ECON is held inactive for tER (200ms maximum) after the power supply has reached VPFD, independent of the E input, to allow for processor stabilization (see Figure 6). DATA RETENTION LIFETIME CALCULATION Most low power SRAMs on the market today can be used with the M40Z111/111W NVRAM Controller. There are, however some criteria which should be used in making the final choice of which SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M40Z111/111W and SRAMs to be Don’t Care once VCC falls below VPFD (min). The SRAM should also guarantee data retention down to VCC =2.0V. The chip enable access time must be sufficient to meet the system needs with the chip enable propagation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT. If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0V. 3/12 M40Z111, M40Z111W Table 3. AC Measurement Condition Input Rise and Fall Times ≤ 5ns Input Pulse Voltages 0 to 3V Input and Output Timing Ref. Voltages 1.5V Figure 4. AC Testing Load Circuit 645Ω DEVICE UNDER TEST Note that Output Hi-Z is defined as the point where data is no longer driven. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the ICCDR value of the M40Z111/111W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT of your choice can then be divided by this current to determine the amount of data retention available (see Table 7). For more information on Battery Storage Life refer to the Application Note AN1012. VCC NOISE AND NEGATIVE-GOING TRANSIENTS ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. CL = 100pF or 5pF CL includes JIG capacitance 1.75V AI02326 A ceramic bypass capacitor value of 0.1µF (as shown in Figure 4) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Table 4. Capacitance (1) (TA = 25°C; f = 1MHz) Symbol CIN COUT Parameter Input Capacitance (2) Output Capacitance Note: 1. Sampled only, not 100% tested. 2. Outputs deselected. 4/12 Test Condition Min Max Unit VIN = 0V 8 pF VOUT = 0V 10 pF M40Z111, M40Z111W Table 5A. DC Characteristics for M40Z111 (TA = 0 to 70°C; VCC = 4.5V to 5.5V) Symbol Parameter ILI (1) Input Leakage Current ILO (1) Output Leakage Current Test Condition Min Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA 6 mA Outputs open Typ ICC Supply Current 3 VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2.2 VCC + 0.3 V VOL Output Low Voltage IOL = 4.0mA 0.4 V VOH Output High Voltage IOH = –2.0mA 2.4 VOHB VOH Battery Back-up IOUT2 = 1.0µA 2.0 IOUT1 VOUT Current (Active) 3.6 V VOUT > VCC –0.3 160 mA VOUT > VCC –0.2 100 mA IOUT2 VOUT Current (Battery Back-up) ICCDR Data Retention Mode Current THS Threshold Select Voltage VSS Power-fail Deselect Voltage (THS = 0) 4.5 Power-fail Deselect Voltage (THS = 1) 4.2 VPFD VSO Battery Back-up Switchover Voltage V VOUT > VBAT –0.3 2.9 µA 100 150 nA VOUT V 4.6 4.75 V 4.35 4.5 V 3.0 V Note: 1. Outputs deselected. 5/12 M40Z111, M40Z111W Table 5B. DC Characteristics for M40Z111W (TA = 0 to 70°C; VCC = 3V to 3.6V or 2.7V to 3.3V) Symbol Parameter ILI (1) Input Leakage Current ILO (1) Output Leakage Current Test Condition Min Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA 4 mA Outputs open Typ ICC Supply Current 2 VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2.0 VCC + 0.3 V VOL Output Low Voltage IOL = 4.0mA 0.4 V VOH Output High Voltage IOH = –2.0mA 2.4 VOHB VOH Battery Back-up IOUT2 = 1.0µA 2.0 IOUT1 VOUT Current (Active) 3.6 V VOUT > VCC –0.3 100 mA VOUT > VCC –0.2 65 mA IOUT2 VOUT Current (Battery Back-up) ICCDR Data Retention Mode Current THS Threshold Select Voltage VSS Power-fail Deselect Voltage (THS = 0) 2.8 Power-fail Deselect Voltage (THS = 1) 2.5 VPFD VSO Battery Back-up Switchover Voltage Note: 1. Outputs deselected. 6/12 V VOUT > VBAT –0.3 2.9 µA 100 150 nA VOUT V 2.9 3.0 V 2.6 2.7 V 2.5 V M40Z111, M40Z111W Table 6. Power Down/Up AC Characteristics (TA = 0 to 70°C) Symbol tF Parameter (1) tFB (2) tR tEDH Max Unit VPFD (max) to VPFD (min) VCC Fall Time 300 µs VPFD (min) to VSO VCC Fall Time 10 µs VPFD(min) to VPFD (max) VCC Rise Time 10 µs Chip Enable Propagation Delay tEDL Min Chip Enable Propagation Delay tER Chip Enable Recovery tWP Write Protect Time M40Z111 15 ns M40Z111W 20 ns M40Z111 10 ns M40Z111W 20 ns 40 200 ms M40Z111 40 150 µs M40Z111W 40 250 µs Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after VCC passes VPFD (min). 2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data. Figure 5. Power Down Timing VCC VPFD (max) VPFD VPFD (min) VSO tF tFB E tWPT VOHB ECON AI02396 7/12 M40Z111, M40Z111W Figure 6. Power Up Timing VCC VPFD (max) VPFD VPFD (min) VSO tR tER E tEDH ECON tEDL VOHB AI02397 Table 7. Battery Table 8/12 Part Number Description Package M4Z28-BR00SH1 Lithium Battery (50mAh) SNAPHAT SH M4Z32-BR00SH1 Lithium Battery (130mAh) SNAPHAT SH M40Z111, M40Z111W ORDERING INFORMATION SCHEME Example: M40Z111W Supply Voltage and Write Protect Voltage 111 VCC = 4.5V to 5.5V THS = VSS 4.5V ≤ VPFD ≤ 4.75V THS = VOUT 4.2V ≤ VPFD ≤ 4.5V MH 1 TR Package MH(1) SOH28 Temp. Range 1 0 to 70 °C Shipping Method for SOIC blank Tubes TR Tape & Reel 111W VCC = 3.0V to 3.6V THS = VSS 2.8V ≤ VPFD ≤ 3.0V VCC = 2.7V to 3.3V THS = VOUT 2.5 ≤ VPFD ≤ 2.7V Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number "M4ZxxBR00SH1" in plastic tube or "M4Zxx-BR00SH1TR" in Tape & Reel form. Caution: Do not place the SNAPHAT battery package "M4Zxx-BR00SH1" in conductive foam since will drain the lithium button-cell battery. For a list of available options (Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 9/12 M40Z111, M40Z111W SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT mm Symb Typ inches Min Max A Typ Min 3.05 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 – – – – eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 α 0° 8° 0° 8° N 28 e 1.27 0.050 28 CP 0.10 A2 0.004 A C B eB e CP D N E H A1 1 SOH-A Drawing is not to scale. 10/12 Max α L M40Z111, M40Z111W SH - SNAPHAT Housing for 28 lead Plastic Small Outline mm Symb Typ Min A inches Max Typ Min Max 9.78 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 A1 eA A2 A A3 B L eB D E SH Drawing is not to scale. 11/12 M40Z111, M40Z111W Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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