STMICROELECTRONICS M41T00SM6E

M41T00S
Serial Access Real-Time Clock
FEATURES SUMMARY
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2.0 TO 5.5V CLOCK OPERATING VOLTAGE
COUNTERS FOR SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY
SOFTWARE CLOCK CALIBRATION
AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY (FIXED
REFERENCE)
– VCC = 2.7 to 5.5V
2.5V ≤ VPFD ≤ 2.7V
SERIAL INTERFACE SUPPORTS I2C BUS
(400kHz PROTOCOL)
LOW OPERATING CURRENT OF 300µA
OSCILLATOR STOP DETECTION
BATTERY OR SUPER-CAP BACK-UP
OPERATING TEMPERATURE OF –40 TO
85°C
ULTRA-LOW BATTERY SUPPLY CURRENT
OF 1µA
December 2004
Figure 1. Packages
8
1
SO8 (M)
8-pin SOIC
1/23
M41T00S
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Table 1.
Figure 3.
Figure 4.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
8-pin SOIC (M) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Oscillator Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Preferred Initial Power-on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Preferred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/23
M41T00S
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16.SO8 – 8-lead Plastic Small Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. SO8 – 8-lead Plastic Small Outline (150 mils body width), Package Mech. Data . . . . . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
M41T00S
SUMMARY DESCRIPTION
The M41T00S Serial Access TIMEKEEPER ®
SRAM is a low power Serial RTC with a built-in
32.768kHz oscillator (external crystal controlled).
Eight bytes of the SRAM (see Table 2., page 11)
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a
two line, bi-directional I2C interface. The built-in
address register is incremented automatically after each WRITE or READ data byte.
The M41T00S has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power failure occurs. The energy needed to sustain the
clock operations can be supplied by a small lithium
button supply when a power failure occurs. The
eight clock address locations contain the century,
year, month, date, day, hour, minute, and second
in 24 hour BCD format. Corrections for 28, 29
(leap year - valid until year 2100), 30 and 31 day
months are made automatically.
The M41T00S is supplied in an 8-pin SOIC.
Figure 2. Logic Diagram
Table 1. Signal Names
VCC VBAT
XI(1)
XI(1)
Oscillator Input
XO(1)
Oscillator Output
FT/OUT
(1)
Frequency Test / Output Driver
(Open Drain)
XO
M41T00S
FT/OUT
SCL
SDA
VSS
SDA
Serial Data Input/Output
SCL
Serial Clock Input
VBAT
Battery Supply Voltage
VCC
Supply Voltage
VSS
Ground
AI09165
Note: 1. For SO8 package only.
Note: 1. For SO8 package only.
Figure 3. 8-pin SOIC (M) Connections
XI
XO
VBAT
VSS
1
8
7
2
3 M41T00S 6
4
5
VCC
(1)
FT/OUT
SCL
SDA
AI09166
Note: 1. Open Drain Output
4/23
M41T00S
Figure 4. Block Diagram
REAL TIME CLOCK
CALENDAR
32KHz
OSCILLATOR
CRYSTAL
OSCILLATOR FAIL
CIRCUIT
RTC &
CALIBRATION
FREQUENCY TEST
SDA
I2C
INTERFACE
SCL
WRITE
PROTECT
VCC
OUTPUT DRIVER
FT
FT/OUT(1)
OUT
INTERNAL
POWER
VBAT
VSO
COMPARE
VPFD
AI09168
Note: 1. Open Drain Output
5/23
M41T00S
OPERATION
The M41T00S clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device
can then be accessed sequentially in the following
order:
1. Seconds Register
2. Minutes Register
3. Century/Hours Register
4. Day Register
5. Date Register
6. Month Register
7. Year Register
8. Calibration Register
The M41T00S clock continually monitors VCC for
an out-of-tolerance condition. Should VCC fall below VPFD, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
Once VCC falls below the switchover voltage
(VSO ), the device automatically switches over to
the battery and powers down into an ultra-low current mode of operation to preserve battery life. If
VBAT is less than VPFD, the device power is
switched from VCC to VBAT when VCC drops below
VBAT. If VBAT is greater than VPFD, the device
power is switched from VCC to VBAT when VCC
drops below VPFD. Upon power-up, the device
switches from battery to VCC at VSO. When VCC
rises above VPFD, it will recognize the inputs.
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the
bus is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
6/23
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from high to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The devices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
M41T00S
Figure 5. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 6. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
1
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
7/23
M41T00S
READ Mode
In this mode the master reads the M41T00S slave
after setting the slave address (see Figure
8., page 9). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address 'An' is written to the on-chip address
pointer. Next the START condition and slave address are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an Acknowledge Bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41T00S slave transmitter will now
place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the
new byte and the address pointer is incremented
to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 06h). The update will resume due
to a Stop Condition or when the pointer increments
to any non-clock address (07h).
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implemented whereby the master reads the M41T00S slave
without first writing to the (volatile) address pointer. The first address that is read is the last one
stored in the pointer (see Figure 9., page 9).
Figure 7. Slave Address Location
R/W
START
A
1
LSB
MSB
SLAVE ADDRESS
1
0
1
0
0
0
AI00602
8/23
M41T00S
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
ACK
S
ACK
BUS ACTIVITY:
R/W
START
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 8. READ Mode Sequence
STOP
SLAVE
ADDRESS
DATA n+X
P
NO ACK
AI00899
STOP
R/W
SLAVE
ADDRESS
DATA n+X
P
NO ACK
BUS ACTIVITY:
DATA n+1
ACK
DATA n
ACK
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 9. Alternative READ Mode Sequence
AI00895
9/23
M41T00S
WRITE Mode
In this mode the master transmitter transmits to
the M41T00S slave receiver. Bus protocol is
shown in Figure 10. Following the START condition and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T00S slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
see Figure 7., page 8 and again after it has received the word address and each data byte.
Data Retention Mode
With valid VCC applied, the M41T00S can be accessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the power input will be switched from the VCC pin to the
battery when VCC falls below the Battery Back-up
Switchover Voltage (VSO). At this time the clock
registers will be maintained by the attached battery supply. On power-up, when VCC returns to a
nominal value, write protection continues for tREC.
For a further, more detailed review of lifetime calculations, please see Application Note AN1012.
SLAVE
ADDRESS
10/23
STOP
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 10. WRITE Mode Sequence
AI00591
M41T00S
CLOCK OPERATION
The 8-byte Register Map (see Table 2) is used to
both set the clock and to read the date and time
from the clock, in a binary coded decimal format.
Seconds, Minutes, and Hours are contained within
the first three registers.
Bits D6 and D7 of Clock Register 02h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
03h contain the Day (day of week). Registers 04h,
05h, and 06h contain the Date (day of month),
Month and Years. The eighth clock register is the
Calibration Register (this is described in the Clock
Calibration section). Bit D7 of Register 00h contains the STOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expected to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts
within one second.
The seven Clock Registers may be read one byte
at a time, or in a sequential block. The Calibration
Register (Address location 07h) may be accessed
independently. Provision has been made to assure that a clock update does not occur while any
of the seven clock addresses are being read. If a
clock address is being read, an update of the clock
registers will be halted. This will prevent a transition of data during the READ.
Clock Registers
The M41T00S offers 8 internal registers which
contain Clock and Calibration data. These registers are memory locations which contain external
(user accessible) and internal copies of the data
(usually referred to as BiPORT™ TIMEKEEPER
cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the
incremented internal copy. The internal divider (or
clock) chain will be reset upon the completion of a
WRITE to any clock address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 06h). The update will resume either due to a Stop Condition or when the pointer
increments to any non-clock address (07h).
Clock Registers store data in BCD. The Calibration Register stores data in Binary Format.
Table 2. TIMEKEEPER® Register Map
Addr
D7
D6
D5
D4
D3
D2
D1
D0
Function/Range BCD
Format
00h
ST
10 Seconds
Seconds
Seconds
00-59
01h
OF
10 Minutes
Minutes
Minutes
00-59
02h
CEB
CB
Hours (24 Hour Format)
Century/
Hours
0-1/00-23
03h
0
0
Day
01-7
04h
0
0
Date: Day of Month
Date
01-31
05h
0
0
Month
Month
01-12
Year
Year
00-99
06h
07h
10 Hours
0
10 Date
0
10 Years
OUT
0
FT
Keys: 0 = Must be set to '0'
CB = Century Bit
CEB = Century Enable Bit
FT = Frequency Test Bit
S
10M
0
Day of Week
Calibration
Calibration
OF = Oscillator Fail Bit
OUT = Output level
S = Sign Bit
ST = Stop Bit
11/23
M41T00S
Calibrating the Clock
The M41T00S is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The
devices are tested not exceed ±35 ppm (parts per
million) oscillator frequency error at 25oC, which
equates to about ±1.53 minutes per month (see
Figure 11., page 13). When the Calibration circuit
is properly employed, accuracy improves to better
than ±2 ppm at 25°C.
The oscillation rate of crystals changes with temperature. The M41T00S design employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure
12., page 13. The number of times pulses which
are blanked (subtracted, negative calibration) or
split (added, positive calibration) depends upon
the value loaded into the five Calibration Bits found
in the Calibration Register. Adding counts speeds
the clock up, subtracting counts slows the clock
down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Calibration Register 07h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the calibration register (see Figure
12., page 13). Assuming that the oscillator is run-
12/23
ning at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent
+10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes
per month.
Two methods are available for ascertaining how
much calibration a given M41T00S may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate reference and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934, “TIMEKEEPER ® CALIBRATION.” This allows the designer to
give the end user the ability to calibrate the clock
as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility
that accesses the Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the
FT/OUT pin. The pin will toggle at 512Hz, when
the Stop Bit (ST, D7 of 00h) is '0,' and the Frequency Test Bit (FT, D6 of 07h) is '1.'
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency Test output frequency.
The FT/OUT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500-10k resistor is recommended in order
to control the rise time. The FT Bit is cleared on
power-down.
M41T00S
Figure 11. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
∆F = K x (T – T )2
O
F
–80
2
2
K = –0.036 ppm/°C ± 0.006 ppm/°C
–100
TO = 25°C ± 5°C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI07888
Figure 12. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
13/23
M41T00S
Century Bit
Bits D7 and D6 of Clock Register 02h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn
of the century (depending upon its initial state). If
CEB is set to a '0,' CB will not toggle.
Oscillator Fail Detection
If the Oscillator Fail Bit (OF) is internally set to '1,'
this indicates that the oscillator has either stopped,
or was stopped for some period of time and can be
used to judge the validity of the clock and date data.
In the event the OF Bit is found to be set to '1' at
any time other than the initial power-up, the STOP
Bit (ST) should be written to a '1,' then immediately
reset to '0.' This will restart the oscillator.
The following conditions can cause the OF Bit to
be set:
– The first time power is applied (defaults to a '1'
on power-up).
– The voltage present on VCC is insufficient to
support oscillation.
– The ST Bit is set to '1.'
– External interference of the crystal.
The OF Bit will remain set to '1' until written to logic
'0.' The oscillator must start and have run for at
least 4 seconds before attempting to reset the OF
Bit to '0.'
Output Driver Pin
When the FT Bit is not set, the FT/OUT pin becomes an output driver that reflects the contents of
D7 of the Calibration Register. In other words,
when D7 (OUT Bit) and D6 (FT Bit) of address location 07h are a '0,' then the FT/OUT pin will be
driven low.
Note: The FT/OUT pin is an open drain which requires an external pull-up resistor.
Preferred Initial Power-on Default
Upon initial application of power to the device, the
ST and FT bits are set to a '0' state, and the OF
and OUT Bits will be set to a '1.' All other Register
bits will initially power-on in a random state (see
Table 3).
Table 3. Preferred Default Values
Condition
Initial Power-up(1)
Subsequent Power-up (with battery back-up)(2)
Note: 1. State of other control bits undefined.
2. UC = Unchanged
14/23
ST
Out
FT
OF
0
1
0
1
UC
UC
0
UC
M41T00S
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 4. Absolute Maximum Ratings
Sym
Parameter
TSTG
Storage Temperature (VCC Off, Oscillator Off)
VCC
Supply Voltage
TSLD
VIO
Lead Solder Temperature for 10 Seconds
Input or Output Voltages
Value
Unit
–55 to 125
°C
–0.3 to 7
V
Lead-free lead finish(1)
260
°C
Standard (SnPb)
lead finish(2,3)
240
°C
–0.3 to Vcc+0.3
V
SOIC
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. For SO8 package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
2. For SO8 package, standard (SnPb) lead finish: Reflow at peak temperature of 240°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
3. The SOX18 package has Lead-free (Pb-free) lead finish, but cannot be exposed to peak reflow temperature in excess of 240°C
(use same reflow profile as standard (SnPb) lead finish).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up Mode
15/23
M41T00S
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 5. Operating and AC Measurement Conditions
Parameter
M41T00S
Supply Voltage (VCC)
2.7 to 5.5V
Ambient Operating Temperature (TA)
–40 to 85°C
Load Capacitance (CL)
100pF
Input Rise and Fall Times
≤ 50ns
Input Pulse Voltages
0.2VCC to 0.8 VCC
Input and Output Timing Ref. Voltages
0.3VCC to 0.7 VCC
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 13. AC Measurement I/O Waveform
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Table 6. Capacitance
Parameter(1,2)
Symbol
CIN
COUT(3)
tLP
Max
Unit
7
pF
Output Capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
Input Capacitance
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
16/23
Min
M41T00S
Table 7. DC Characteristics
Sym
Test Condition(1)
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC1
Supply Current
Min
Typ
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
Switch Freq = 400kHz
300
µA
SCL = 0Hz
All Inputs
≥ VCC – 0.2V
≤ VSS + 0.2V
70
µA
ICC2
Supply Current (standby)
VIL
Input Low Voltage
–0.3
0.3VCC
V
VIH
Input High Voltage
0.7VCC
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 3.0mA
0.4
V
Output Low Voltage (Open Drain)(2)
IOL = 10mA
0.4
V
Pull-up Supply Voltage (Open Drain)
FT/OUT
5.5
V
3.5(4)
V
1
µA
VBAT(3)
Back-up Supply Voltage
IBAT
Battery Supply Current
Note: 1.
2.
3.
4.
2.0
TA = 25°C, VCC = 0V
Oscillator ON, VBAT = 3V
0.6
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
For FT/OUT pin (Open Drain)
STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
For rechargeable back-up, VBAT (max) may be considered to be VCC.
Table 8. Crystal Electrical Characteristics
Parameter(1,2)
Sym
fO
Resonant Frequency
RS
Series Resistance
CL
Load Capacitance
Min
Typ
Max
32.768
kHz
60(3)
12.5
Units
kΩ
pF
Note: 1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork
Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at [email protected] or http://www.kdsj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T00S. Circuit board layout considerations for the 32.768kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
3. For applications requiring back-up supply operation below 2.5V, RS (max) should be considered 40kΩ.
17/23
M41T00S
Figure 14. Power Down/Up Mode AC Waveforms
VCC
VSO
tPD
trec
SDA
SCL
DON'T CARE
AI00596
Table 9. Power Down/Up AC Characteristics
Parameter(1,2)
Symbol
Min
Typ
Max
Unit
tPD
SCL and SDA at VIH before Power Down
0
nS
trec
SCL and SDA at VIH after Power Up
10
µS
Note: 1. VCC fall time should not exceed 5mV/µs.
2. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
Table 10. Power Down/Up Trip Points DC Characteristics
Parameter(1,2)
Sym
Power-fail Deselect
VPFD
VSO
Hysteresis
Battery Back-up Switchover Voltage
(VCC < VBAT; VCC < VPFD)
Hysteresis
Min
Typ
Max
Unit
2.5
2.6
2.7
V
25
mV
VBAT < VPFD
VBAT
V
VBAT > VPFD
VPFD
V
40
mV
Note: 1. All voltages referenced to VSS.
2. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
18/23
M41T00S
Figure 15. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tHD:STA
tF
tR
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
SR
tSU:STO
P
AI00589
Table 11. AC Characteristics
Parameter(1)
Sym
Min
Typ
Max
Units
400
kHz
fSCL
SCL Clock Frequency
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
600
ns
0
tR
SDA and SCL Rise Time
300
ns
tF
SDA and SCL Fall Time
300
ns
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:DAT(2)
Data Setup Time
100
ns
tHD:DAT
Data Hold Time
0
µs
tSU:STO
STOP Condition Setup Time
600
ns
Time the bus must be free before a new
transmission can start
1.3
µs
tBUF
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
19/23
M41T00S
PACKAGE MECHANICAL INFORMATION
Figure 16. SO8 – 8-lead Plastic Small Package Outline
h x 45˚
A2
A
C
B
ddd
e
D
8
E
H
1
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 12. SO8 – 8-lead Plastic Small Outline (150 mils body width), Package Mech. Data
mm
inches
Symb
Typ
Min
Max
A
1.35
A1
Min
Max
1.75
0.053
0.069
0.10
0.25
0.004
0.010
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
–
–
–
–
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
α
0°
8°
0°
8°
N
8
e
ddd
20/23
1.27
Typ
0.050
8
0.10
0.004
M41T00S
PART NUMBERING
Table 13. Ordering Information Scheme
Example:
M41T
00S
M
6
E
Device Type
M41T
Supply Voltage and Write Protect Voltage
00S = VCC = 2.7 to 5.5V
Package
M = SO8
Temperature Range
6 = –40°C to 85°C
Shipping Method
For SO8:
E = Lead-free Package (ECO
PACK®), Tubes
F = Lead-free Package (ECO
PACK®), Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
21/23
M41T00S
REVISION HISTORY
Table 14. Document Revision History
Date
Version
Revision Details
February 10, 2004
0.1
First Draft
20-Feb-04
0.2
Update characteristics (Table 9, 10, 5, 7, 13)
14-Apr-04
1.0
Product promoted; reformatted; update characteristics, including Lead-free package
information (Figure 4. 11; Table 4. 11, 13)
05-May-04
1.1
Update DC Characteristics (Table 7)
16-Jun-04
1.2
Added package shipping (Table 13)
13-Sep-04
2.0
Update Maximum ratings (Table 4)
26-Nov-04
3.0
Promote document; update characteristics; remove references to SOX18 package
(Figure 1, 5; Table 14)
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22/23
M41T00S
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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23/23