M41T0 SERIAL REAL-TIME CLOCK FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ ■ 2.0 TO 5.5V CLOCK OPERATING VOLTAGE COUNTERS FOR SECONDS, MINUTES, HOURS, DAY, DATE, MONTH, YEARS, and CENTURY YEAR 2000 COMPLIANT I2C BUS COMPATIBLE (400kHz) LOW OPERATING CURRENT OF 130µA OPERATING TEMPERATURE OF –40 TO 85°C AUTOMATIC LEAP YEAR COMPENSATION SPECIAL SOFTWARE PROGRAMMABLE OUTPUT OSCILLATOR STOP DETECTION July 2004 Figure 1. 8-pin SOIC Packages 8 1 SO8 (M) TSSOP8 3x3 (DS) 1/20 M41T0 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. 8-pin SOIC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Figure 3. Table 1. Figure 4. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Figure 5. Table 4. Table 5. Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC Testing Input/Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Stop data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 8. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 7. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 9. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 10.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 12.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Oscillator Stop Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/20 M41T0 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13.SO8 – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Drawing16 Table 9. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 16 Figure 14.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 17 Table 10. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . 17 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3/20 M41T0 SUMMARY DESCRIPTION The M41T0 TIMEKEEPER® RAM is a low power Serial TIMEKEEPER with a built-in 32.768kHz oscillator (external crystal controlled). Eight registers are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a two-line bi-directional bus. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T0 is supplied in 8 lead Plastic Small Outline package. Figure 2. Logic Diagram Table 1. Signal Names VCC OSCI Oscillator Input OCSO Oscillator Output OUT Output Driver (Open Drain) SDA Serial Data Address Input / Output SCL Serial Clock NF(1) No Function VCC Supply Voltage VSS Ground OSCO OSCI M41T0 SCL SDA OUT VSS AI07028 Note: 1. NF pin must be tied to VSS. Figure 3. SOIC Connections M41T0 OSCI OSCO (1) NF VSS 1 2 3 4 8 7 6 5 AI07029 Note: 1. NF pin must be tied to VSS. 4/20 VCC OUT SCL SDA M41T0 Figure 4. Block Diagram 1 Hz OSCI OSCILLATOR 32.768 kHz SECONDS DIVIDER OSCO MINUTES OUT CENTURY/HOURS CONTROL LOGIC VCC VSS DAY DATE MONTH SCL SDA SERIAL BUS INTERFACE YEAR ADDRESS REGISTER CONTROL AI07030 5/20 M41T0 MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol Parameter TSTG Storage Temperature (VCC Off, Oscillator Off) VCC Supply Voltage TSLD(1) VIO Lead Solder Temperature for 10 Seconds Input or Output Voltages Value Unit –55 to 125 °C –0.3 to 7 V 260 °C –0.3 to VCC + 0.3 V IO Output Current 20 mA PD Power Dissipation 1 W Note: 1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 and 150 seconds). 6/20 M41T0 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. Operating and AC Measurement Conditions Parameter M41T0 Unit Supply Voltage (VCC) 2.0 to 5.5 V Ambient Operating Temperature (TA) –40 to 85 °C Load Capacitance (CL) 100 pF Input Rise and Fall Times ≤5 ns Input Pulse Voltages 0.2VCC to 0.8VCC V Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC V Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 5. AC Testing Input/Output Waveform 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI02568 Table 4. Capacitance Symbol CIN COUT(3) tLP Parameter(1,2) Min Max Unit Input Capacitance (SCL) 7 pF Output Capacitance (SDA, OUT) 10 pF Low-pass filter input time constant (SDA and SCL) 50 ns Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25°C, f = 1MHz. 3. Outputs deselected. 7/20 M41T0 Table 5. DC Characteristics Sym Test Condition(1) Parameter ILI Input Leakage Current ILO Output Leakage Current ICC1 Supply Current Min Typ Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA 3.0V 35 55 µA 5.5V 130 200 µA 3.0V 0.9 1.2 µA 31 µA Frequency (SCL) = 400kHz ICC2(2) Supply Current (Standby) All inputs = VCC – 0.2V Frequency (SCL) = 0Hz 5.5V VIL Input Low Voltage –0.3 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC + 0.3 V VOL Output Low Voltage IOL = 3mA 0.4 V Output Low Voltage (Open Drain) IOL = 10mA 0.4 V Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). 2. At 25°C. Table 6. Crystal Electrical Characteristics Symbol Parameter(1,2) fO Resonant Frequency RS Series Resistance CL Load Capacitance Min Typ Max 32.768 kHz 60(3) 12.5 Unit KΩ pF Note: 1. These values are externally supplied. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thruhole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at [email protected] or http://www.kdsj.co.jp for further information on this crystal type. 2. Load capacitors are integrated within the M41T0. Circuit board layout considerations for the 32.768kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. RS = 40kΩ when VCC ≤ 2.5V. 8/20 M41T0 OPERATION The M41T0 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: 1. Seconds Register 2. Minutes Register 3. Century/Hours Register 4. Day Register 5. Date Register 6. Month Register 7. Years Register 8. Control Register 2-Wire Bus Characteristics This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: – Data transfer may be initiated only when the bus is not busy. – During data transfer, the data line must remain stable whenever the clock line is High. Changes in the data line while the clock line is High will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy. Both data and clock lines remain High. Start data transfer. A change in the state of the data line, from High to Low, while the clock is High, defines the START condition. Stop data transfer. A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition. Data valid. The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition, a device that gives out a message is called “transmitter”, the receiving device that gets the message is called “receiver”. The device that controls the message is called “master”. The devices that are controlled by the master are called “slaves”. Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition. 9/20 M41T0 Figure 6. Serial Bus Data Transfer Sequence DATA LINE STABLE DATA VALID CLOCK DATA START CONDITION CHANGE OF DATA ALLOWED STOP CONDITION AI00587 Figure 7. Acknowledgement Sequence CLOCK PULSE FOR ACKNOWLEDGEMENT START SCLK FROM MASTER 1 DATA OUTPUT BY TRANSMITTER 2 8 MSB 9 LSB DATA OUTPUT BY RECEIVER AI00601 Figure 8. Bus Timing Requirements Sequence SDA tBUF tHD:STA tHD:STA tR tF SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR tSU:STO P AI00589 Note: P = STOP and S = START 10/20 M41T0 Table 7. AC Characteristics Parameter(1) Symbol Min Typ Max Unit 400 kHz fSCL SCL Clock Frequency tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 600 ns 0 tR SDA and SCL Rise Time 300 ns tF SDA and SCL Fall Time 300 ns tHD:STA START Condition Hold Time (after this period the first clock pulse is generated) 600 ns tSU:STA START Condition Setup Time (only relevant for a repeated start condition) 600 ns tSU:DAT Data Setup Time 100 ns tHD:DAT(2) Data Hold Time 0 µs STOP Condition Setup Time 600 ns Time the bus must be free before a new transmission can start 1.3 µs tSU:STO tBUF Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL. 11/20 M41T0 READ Mode In this mode, the master reads the M41T0 slave after setting the slave address (see Figure 9.). Following the WRITE Mode Control Bit (R/W = 0) and the Acknowledge Bit, the word address An is written to the on-chip address pointer. Next the START condition and slave address are repeated, followed by the READ Mode Control Bit (R/W = 1). At this point, the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Bit. The M41T0 slave transmitter will now place the data byte at address An+1 on the bus. The master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. An alternate READ Mode may also be implemented, whereby the master reads the M41T0 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 11., page 13). WRITE Mode In this mode the master transmitter transmits to the M41T0 slave receiver. Bus protocol is shown in Figure 12., page 13. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock. The M41T0 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see Figure 9.). Figure 9. Slave Address Location R/W SLAVE ADDRESS 1 A LSB MSB START 1 0 1 0 0 0 AI00602 12/20 M41T0 SLAVE ADDRESS DATA n+1 ACK DATA n ACK S ACK BUS ACTIVITY: R/W START WORD ADDRESS (An) ACK S R/W SDA LINE ACK BUS ACTIVITY: MASTER START Figure 10. READ Mode Sequence STOP SLAVE ADDRESS P AI00899 NO ACK DATA n+X STOP SLAVE ADDRESS P NO ACK BUS ACTIVITY: DATA n+X ACK DATA n+1 ACK DATA n ACK S ACK SDA LINE R/W BUS ACTIVITY: MASTER START Figure 11. Alternate READ Mode Sequence AI00895 SLAVE ADDRESS STOP DATA n+X P ACK DATA n+1 ACK BUS ACTIVITY: DATA n ACK WORD ADDRESS (An) ACK S ACK SDA LINE R/W BUS ACTIVITY: MASTER START Figure 12. WRITE Mode Sequence AI00591 13/20 M41T0 CLOCK OPERATION The M41T0 is driven by a quartz controlled oscillator with a nominal frequency of 32.768kHz. The accuracy of the Real-Time Clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The M41T0 is tested to meet ± 35 ppm with nominal crystal. The eightbyte Clock Register (see Table 8., page 15) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, Minutes, and Hours are contained within the first three registers. Bits D6 and D7 of Clock Register 2 (Hours Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2 of Register 3 contain the Day (day of week). Registers 4, 5 and 6 contain the Date (day of month), Month and Years. The final register is the Control Register. Bit D7 of Register 0 contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within four seconds (typically one second). The seven clock registers may be read one byte at a time, or in a sequential block. The Control Register (Address location 7) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. If a clock address is being read, an update of the clock registers will be delayed by 250ms to allow the READ to be completed before the update occurs. This will prevent a transition of data during the READ. 14/20 Note: This 250ms delay affects only the clock register update and does not alter the actual clock time. Output Driver Pin The OUT pin is an output driver that reflects the contents of D7 of the Control Register. In other words, when D7 of location 7 is a '0' then the OUT pin will be driven low. Note: The OUT pin is open drain which requires an external pull-up resistor. Oscillator Stop Detection If the Oscillator Fail (OF) Bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. This bit will be set to '1' any time the oscillator stops. The following conditions can cause the OF Bit to be set: – The first time power is applied (defaults to a '1' on power-up). – The voltage present on VCC is insufficient to support oscillation. – The ST Bit is set to '1.' – External interference or removal of the crystal. This bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4 seconds before attempting to reset the OF Bit to '0.' This function operates both under normal power and in battery back-up. Initial Power-on Defaults Upon initial application of power to the device, the OUT Bit and OF Bit will be set to a '1,' while the ST Bit will be set to '0.' All other Register bits will initially power-on in a random state. M41T0 Table 8. Register Map Data Address D7 D6 D5 D4 D3 D2 D1 D0 Function/Range BCD Format 0 ST 10 Seconds Seconds Seconds 00-59 1 OF 10 Minutes Minutes Minutes 00-59 2 CEB (1) CB Hours Century/Hours 0-1/00-23 3 X X Day 01-07 4 X X Date Date 01-31 5 X X Month Month 01-12 Years Year 00-99 6 7 10 Hours X X X Day 10 Date X 10 M. 10 Years OUT Keys: ST = STOP Bit OUT = Output level X = Don’t care 0 = Must be set to '0.' 0 X X X X X X Control CEB = Century Enable Bit CB = Century Bit OF = Oscillator Fail Bit Note: 1. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). When CEB is set to '0', CB will not toggle. 15/20 M41T0 PACKAGE MECHANICAL INFORMATION Figure 13. SO8 – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Drawing h x 45˚ A2 A C B ddd e D 8 E H 1 A1 α L SO-A Note: Drawing is not to scale. Table 9. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data mm inches Symb Typ Min Max Typ Min Max A – 1.35 1.75 – 0.053 0.069 A1 – 0.10 0.25 – 0.004 0.010 B – 0.33 0.51 – 0.013 0.020 C – 0.19 0.25 – 0.007 0.010 D – 4.80 5.00 – 0.189 0.197 ddd – – 0.10 – – 0.004 E – 3.80 4.00 – 0.150 0.157 e 1.27 – – 0.050 – – H – 5.80 6.20 – 0.228 0.244 h – 0.25 0.50 – 0.010 0.020 L – 0.40 0.90 – 0.016 0.035 α – 0° 8° – 0° 8° N 16/20 8 8 M41T0 Figure 14. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline D 8 5 c E1 1 E 4 α L A1 A A2 L1 CP b e TSSOP8BM Note: Drawing is not to scale. Table 10. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data mm inches Symb Typ Min Max Typ Min Max A – – 1.10 – – 0.043 A1 – 0.05 0.15 – 0.002 0.006 A2 0.85 0.75 0.95 0.034 0.030 0.037 b – 0.25 0.40 – 0.010 0.016 c – 0.13 0.23 – 0.005 0.009 CP – – 0.10 – – 0.004 D 3.00 2.90 3.10 0.118 0.114 0.122 e 0.65 – – 0.026 – – E 4.90 4.65 5.15 0.193 0.183 0.203 E1 3.00 2.90 3.10 0.118 0.114 0.122 L 0.55 0.40 0.70 0.022 0.0160.028 0.030 L1 0.95 – – 0.037 – – α – 0° 6° – 0° 6° N 8 8 17/20 M41T0 PART NUMBERING Table 11. Ordering Information Scheme Example: M41T 0 M 6 T Device Type M41T Supply Voltage and Write Protect Voltage 0 = VCC = 2.0 to 5.5V Package M = SO8 (150mils width) DS = TSSOP8 Temperature Range 6 = –40 to 85°C Shipping Method blank = Tubes (Not for New Design - Use E) E = Lead-Free Package (ECO PACK®), Tubes F = Lead-Free Package (ECO PACK®), Tape & Reel T = Tape & Reel (Not for New Design - Use F) For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 18/20 M41T0 REVISION HISTORY Table 12. Document Revision History Date Rev. # Revision Details February 2003 1.0 First Issue 18-Feb-03 1.1 Add Pb-Free information (Table 2., Table 11.); update package information (Figure 1., Figure 14.; Table 11.) 01-Apr-03 1.2 Fix package outline and data (Figure 1., Figure 14., Table 10., Table 11.) 10-Apr-03 1.3 Revert to previous package (Figure 1., Figure 14., Table 10., Table 11.) 30-Oct-03 1.4 Remove footnote (Table 2.) 30-Jun-2004 2.0 Shipping Method options updated and Note 1 removed from Table 11., Ordering Information Scheme. Datasheet put in new template. 23-Jul-2004 3.0 Content corrected from M41T80 to M41T0. 19/20 M41T0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 20/20